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Published SFF-TA-1009 Rev 3.0 SFF-TA-1009 Specification for Enterprise and Datacenter Standard Form Factor Pin and Signal Specification Rev 3.0 March 19, 2021 SECRETARIAT: SFF TA TWG This specification is made available for public review at https://www.snia.org/sff/specifications. Comments may be submitted at https://www.snia.org/feedback. Comments received will be considered for inclusion in future revisions of this specification. This specification provides a common reference for host systems manufacturers, host system integrators, and device suppliers. This specification originates from Enterprise and Datacenter SSD Form Factor Working Group (EDSFF). With non-SSD devices also using EDSFF and agreement from the EDSFF Working Group, the SFF TA TWG changed EDSFF to Enterprise and Datacenter Standard Form Factor. The description of the details in this specification does not assure that the specific component is available from device suppliers. If such a device is supplied it shall comply with this specification to achieve interoperability between device suppliers. ABSTRACT: This specification defines the pin list and pin placement, function of the pins, device specific electrical requirements, and specific features of enterprise and datacenter-based devices. This specification relies on SFF-TA-1002 for the connector mechanicals and SFF-TA-1006, SFF-TA-1007, and SFF-TA- 1008 form factor specifications for the form factor mechanicals. POINTS OF CONTACT: Anthony Constantine Chairman SFF TA TWG Intel Corporation Email: [email protected] 2111 NE 25th Ave, MS JF5-270 Hillsboro, OR 97124 Ph: 971 215 1128 Email: [email protected] Enterprise and Datacenter Standard Form Factor Pin and Signal Specification Page 1 Copyright © 2021 SNIA. All rights reserved. Published SFF-TA-1009 Rev 3.0 Intellectual Property The user's attention is called to the possibility that implementation of this specification may require the use of an invention covered by patent rights. By distribution of this specification, no position is taken with respect to the validity of a claim or claims or of any patent rights in connection therewith. This specification is considered SNIA Architecture and is covered by the SNIA IP Policy and as a result goes through a request for disclosure when it is published. Additional information can be found at the following locations: • Results of IP Disclosures: https://www.snia.org/sffdisclosures • SNIA IP Policy: https://www.snia.org/ippolicy Copyright The SNIA hereby grants permission for individuals to use this document for personal use only, and for corporations and other business entities to use this document for internal use only (including internal copying, distribution, and display) provided that: 1. Any text, diagram, chart, table or definition reproduced shall be reproduced in its entirety with no alteration, and, 2. Any document, printed or electronic, in which material from this document (or any portion hereof) is reproduced shall acknowledge the SNIA copyright on that material, and shall credit the SNIA for granting permission for its reuse. Other than as explicitly provided above, there may be no commercial use of this document, or sale of any part, or this entire document, or distribution of this document to third parties. All rights not explicitly granted are expressly reserved to SNIA. Permission to use this document for purposes other than those enumerated (Exception) above may be requested by e-mailing [email protected]. Please include the identity of the requesting individual and/or company and a brief description of the purpose, nature, and scope of the requested use. Permission for the Exception shall not be unreasonably withheld. It can be assumed permission is granted if the Exception request is not acknowledged within ten (10) business days of SNIA's receipt. Any denial of permission for the Exception shall include an explanation of such refusal. Disclaimer The information contained in this publication is subject to change without notice. The SNIA makes no warranty of any kind with regard to this specification, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The SNIA shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing, performance, or use of this specification. Suggestions for revisions should be directed to https://www.snia.org/feedback/. Enterprise and Datacenter Standard Form Factor Pin and Signal Specification Page 2 Copyright © 2021 SNIA. All rights reserved. Published SFF-TA-1009 Rev 3.0 Foreword The development work on this specification was done by the SNIA SFF TWG, an industry group. Since its formation as the SFF Committee in August 1990, the membership has included a mix of companies which are leaders across the industry. For those who wish to participate in the activities of the SFF TWG, the signup for membership can be found at https://www.snia.org/sff/join. Revision History Rev 1.0 March 23, 2018: - Initial release Rev 2.0 May 22, 2018: - Change to TX/RX ordering and changed table orientation for tables 4-4, 4-5, and 4-6. - Clarification to power sequencing requirements (section 5.2). - Update to unused reference clock guidance (section 4.2.2). - Minor editorial and formatting changes throughout document. Rev 3.0 March 19, 2021: - Name change to Enterprise and Datacenter Standard Form Factor - Revised to new format used in SFF - Updated Revision of reference documents - Editorial cleanup throughout document - Minor clarifications made throughout document - Power and Grounds: Additional requirements and expectations added to power sequencing - PCIe signals: Clarifications made to PCIe single port mode below x4 - CLKREQ: Clarifications made to CLKREQ# and PERST1# behavior in relation to DUALPORTEN# - Addition of Pull-up/Pull-down locations and values to signals requiring Pull-up/Pull-down - SMBus: Clarification on device and host pull-ups - SMBRST#: Clarifications made to SMBRST behavior - DUALPORTEN#: Replaced table on dual port vs. single port usage with simpler definition - LED/ACTIVITY: ACTIVITY portion removed. Spec will no longer support the use of ACTIVITY - Errata fix in tables 4-4, 4-5, and 4-6 to rename LED#/Activity to LED to match functional definition along with title of these tables. Changed 3.3 VAux to 3.3 Vaux - 12V supply requirements: Added new requirements for Max sustained power, Initial power, max power, and slew rate - 3.3 Vaux supply requirements: Clarified measurement time for current. - Timing requirements: Added specs for SMBRST#, PWRDIS de-assertion time and PERST to 12V power - 3.3V Logic signaling: Added SMBus to signals covered and its operating voltage, a new Vil for LEDs, updated leakage currents, and added notes. - Added Amber/Blue LED for SFF-TA-1008 along with description, values, and example schematics - LED Requirements: relaxed wavelength and point intensity ranges - Clarified Amber LED usage for SFF-TA-1006 and SFF-TA-1007 - Section 8 added for Electrical Requirements including S-parameters and eye masks Enterprise and Datacenter Standard Form Factor Pin and Signal Specification Page 3 Copyright © 2021 SNIA. All rights reserved. Published SFF-TA-1009 Rev 3.0 - Contents 1. Scope 6 1.1 Application Specific Criteria 6 2. References and Conventions 6 2.1 Industry Documents 6 2.2 Sources 6 2.3 Conventions 7 3. Keywords, Acronyms, and Definitions 8 3.1 Keywords 8 3.2 Acronyms and Abbreviations 8 3.3 Definitions 9 4. General Description 10 5. Signal List 11 5.1 Power and Grounds 12 5.2 PCIe Signals 13 5.2.1 High Speed Signals (PERp/n, PETp/n) 13 5.2.2 Reference Clock 14 5.2.3 PERST# 15 5.2.4 CLKREQ# 15 5.3 Sideband Signals 15 5.3.1 PRSNT[0..2]# 15 5.3.2 SMBus Interface 15 5.3.3 SMBRST# 16 5.3.4 DUALPORTEN# 16 5.3.5 LED 16 5.3.6 PWRDIS 16 5.3.7 MFG 16 5.3.8 RFU 17 5.4 Connector pinout definitions 17 6. Electrical Requirements 23 6.1 Power Supply Requirements 23 6.2 Timings 24 6.3 3.3 V Logic Signal Requirements 24 7. LEDs 26 7.1 Green LED 26 7.2 Amber LED (SFF-TA-1006 and SFF-TA-1007) 26 7.3 Amber/Blue LED (SFF-TA-1008) 26 8. PCIe Electrical Requirements 28 8.1 Signal Integrity Requirements 28 8.1.1 Insertion Loss (IL) 29 8.1.2 Return Loss (RL) 29 8.1.3 Power Sum Near End Crosstalk (PSNEXT) 29 8.1.4 Power Sum Far End Crosstalk (PSFEXT) 30 8.2 Transmitter and Receiver Sensitivity Eye Limits 31 8.2.1 EDSFF Device Transmitter Eye Mask 31 8.2.2 EDSFF Host Transmitter Eye Mask 31 8.2.3 EDSFF Device Receiver Minimum Sensitivity 32 8.2.4 EDSFF Host Receiver Minimum Sensitivity 32 8.3 Test Fixtures 32 Enterprise and Datacenter Standard Form Factor Pin and Signal Specification Page 4 Copyright © 2021 SNIA. All rights reserved. Published SFF-TA-1009 Rev 3.0 Figures Figure 5-1. PET and PER Signal Connectivity Between Host and Device 13 Figure 6-1. EDSFF Device Timing Diagram for PWRDIS 24 Figure 7-1. Example Schematic for Controlling the Blue/Amber LED (Common Cathode) 27 Figure 7-2. Example Schematic for Controlling the Blue/Amber LED (Common Anode) 27 Figure 8-1. EDSFF Electrical Requirements Coverage 28 Figure 8-2. Example of Circuit Contributions to Insertion Loss and Return Loss 29 Figure 8-3. Example of PSNEXT Test Configuration for Device 30 Figure 8-4. Example of PSFEXT Victim and Aggressors 30 Figure 8-5. Eye Diagram for EDSFF Device Transmitter 31 Figure 8-6. Eye Diagram for EDSFF Host Transmitter 31 Tables Table 5-1. EDSFF Connector Pin List 11 Table 5-2.
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