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Overview of 3-D Architecture Design Opportunities and Techniques Tutorial Overview of 3-D Architecture Design Opportunities and Techniques Jishen Zhao Yuan Xie University of California Santa Cruz University of California Santa Barbara Qiaosha Zou Huawei Technologies Co. Ltd. First, the reduced interconnect Editor’s note: wire length and the declined number Three-dimensional (3-D) integration, a breakthrough technology to achieve of global signals can directly reduce “More Moore and More Than Moore,” provides numerous benefits, e.g., the circuit delay and system power higher performance, lower power consumption, and higher bandwidth, by dissipation. A variety of previous stud- utilizing vertical interconnects and die/wafer stacking. This paper presents ies [1] have demonstrated that the an overview of 3-D integration along with various design challenges and reduced wire length can lead to up to recent innovations. 30% delay reduction in 3-D arithmetic —Partha Pande, Washington State University unit design. In addition, the reduction in wire length, repeaters, and repeat- ing latches can be translated into power reduc- THREE-DIMENSIONAL INTEGRATION may refer to tion due to the reduced parasitics with the shorter various technologies that share a common salient wire length and incorporating previously off-chip feature: they integrate two or more dies of active signals to be on-chip. For example, Ouyang et devices in a single circuit. Compared to traditional al. [1] demonstrated 3-D-stacked arithmetic units 2-D integration technologies, 3-D integration replaces with up to 46% power saving compared with long, global wires (with massive repeaters) with 2-D designs. short, vertical or horizontal interconnects. Looking Second, 3-D integration enables high-band- further out, 3-D integration introduces a few benign width memory (HBM) due to the wide bus width effects that are likely to innovate computer architec- between the processor and the integrated memory. ture design in a nontraditional manner. It releases the constraint of off-chip pin counts, and therefore can dramatically increase memory Digital Object Identifier 10.1109/MDAT.2015.2463282 bandwidth by an order of magnitude. For example, Date of publication: 31 July 2015; date of current version: Microns hybrid memory cube (HMC) [2] can offer 30 June 2017. up to 160-GB/s bandwidth with a 2-GB capacity. 60 2168-2356/15 © 2015 IEEE Copublished by the IEEE CEDA, IEEE CASS, IEEE SSCS, and TTTC IEEE Design&Test Today, memory bandwidth is a fundamental perfor- raised by adopting 3-D integration technologies, mance bottleneck. Modern applications typically such as thermal issue which is imposed by dense adopt large memory working set and increasingly integration of active electronic devices, the cost larger number of threads which can simultane- issues which is incurred by extra process and ously access the memory. By offering high mem- increased die area, and the opportunity in designing ory bandwidth, 3-D integration can substantially cost-effective microprocessor architectures. From change the way memory hierarchy is designed the industry prospective, 3-D integrated memory is to support high-performance and energy-efficient envisioned to become pervasive in the near future. data movement. Intel's Xeon Phi processors are delivered with 3-D Third, 3-D integration allows different circuit lay- stacked DRAMs [5]. ers to be implemented by different and incompat- In this article, we overview recent novel com- ible process technologies, enabling heterogeneous puter architecture designs enabled by 3-D integra- integration. It enables feasible and cost-effective tion technologies. We will start from introducing architecture designs composed of heterogeneous the basis of various 3-D integration technologies. technologies to achieve the More than More technol- We will then review recent 3-D integrated com- ogy projected by International Technology Roadmap puter architecture designs, including 3-D-stacked for Semiconductors (ITRS) in future microproces- multicore processor design, integrated HBM and sors. For example, 3-D integration allows optical hybrid memory design, and 3-D NoC design. We devices to be integrated closely with digital circuits will also discuss recent studies that investigate ther- with new architecture designs [3]. Three-dimensional mal and cost issued concerned with 3-D integrated integration also allows novel computer archi- architectures. tectures to be developed such as hybrid proces- sor cache and memory hierarchy design. Various Three-dimensional integration memory technologies, such as SRAM, spin-trans- technologies fer torque RAM (STT-RAM), phase-change mem- Based on fabrication processes and media of ver- ory (PCM), and resistive RAM (ReRAM) trade off tical interconnects, 3-D integration technologies can between performance, power, density, imple- be roughly categorized as through-silicon-via (TSV)- mentation complexity, and cost. A hybrid mem- based, monolithic, and contactless 3-D integration. ory hierarchy incorporated with various memory TSV-based 3-D integration (Figure 1a) adopts sev- technologies can be optimized for all metrics [4]. eral active device layers, which can be fabricated Three-dimensional integration is a critical technol- in parallel. These layers are then vertically stacked ogy that enables such hybrid memory hierarchy together to form a single integrated circuit (IC). designs. Typically, TSVs are directly formed in each upper Fourth, 3-D integration enables much condensed tier before the stacking for vertical interconnect. form factor compared to traditional 2-D integration Therefore, performance of TSVs largely affects the technologies. Due to the addition of a third dimen- yield of 3-D ICs. Steps of 3-D fabrication are differ- sion to conventional 2-D layout, it leads to a higher ent from those of 2-D counterparts mainly due to the packing density and smaller footprint. This poten- formation of TSVs. In general, four additional steps tially leads to processor designs with lower cost. are necessary for 3-D integration, namely etching, As such, both academic and industry communi- thinning, alignment, and bonding [6]. In terms of ties abound with research studies that examine the the bonding orientation, we can classify the bonding rich architectural space enabled by 3-D integration, into face-to-back (F2B) and face-to-face (F2F) bond- since its debut decades ago. From the academia ing methods. F2F bonding enables higher intercon- prospective, comprehensive studies have been nect density via CuCu bonding on the top metal layer performed across all aspects of microprocessor and results in no silicon area overhead for interlayer architecture design by employing 3-D integration signals. In contrast, due to the alignment precision technologies, such as 3-D-stacked processor core and the interconnect size, the interconnect density and cache architectures, 3-D integrated memory, 3-D in F2B is relatively smaller. Three different stacking network-on-chip (NoC). Furthermore, a large body strategies can be achieved: wafer-to-wafer (W2W), of research studied critical issues and opportunities die-to-wafer (D2W), and die-to-die (D2D) stacking. July/August 2017 61 Tutorial such as field mobility and threshold voltage; second, building upper planes cannot compromise the elec- trical performance of the bottom layer. By employ- ing sequential fabrication process, monolithic 3-D ICs allow the pitch of vertical interconnects smaller than TSVs. Therefore, monolithic 3-D integration technology enables finer grained stacking at gate level or even transistor level. Contactless 3-D integration employs coupling of electric or magnetic fields to perform the interlayer communication with a comparable data rate as TSVs. Based on the coupling principle, contactless 3-D inte- gration can be further categorized into capacitively and inductively coupled 3-D integration [8]. The major benefit of contactless 3-D integration is that the fabrication process is compatible with 2-D processes. However, the inductors and capacitors can dissipate certain amount of power. For example, although the inductive coupling can consume only 0.14 pJ/b, the Figure 1. A conceptual view of parallel 3-D energy consumption of the inductors is continuous, integration. wasting significant amount of power [9], [10]. Comparison of 3-D integration technologies: The major difference among these three is whether Compared to TSV-based 3-D integration, monolithic to slice the wafer into dice before stacking. For W2W integration can lead to up to 8% smaller area due stacking, wafers are bonded before sliced into dice. to smaller size of intertier via than the TSVs, 12% This process has the highest productivity yet the low- lower longest path delay, and 7% lower power [7]. est compound yield. Testings are required for D2W Nevertheless, implementing monolithic 3-D ICs and D2D stacking and only known-good dies (KGDs) requires nontrivial changes to conventional fabri- are selected for bonding. Therefore, the compound cation process, making it less practical compared yield is increased by preventing bad dies from stack- to the TSV-based approach. One of major issues ing on good ones. with contactless transmissions is the significant To reduce the manufacturing complexity and metal area consumption introduced by coils and fabrication cost, recent 3-D IC designs employ an metal plates, especially when high transmission alternative integration technique, interposer-based integration techniques, which is also known as 2.5-D integrated circuits (Figure 1b). Interposer is
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