ECEN 325 Lab 8: BJT Amplifier Configurations
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ECEN 325 Lab 8: BJT Amplifier Configurations Objectives The purpose of the lab is to examine the properties of the BJT amplifier configurations and investigate their small- signal performance, with the emphasis on the design of BJT amplifiers. Introduction Superposition Theorem - Linear and Nonlinear Circuit Solution The superposition theorem states that in a linear circuit with multiple sources, any branch current or node voltage is the sum of the currents or voltages produced by each source applied individually. Linear components include resistors, capacitors, inductors, and controlled sources, therefore any combination of these elements yield a linear circuit. Figure 1 shows the application of superposition theorem to solve linear circuits, where the DC and AC solutions are obtained by applying only DC and AC sources, respectively, providing the total solution as Vo = Vo,dc + Vo,ac . VCC VCC Linear Circuit Vo Linear CircuitVo,dc Linear Circuit Vo,ac Vi Vi −VEE −VEE Figure 1: Application of the superposition theorem to linear circuits The superposition theorem can be extended to solve nonlinear circuits under certain restrictions, which are known as small-signal conditions. The DC solution usually requires using simplified DC models for the nonlinear devices (such as using the constant-voltage-drop model for a diode or a base-emitter junction, instead of the exponential model), and can be obtained by applying only DC sources. AC small-signal model parameters are dependent on the DC solution, as well as other device parameters. Once the linearized circuit using AC small-signal models is constructed, AC solution can be obtained by applying only AC sources. Figure 2 illustrates extension of the superposition theorem to nonlinear circuits, where the approximate solution is Vo ≈ Vo,dc + Vo,ac . VCC VCC Nonlinear Circuit Linearized Circuit Nonlinear Circuit V V V o Simplified DC Models o,dc Small−signal AC Models o,ac Vi Vi −VEE −VEE Figure 2: Extension of the superposition theorem to nonlinear circuits BJT Small-Signal AC models BJTs are nonlinear devices, where the collector current is an exponential function of the base-emitter voltage. Typical BJT amplifiers include DC sources providing the DC bias, as well as AC sources as the signals to be amplified. Extension of superposition to BJT amplifiers requires finding the DC solution first, where the BJTs must be biased in the active region. Figure 3 shows the AC small-signal models for NPN and PNP BJTs in the active region. © Department of Electrical and Computer Engineering, Texas A&M University 1 C E iC iE B NPN B PNP iB iB iE iC E C π model T model π model T model C E E ib ic ie B C α ie re ie rπ vbe gm vbe r o B r r v g v o π eb m eb ro B ro re ie ie B C α i i i e E b c E C Figure 3: Small-signal AC models for NPN and PNP BJTs Small-signal parameters in Fig. 3 can be calculated as IC β VT β VA gm = rπ = re = α = ro = (1) VT gm IE β + 1 IC where IC and IE are DC collector and emitter currents, respectively, VT is the thermal voltage (approximately 25mV at room temperature), β is the current gain of the transistor (around 100 or larger), and VA is the Early Voltage (around 100V). For typical discrete BJT circuit implementations, ro will not have a significant impact, therefore will be ignored. For small-signal AC analysis, π-model and T-model provide identical results, however the T-model allows more intuitive analysis with simpler calculations. Table 1 shows node impedances and node-to-node gains for generic BJT configurations, which are derived by substituting the transistor with its T-model, where ro = 1. Table 1: BJT Node Impedances and Node-to-Node Gains when ro = 1 NPN PNP Impedance NPN PNP Gain ZC ZE ZC ZE vc vc −αZC Zbase =(β+1)(re+ZE ) vb vc = v vb re + ZE Z Z b base Z base Z E C ZE ZC Zemitter Z C ve ZC vc ZB v vc αZC Z =r + ZB c = ZB emitter e β+1 v Z Z e emitter ZB ZC B Z ve C Zemitter Zcollector ZE ZE v v ve b e v Z e = E ZB Zcollector =1 v r + Z Z ZE b e E E ZB vb Zcollector 2 BJT Amplifier Configurations Common-Emitter Configuration Figures 4 and 5 show the common-emitter configurations for NPN and PNP BJTs, respectively. Analysis of this configuration yields RB2 VRE DC : VRB2 ≈ VCC VRE = VRB2 − 0.7 IE = ≈ IC (2) RB1 + RB2 RE Vo,ac RC AC : Av = ≈ − Ri = RB1 k RB2 k (β + 1)(re + (RE k RG )) Ro = RC (3) Vi re + (RE k RG ) VCC VCC V RB1 RC RB1 RC RC RC Vo Vo,dc Ri Vo,ac Ro Vi Vi RB V V RB2 RE RG RB2 RB2 RE RE RE ||RG (a) (b) (c) Figure 4: (a) NPN Common-Emitter Configuration (b) DC equivalent (c) AC equivalent VCC VCC RB2 RE RG RB2 VRB2 VRE RE RE ||RG Ri Ro Vi Vo Vo,dc Vi RB Vo,ac V RB1 RC RB1 RC RC RC (a) (b) (c) Figure 5: (a) PNP Common-Emitter Configuration (b) DC equivalent (c) AC equivalent Typical design specifications for the common-emitter configuration includes: • 0-to-peak unclipped output voltage swing: V^o Vo,ac • Voltage gain: Av = Vi • Input and output resistances: Ri and Ro • THD at the maximum output level • Sensitivity to β and jVBE j variations Based on the typical specifications, design procedure for the common-emitter amplifier in Figs. 4 and 5 can be given as follows: µ Choose VRE ≥ 1V to have less than 10% variation of IC when VBE = 0.7 ± 0.1. µ To have an unclipped output swing of V^o , VRC should be chosen such that (VCC −V^o −VRE −0.2) ≥ VRC ≥ V^o . Choice of VRC does not only affect the available signal swing at the output, but also determines the available gain as well as the linearity of the amplifier as follows: 3 RC VRC =IC VRC VRC,max VCC − V^o − VRE − 0.2 P RG = 0 ) jAv j = = = ) jAv jmax = = re VT =IC VT VT VT V^o P Small-signal condition: v^be = VT VT ) V^o VRC VRC To maximize the available gain and linearity, choose VRC = VRC,max = VCC − V^o − VRE − 0.2 Note that VCE,sat ≈ 0.2V is an approximation, you may increase it up to 0.5V to avoid clipping in case operat- ing point shifts due to resistor tolerances. µ Choose IC such that β 1 I ≤ C R N N jA j i + + v VRE + 0.7 VCC − VRE − 0.7 VRC IRB1 where Ri is the minimum input resistance specified, and N ≈ ≥ 10 for β-insensitive design. IB Note that as long as VRC and VRE are kept the same, choice of IC does not change the output swing or the available gain, but affects the input and output resistances, as well as the resistor values in the amplifier. µ Find the resistor values VRC VRE RC β(VCC − VRE − 0.7) β(VRE + 0.7) RC = RE = RG ≈ − re RB1 = RB2 = IC IC jAv j NIC NIC µ Simulate the circuit for the final adjustment of RG . Common-Collector Configuration Figures 6 and 7 show the common-collector configurations for NPN and PNP BJTs, respectively. Also known as the emitter-follower, analysis of this configuration yields RB2 VRE DC : VRB2 ≈ VCC VRE = VRB2 − 0.7 IE = ≈ IC (4) RB1 + RB2 RE Vo,ac RE AC : Av = = Ri = RB1 k RB2 k (β + 1)(re + RE ) Ro = RE k re (5) Vi re + RE VCC VCC RB1 RB1 Ri Ro Vi Vo Vo,dc Vi RB Vo,ac V V RB2 RE RB2 RB2 RE RE RE (a) (b) (c) Figure 6: (a) NPN Common-Collector (Emitter-Follower) Configuration (b) DC equivalent (c) AC equivalent VCC VCC V V RB2 RE RB2 RB2 RE RE RE Vo Vo,dc Ri Vo,ac Ro Vi RB1 RB1 Vi RB (a) (b) (c) Figure 7: (a) PNP Common-Collector (Emitter-Follower) Configuration (b) DC equivalent (c) AC equivalent In typical multi-stage amplifiers, emitter follower is directly connected to a gain stage, such as a common-emitter amplifier, without the extra biasing resistors RB1 and RB2. Therefore, DC voltage levels in an emitter follower is typically dependent on the previous amplifier stage. 4 Common-Base Configuration Figures 8 and 9 show the common-base configurations for NPN and PNP BJTs, respectively. Analysis of this con- figuration yields RB2 VRE DC : VRB2 ≈ VCC VRE = VRB2 − 0.7 IE = ≈ IC (6) RB1 + RB2 RE Vo,ac RC AC : Av = = Ri = RE k re Ro = RC (7) Vi re VCC VCC V RB1 RC RB1 RC RC RC Ro Vo Vo,dc Vo,ac Ri V V RB2 RE Vi RB2 RB2 RE RE RE Vi (a) (b) (c) Figure 8: (a) NPN Common-Base Configuration (b) DC equivalent (c) AC equivalent VCC VCC V V RB2 RE RB2 RB2 RE RE RE Ri Vi Ro Vi Vo Vo,dc Vo,ac R B1 V RB1 RC RC RC RC (a) (b) (c) Figure 9: (a) PNP Common-Base Configuration (b) DC equivalent (c) AC equivalent Common-base stages are typically used in cascode or folded-cascode amplifiers, where a common-base stage is directly following a common-emitter amplifier. Calculations 1. Design the common-emitter amplifier in Fig.