Europäisches Patentamt *EP001282072A1* (19) European Patent Office

Office européen des brevets (11) EP 1 282 072 A1

(12) EUROPEAN PATENT APPLICATION

(43) Date of publication: (51) Int Cl.7: G06K 19/073, G11C 5/14, 05.02.2003 Bulletin 2003/06 G11C 16/30, G05F 1/618, H02M 3/158 (21) Application number: 02017155.9

(22) Date of filing: 30.07.2002

(84) Designated Contracting States: (72) Inventor: Takabayashi, Yasutaka, AT BE BG CH CY CZ DE DK EE ES FI FR GB GR c/oOki Electric Ind. Co.Ltd IE IT LI LU MC NL PT SE SK TR Tokyo (JP) Designated Extension States: AL LT LV MK RO SI (74) Representative: Betten & Resch Patentanwälte, (30) Priority: 30.07.2001 JP 2001229374 Theatinerstrasse 8 80333 München (DE) (71) Applicant: Oki Electric Industry Co., Ltd. Tokyo (JP)

(54) regulator and semiconductor

(57) A includes a constant current ing through the load is larger than the constant current circuit which is connected between an input node with and a second which is provided between the which a voltage is supplied and an output output node and a common potential node and which node to which a load is connected and which supplies flows surplus current to the common potential node constant current to the output node. The voltage regu- when current flowing through the load is less than the lator also includes a first transistor which is provided in constant current. The voltage regulator also includes a parallel to the constant current circuit and which flows control circuit which controls a conductive state of the additional current to the output node when current flow- first and the second so that an output voltage of the output node is maintained at constant voltage. EP 1 282 072 A1

Printed by Jouve, 75001 PARIS (FR) 1 EP 1 282 072 A1 2

Description the ground potential GND. [0008] In this voltage regulator, the voltage VREG at BACKGROUND OF THE INVENTION the output node N1 is divided by the R1 and the resistor R2 and is applied to the non-inverted input ter- FIELD OF THE INVENTION 5 minal ᮀof the amplification circuit A as the comparison voltage VC (=VREGxR2/(R1+R2)). The voltage regula- [0001] The present invention generally relates to a tor receives the voltage VREG at the output node N1 voltage regulator used for Integrated Circuit Card and a and the reference voltage VR applied to the inverted in- semiconductor integrated circuit (it is called simply IC put terminal ᮀ of the amplification circuit A, and com- hereinafter). 10 pares and amplifies the voltage difference between the [0002] This application relies for priority on Japanese voltage VC and the voltage VR. patent application, Serial Number 229374/2001, filed [0009] Therefore, if the comparison voltage VC is July 30, 2001, which is incorporated herein by reference higher than the reference voltage VR, the output voltage in its entirety. VO of the amplification circuit A goes high, internal re- 15 sistance (resistance between a source and a drain) of DESCRIPTION OF THE RELATED ART the transistor M1 increases, and the voltage VREG of the output node N1 falls. Conversely, if the comparison [0003] Fig. 2 is a system configuration figure showing voltage VC is lower than the reference voltage VR, the an example of an integrated circuit card. This integrated output voltage VO of the amplification circuit A becomes circuit card has the internal logic part 2. This internal 20 low, internal resistance of the transistor M1 decreases, logic part 2 has EEPROM 1 (it is a nonvolatile memory and the voltage VREG of the output node N1 goes up. which can electrically erase data stored therein), and [0010] By the above feedback operation, the voltage CPU () and ROM.. The EEP- VREG of the output node N1 is stabilized in the state ROM 1 is a memory for memorizing data, such as per- where the comparison voltage VC coincides with the ref- sonal information. The CPU is the equipment for per- 25 erence voltage VR. Therefore, it becomes VREG=VRx forming data processing. (1+R1/R2). In addition, since voltage change of the out- [0004] Furthermore, this integrated circuit card has a put node N1 by the feedback operation returns to the band gap 4 and a voltage regulator 3. The voltage reg- amplification circuit A through the C1, it is pre- ulator 3 adjusts a power-supply voltage VDD supplied vented that the amplification circuit A will be in an oscil- from an external device, and supplies a constant voltage 30 lation state. Moreover, since a very small current change VREG to the internal logic part 2. The band gap 4 gen- caused by a load connected to the output node N1 is erates a reference voltage VR used as the reference of absorbed by the capacitor C2, the voltage VREG of the the voltage VREG and a constant current control signal output node N1 is maintained almost uniformly. CS. [0011] The voltage regulator shown in Fig. 3 (b) is re- [0005] The conventional voltage regulator used for 35 placed with the transistor M1 of the voltage regulator the integrated circuit card is shown in Fig. 3 (a) and Fig. shown in Fig. 3 (a), and has a constant current circuit B 3 (b). A series type voltage regulator is shown in Fig. 3 which supplies constant current to the output node N1 (a), and a shunt type voltage regulator is shown in Fig. from the power-supply voltage VDD. Furthermore, this 3 (b). voltage regulator has an N type MOS transistor M2 con- [0006] The voltage regulator shown in Fig. 3 (a) has 40 nected between the output node N1 and the ground po- a differential amplification circuit A which has an invert- tential GND and controlled by the output voltage VO of ed input terminalᮀᮀᮀto which the reference voltage VR the amplification circuit A. is applied. An output of the differential amplification cir- [0012] In this voltage regulator, the constant current cuit A is connected to a gate of a P type MOS transistor is always supplied to the output node N1 by the constant M1. A power-supply voltage VDD is applied to a source 45 current circuit B from the power-supply voltage VDD. of the transistor M1 and a drain of the transistor M1 is Reduction of current which flows for the load connected connected to an output node N1. A circuit to the output node N1 rises voltage VREG of the output which comprised of a resistor R1 and a resistor R2 is node N1. By this, the output voltage VO of the amplifi- connected between the output node N1 and a ground cation circuit A rises, the internal resistance of the tran- potential GND. Comparison voltage VC generated from 50 sistor M2 decreases, and current which flows to this the voltage divider circuit is given to an non-inverted in- transistor M2 increases. Conversely, an increase of cur- put terminal ᮀ of the amplification circuit A. rent which flows for load reduces voltage VREG of the [0007] The constant current control signal CS for gen- output node N1. By this, the output voltage VO of the erating constant current is given to the amplification cir- amplification circuit A falls, the internal resistance of the cuit A. The signal of the output node N1 is given to the 55 transistor M2 increases, and current which flows to this amplification circuit A through a capacitor C1 for phase transistor M2 decreases. It is controlled by such feed- compensation. A capacitor C2 for voltage flat and back operation so that the sum of current which flows smooth is connected between the output node N1 and for the load connected to the output node N1, and cur-

2 3 EP 1 282 072 A1 4 rent which flows to the transistor M2 becomes always first and the second transistors so that an output voltage constant, and the voltage VREG of the output node N1 of the output node is maintained at constant voltage. is stabilized. [0021] The above and further objects and novel fea- [0013] However, the following subjects occurred in tures of the invention will more fully appear from the fol- the conventional voltage regulator. 5 lowing detailed description, appended claims, and ac- [0014] For example, in the series type voltage regu- companying drawings. lator, when the power-supply voltage VDD is 5V, the voltage VREG at the output node N1 is 3V and the load BRIEF DESCRIPTION OF THE DRAWINGS current range between 0 and 10mA, 0-10mA current is supplied from the power-supply voltage VDD corre- 10 [0022] sponding to the load current. [0015] Therefore, the product of the voltage drop (2V) Fig. 1 is a circuit diagram showing a voltage regu- with the transistor M1 and the load current is lost, and it lator according to a first preferred embodiment of is satisfactory from the viewpoint of power consumption. the present invention. [0016] However, since current supplied from the pow- 15 Fig. 2 is a schematic block diagram showing an IC er-supply voltage VDD corresponded to load current, card of the related art. there is a problem enable it to analyze operation of the Fig. 3 (a) and Fig. 3 (b) are circuit diagrams showing internal logic part of the integrated circuit card, by acting voltage regulators of the related art. as the monitor of the change of current supplied from Fig. 4 is a circuit diagram showing a voltage regu- the exterior. 20 lator according to a first preferred embodiment of [0017] When analysis technique, such as DPA/SPA the present invention. (Differential Power Analysis/Simple Power Analysis), is Fig. 5 is a circuit diagram showing a voltage regu- used especially, there is a possibility that the problem lator according to a second preferred embodiment that secret data which should be protected on security of the present invention. will be decoded from a power-supply current waveform 25 Fig. 6 is a circuit diagram showing a voltage regu- may occur. lator according to a third preferred embodiment of [0018] On the other hand, at the shunt type voltage the present invention. regulator shown in Fig. 3 (b), since constant current al- Fig. 7 is a circuit diagram showing an cir- ways flows from the power-supply voltage VDD by the cuit 10A in Fig. 6. constant current circuit B, there is no possibility that an 30 Fig. 8 is a circuit diagram showing a voltage regu- internal state may be decoded by the monitor of a pow- lator according to a fourth preferred embodiment of er-supply current waveform. However, for this reason, the present invention. regardless of actual load current, current which always Fig. 9 is a circuit diagram showing an amplifier cir- exceeds 10mA needed to be supplied and there is a cuit 10B in Fig. 8. problem in the viewpoint of power consumption. 35 [0019] Therefore, there are few increases in power DETAILED DESCRIPTION OF THE PREFERRED consumption and the voltage regulator and IC with dif- EMBODIMENT ficult analysis of operation of an internal logic circuit have been desired. [0023] A voltage regulator and a semiconductor inte- 40 grated circuit according to the present invention will be SUMMARY OF THE INVENTION explained hereinafter with reference to figures.

[0020] According to one aspect of the present inven- First preferred embodiment tion, there is provided a voltage regulator includes a con- stant current circuit which is connected between an in- 45 [0024] Fig. 1 is a circuit diagram showing a voltage put node with which a power supply voltage is supplied regulator according to a first preferred embodiment of and an output node to which a load is connected and the present invention. which supplies constant current to the output node. The [0025] This voltage regulator has differential type am- voltage regulator also includes a first transistor which is plification circuit 101 and amplification circuit 102 where provided in parallel to the constant current circuit and 50 a reference voltage VR is applied to an inverted input which flows insufficient current to the output node when terminalᮀ, and a comparison voltage VC is given to an current flowing through the load is larger than the con- non-inverted input terminal +. The amplification circuit stant current and a second transistor which is provided 101 and the amplification circuit 102 are the same struc- between the output node and a common potential node tures mutually. The output of the amplification circuit 101 and which flows surplus current to the common potential 55 is connected to a gate of a P channel MOS transistor 31 node when current flowing through the load is less than (hereinafter referred to as PMOS) and the output of the the constant current. The voltage regulator also includes amplification circuit 102 is connected to a gate of an N a control circuit which controls a conductive state of the channel MOS transistor 32 (hereinafter referred to as

3 5 EP 1 282 072 A1 6

NMOS). A source of the PMOS 31 is supplied with the [0032] A gate of an NMOS 19 is connected to the node power-supply voltage VDD and a drain of the PMOS 31 N11, and a source of this NMOS 19 is connected to the is connected to the output node NO. A drain of the ground potential GND through an NMOS 20. Moreover, NMOS 32 is connected to the output node NO and a a gate of the NMOS 20 and a gate of an NMOS 14 are source of the NMOS 32 is connected to a ground poten- 5 connected to a drain of the NMOS14. The Phase com- tial GND. pensation signal PS gives the gate of the NMOS 20. A [0026] The constant current control signal CS for gen- drain of the NMOS19 is connected to a drain and a gate erating constant current is applied to the amplification of a PMOS 21, and a source of the PMOS 21 is con- circuit 101 and the amplification circuit 102. Further- nected to the power-supply voltage VDD. more, the amplification circuit 101 and the amplification 10 [0033] Furthermore, a gate of a NMOS 22 is connect- circuit 102 receive phase compensation signal PS ed to the node N11, and a source of the NMOS 22 is through the capacitor 33 and the capacitor 34 for phase connected to the ground potential GND through an compensation so that operation stabilized, without be- NMOS 23. Moreover, a gate of the NMOS 23 and a gate ing in an oscillation state may be performed. of a NMOS15 are connected to a drain of the NMOS 15. [0027] The constant current circuit 40 is connected 15 A drain of the NMOS 22 is connected to a drain of a between the power-supply voltage VDD and the output PMOS 24. A source and a gate of the PMOS 24 are node NO. The constant current circuit 40 is set up so as connected to the power-supply voltage VDD and the to flow constant current having about a half of an aver- PMOS 21, respectively. age load current. Moreover, between the output node [0034] In such an amplification circuit, the voltage dif- NO and the ground potential GND, the capacitor 35 for 20 ference between the reference voltage VR and the com- voltage flat and smooth is connected. parison voltage VC which are inputted into the PMOS [0028] Furthermore, between the output node NO and 11 and the PMOS 12 comprised of a differential input the ground potential GND, a voltage dividing circuit part is amplified. The output voltage VO is output from which comprised of resistor 36 and resistor 37 is con- the connecting point of drains of the NMOS 22 and the nected, and the comparison voltage VC generated by 25 PMOS 24. the voltage dividing circuit is applied to the non-inverted [0035] On the other hand, as shown in Fig. 3 (b), a input terminal + of the amplification circuit 101, and the constant current circuit has a PMOS 41 so as to flow non-inverted input terminal + of the amplification circuit constant current based on the constant current control 102. Voltage VREG adjusted to desired constant volt- signal CS. A source of the PMOS 41 is connected to the age is output from the output node NO to the load circuit 30 power-supply voltage VDD, and a drain of the PMOS 41 not illustrated. is connected to a gate and a drain of an NMOS 42. [0029] Fig. 4 (a) and Fig. 4 (b) is a circuit diagram Source of the NMOS 42 is connected to the ground po- showing an example of the amplification circuit in Fig. tential GND. 1, and a constant current circuit. [0036] A gate of an NMOS 43 which constitutes a cur- [0030] This amplification circuit has a PMOS 11 and 35 rent mirror circuit to the NMOS 42 is connected to a drain a PMOS12 which constitute a differential input part. The of the NMOS 42. Source of the NMOS 43 is connected reference voltage VR is applied to a gate of the PMOS to the ground potential GND, and a drain of the NMOS 11and the comparison voltage VC is applied to a gate 43 is connected to a drain and a gate of the PMOS44. of PMOS 12. Sources of the PMOS 11 and the PMOS Source of the PMOS 44 is connected to the power-sup- 12 are commonly connected to the power-supply volt- 40 ply voltage VDD. age VDD through a PMOS 13. The constant current con- [0037] A gate of a PMOS 45 which constitutes a cur- trol signal CS is applied to a gate of the PMOS 11, and rent mirror circuit to the PMOS 44 is connected to the constant current supplies the PMOS 11 and the PMOS drain of the PMOS 44.. A Source of the PMOS 45 is 12 through this PMOS 13. Drains of the PMOS 11 and connected to the power-supply voltage VDD, and a the PMOS 12 are connected to the ground potential 45 drain of the PMOS 45 is connected to an output node GND through NMOS 14 and NMOS 15 by which NO of a voltage regulator. connection is made in the direction of order, respective- [0038] In such a constant current circuit, desired con- ly. stant current is supplied to the output node NO by setting [0031] Furthermore, this amplification circuit has a dimension of the gate width and gate length of each tran- PMOS 16 constituted so that constant current might be 50 sistor so that it may become a predetermined ratio. For passed based on the constant current control signal CS, example, if current of 50µA flows to the PMOS 41 and source of this PMOS 16 is connected to the power-sup- the NMOS 42 based on the constant current control sig- ply voltage VDD, and drain of this PMOS 16 is connect- nal CS, in proportion to current which flows to this NMOS ed to the node N11. A drain and a gate of an NMOS 17 42, current of 500µA flows to the NMOS 43. Thereby, are connected to the node N11, and a source of this 55 current of 500µA flows also to the PMOS 44, in propor- NMOS 17 is connected to a gate and a source of an tion to current which flows to the PMOS 44, current of NMOS 18. The source of the NMOS 18 is connected to 5mA flows to the NMOS 45. And 5mA constant current the ground potential GND. is supplied to the output node NO.

4 7 EP 1 282 072 A1 8

[0039] Next, operation of the circuit shown in Fig. 1 is [0049] Moreover, since only the insufficiency is sup- explained. plied from the PMOS 31 when load current exceeds the [0040] First, the load circuit not illustrated is connect- capability of the constant current circuit 40, there is little ed to the output node NO. This load circuit has a condi- change of current supplied from the power-supply volt- tion that predetermined voltage VREG of 3V is appeared 5 age VDD, and the analysis of the internal state of a load at the output node NO and load current changes in the circuit becomes very difficult. range of 0-10mA when the load circuit is connected to [0050] Therefore, by setting current of the constant the output node NO. current circuit 40 as suitable value, the voltage regulator [0041] From the exterior, the power-supply voltage to which power consumption is not made to almost in- VDD of 5V is supplied, for example, and when stable 10 crease and with the difficult analysis of a load circuit of reference voltage VR and the constant current control operation can be obtained. signal CS are applied, 5mA constant current is supplied to the output node NO through the constant current cir- Second preferred embodiment cuit 40. [0042] Simultaneously, the gate of the PMOS 31 serv- 15 [0051] Fig.5 is a circuit diagram showing a voltage ing as constant connected in parallel with regulator according to a second preferred embodiment the constant current circuit 40 is controlled by the output of the present invention. In Fig. 5, wherein like elements voltage VO1 of the amplification circuit 101. Moreover, are given like reference characters in Fig. 1. the gate of the NMOS 32 connected in parallel with the [0052] The difference between the second embodi- load circuit is controlled by the output voltage V02 of the 20 ment and the first embodiment resides in that a resistor amplification circuit 102. 38 is connected between the resistor 36 and the resistor [0043] Voltage of the output node NO is divided by the 37. The sum of resistance value of this resistor 36 and resistor 36 and the resistor 37 and it is given to the input resistance value of the resistor 38 is set as the resist- side of the amplification circuit 101 and the amplification ance value of the resistor 36 in Fig. 1. The comparison circuit 102 as the comparison voltage VC. The reference 25 voltage VC1 appeared at a connection point where the voltage VR set up so that this output node NO might resistor 36 and the resistor 38 are connected to each serve as predetermined voltage VREG is given to the other may be applied to the non-inverted input terminal input side of the amplification circuit 101 and the ampli- + of the amplification circuit 101. The comparison volt- fication circuit 102 age VC2 appeared at a connection point where the re- [0044] Thereby, where the output node NO is set to 30 sistor 37 and the resistor 38 are connected to each other voltage VREG, the output voltage VO1 of the amplifica- may be applied to the non-inverted input terminal + of tion circuit 101 and the output voltage VO2 of the am- the amplification circuit 102. plification circuit 102 are stabilized, and stable constant [0053] The resistance value of the resistor 38 is set voltage VREG is outputted. as the resistance value which can give the potential dif- [0045] For example, when load current is 10mA, 5mA 35 ference more than the variation voltage of offset of the is supplied through the constant current circuit 40, and amplification circuit 101 and the amplification circuit 102 5mA of an insufficiency is supplied to the output node to the non-inverted input terminal + of the amplification NO through the PMOS 31. And the NMOS 32 enters into circuit 101 and the amplification circuit 102. In addition, an OFF state. the resistance ratio of the resistor 36, the resistor 38, [0046] Moreover, when load current is 1mA, the 40 and the resistor 37 is set up so that the comparison volt- PMOS 31 enters into an OFF state, 1mA is supplied to age VC2 equal to the level of the reference voltage VR the load circuit in 5mA supplied to the output node NO to the voltage VREG of the output node NO. That is, from the constant current circuit 40, and 4mA for a sur- when the resistance value of the resistor 36, the resistor plus (remaining) flows to the ground potential GND 38, and the resistor 37 is R36, and R38 and R37, re- through the NMOS 32. 45 spectively, the reference voltage VR is expressed with [0047] As mentioned above, the voltage regulator of the following formula. the first preferred embodiment has the PMOS 31 pro- vided in parallel with the constant current circuit 40 and VR=VREGϫR37 /(R36+R38) +R37 the NMOS 32 provided in parallel with the load circuit. These PMOS 31 and NMOS 32 may be controlled so 50 that the output node NO may serve as voltage VREG. [0054] Moreover, the drive capability of the amplifica- [0048] Since current supplied from the power-supply tion circuit 102 is set up more greatly than the amplifi- voltage VDD becomes constant value unless load cur- cation circuit 102. Other structures are the same as that rent which flows in a load circuit exceeds the capability of Fig. 1. of the constant current circuit 40, the analysis of the in- 55 [0055] Next, operation is explained. ternal state of the load circuit (internal logic circuit) by [0056] When the power-supply voltage VDD is sup- the monitor of a power-supply current waveform be- plied and the reference voltage VR, the constant current comes impossible. control signal CS, and the constant current circuit 40 are

5 9 EP 1 282 072 A1 10 stabilized, the output voltage VO1 of the amplification [0062] This voltage regulator is replaced with the am- circuit 101 tends to control the gate of the PMOS 31 plification circuit 102 in Fig. 5, and has amplification cir- serving as current source so that the comparison volt- cuit 10A whose operation is controlled by the control sig- age VC1 is set to the same level as the reference voltage nal S1. Moreover, while a PMOS 51 for a by which VR. Moreover, the output voltage VO2 of the amplifica- 5 ON/OFF control is carried out with a control signal S1 is tion circuit 102 controls the gate of the NMOS 32 so that provided between the power-supply voltage VDD and the comparison voltage VC2 is set to the same level as the constant current circuit 40 in series, an NMOS 52 the reference voltage VR. for a switch by which ON/OFF control is carried out with [0057] At this time, since drive capability of the ampli- this control signal S1 is provided between the output fication circuit 101 is larger than that of the amplification 10 side of amplification circuit 10A, and the ground poten- circuit 102, the comparison voltage VC2 is set to the ref- tial GND. Other structures are the same as that of Fig. 5. erence voltage VR. And the comparison voltage VC1 is [0063] Fig.7 is one example of circuit diagram show- set to a level high a little to the reference voltage VR by ing an amplifier circuit 10A in Fig.6. In Fig. 7, wherein having formed resistor 38. Therefore, the voltage VREG like elements are given like reference characters in Fig. becomes constant voltage by the amplification circuit 15 4 (a). 102 and NMOS 32 and comes to be supplied to an inside [0064] In this amplification circuit 10A, an NMOS2 5, as internal voltage. a PMOS2 6, a PMOS 27, and the inverter 28 are added [0058] Since the comparison voltage VC1 is higher to the amplification circuit of Fig. 4 (a). than the reference voltage VR, the output voltage VO1 [0065] The NMOS 25 is connected between the node of the amplification circuit 101 is H level, and the PNOS 20 N11 and the ground potential GND, and a gate of the 31 serving as current source is in an OFF state. That is, NMOS 25 is controlled by the control signal S1. The in usual, current supply to inside is performed only by PMOS 26 is inserted between sources of the PMOS 11 the constant current circuit 40. and the PMOS 12, and a drain of the PMOS 13, and a [0059] When current consumption of an internal cir- gate of the PMOS 26 is controlled by the control signal cuit exceeds the supply capability of the constant cur- 25 S1. Moreover, a PMOS 27 is connected between the rent circuit 40, the voltage VREG falls gradually and the gate of a PMOS 24 and a source of the PMOS 24, and comparison voltage VC1 approaches the reference volt- a gate of the PMOS 24 is controlled by an inverted con- age VR. When the comparison voltage VC1 is more trol signal S1 inverted by the inverter 28. nearly less than the reference voltage VR, the output [0066] Next, operation is explained. voltage VO1 of the amplification circuit 101 falls, the 30 [0067] When the control signal S 1 is L level, the PMOS 31 serving as current source is changed into an PMOS 51 is in an ON state and the NMOS 52 is in an ON state and the comparison voltage VC1 tends to OFF state. In the amplification circuit 10A, the NMOS raise. Namely, when current consumption of an internal 25 and the PMOS 27 are in OFF states, and the PMOS circuit exceeds the supply capability of the constant cur- 26 is in an ON state. Therefore, operation of the voltage rent circuit 40, the voltage VREG of the output node NO 35 regulator of the Fig. 6 in case the control signal S1 is L is controlled by the amplification circuit 101 and the am- level is the same as that of the voltage regulator of Fig. 5. plification circuit 102, and the PMOS 31 and the NMOS [0068] On the other hand, when the control signal S1 32. is H level, the PMOS 51 is in an OFF state and the [0060] As mentioned above, in the voltage regulator NMOS 52 is in an ON state. Thereby, while the constant of the second embodiment, the comparison voltage VC1 40 current circuit 40 is disconnected from the power-supply applied to the amplification circuit 101 is set so that it voltage VDD, the output side of amplification circuit 10A may become higher than the comparison voltage VC2 is fixed to L level, and the NMOS 32 in an OFF state. In applied to the amplification circuit 102. Thereby, priority amplification circuit 10A, the NMOS 25 and the PMOS is given to control of the NMOS 32 over the PMOS 31, 27 are in ON states, and the PMOS 26 is in an OFF and current supply to an internal circuit is supplied from 45 state. Therefore, almost all the current passes of ampli- the constant current circuit 40. Therefore, since current fication circuit 10A are cut off. is supplied from the PMOS 31 only when the supply ca- [0069] Therefore, when the control signal S1 is H lev- pability of the constant current circuit 40 is exceeded, el, this voltage regulator serves as the same structure there is an advantage that the monitor of internal current as the voltage regulator of the conventional series type consumption becomes difficult and the effect of the 50 of Fig. 3 (a). measure against security becomes large further. [0070] As mentioned above, in the third preferred em- bodiment, the voltage regulator has the PMOS 51 for Third preferred embodiment disconnecting the constant current circuit 40 from the power-supply voltage VDD according to the control sig- [0061] Fig.6 is a circuit diagram showing a voltage 55 nal S1 and the NMOS 52 which is connected in parallel regulator according to a third preferred embodiment of with the output node NO and for changing the NMOS 32 the present invention. In Fig. 6, wherein like elements into an OFF state. Furthermore, the voltage regulator are given like reference characters in Fig. 5. has the amplification circuit 10A by which almost all op-

6 11 EP 1 282 072 A1 12 eration is stopped with this control signal S1. For this control signal SB is H level, the PMOS 51 is in an OFF reason, in addition to the same advantage as the second state and the NMOS 52 is in an ON state. Thereby, while embodiment, in the case of the state of operation where the constant current circuit 40 is electrically separated security does not pose a problem, there is an advantage from the power-supply voltage VDD and the output side that power consumption is reducible for being carried 5 of the amplification circuit 10A is fixed to L level, and out by enabling it to constitute a series type voltage reg- thus the NMOS 32 is in an OFF state. Moreover, in the ulator, by setting the control signal S1 as H level. amplification circuit 10A, the NMOS 25 and the PMOS 27 are in ON states, the PMOS 26 is in an OFF state Fourth preferred embodiment and thus almost all the current passes in this amplifica- 10 tion circuit 10A are cut off. Furthermore, in the amplifi- [0071] Fig. 8 is a circuit diagram showing a voltage cation circuit 10B, the PMOS 29b is in an ON state and regulator according to a fourth preferred embodiment of the PMOS 13a and the PMOS 29a are connected in par- the present invention. In Fig. 8, wherein like elements allel. Therefore, where the standby signal is L level and are given like reference characters in Fig. 6. the control signal SB is H level, this voltage regulator [0072] This voltage regulator is replaced with the am- 15 serves as the structure as the voltage regulator of the plification circuit 102 in Fig. 6, and has amplification cir- conventional series type of Fig. 3 (a). cuit 10B whose operation is controlled by standby signal [0080] When the standby signal SA is H level, regard- SA. Moreover, the logic OR gate 53 (hereafter referred less of the level of the control signal SB, the PMOS 51 to as OR) for taking the logic sum of standby signal SA is in an OFF state and the NMOS 52 will is in an ON and the control signal SB is provided. The amplification 20 state. Thereby, the constant current circuit 40 is electri- circuit 10A, and the PMOS 51 and the NMOS 52 are cally separated form the power-supply voltage VDD and controlled by this output signal of OR 53. Other struc- the output side of the amplification circuit 10A is fixed to tures are the same as that of Fig. 6. L level, and thus the NMOS 32 is in an OFF state. More- [0073] Fig.9 is a circuit diagram showing an amplifier over, in the amplification circuit 10A, the NMOS 25 and circuit 10B in Fig.8. In Fig. 9, wherein like elements are 25 the PMOS 27 is in an ON state, the PMOS 26 is in an given like reference characters in Fig. 4 (a). OFF state and almost all the current passes in this am- [0074] In this amplification circuit 10B, a PMOS 29a plification circuit 10A is cut off. On the other hand, in the and a PMOS 29b connected n-series are added to the amplification circuit 10B, the PMOS 29b is in an OFF amplification circuit of Fig. 4 (a). Furthermore, a PMOS state and the PMOS 13b is detached. Thereby, while 13a with little current capacity is replaced with the 30 the drive capability to the PMOS 31 of the amplification PMOS 13. circuit 10B declines, the power consumption of this am- [0075] The gate width of the PMOS 13a is set as the plification circuit 10b declines. Therefore, when the con- minimum size which can drive the PMOS 31 by amplifi- trol signal SA is L level, this voltage regulator serves as cation circuit 10B. And the gate width of the PMOS 13a the series type structure in the low power-consumption is set so that the sum total of the gate width of this PMOS 35 mode. 13a and the gate width of the PMOS 29a may become [0081] As mentioned above, in the fourth embodi- equal to the gate width of the PMOS13. ment, the voltage regulator has the amplification circuit [0076] A source of the PMOS 29a is connected to the 10B which enters in to the low power-consumption power-supply voltage VDD, and a drain of the PMOS mode according to the standby signal SA. Therefore, the 29a is connected to a source of the PMOS 29b. Further- 40 voltage regulator can be operated in the low power-con- more, a drain of the PMOS 29b is connected to a drain sumption mode at the time of standby, by using standby of the PMOS 13a. The constant current control signal signal SA and the control signal SB. CS and the standby signal SA are applied to a gate of [0082] In addition, this invention is not limited to the the PMOS 29a and a gate of the PMOS 29b, respec- above-mentioned case of the operation, but various tively. Other structures are the same as that of Fig. 4 (a). 45 modifications is possible for it. As a modification, there [0077] Next, operation is explained. are followings, for example. [0078] When the both of the standby signal SA and the control signal SB are L level, the PMOS51 is in an (a) A bipolar transistor may be replaced with the ON state and the NMOS 52 is in an OFF state. In the PMOS 31 and the NMOS 32 amplification circuit 10A, the NMOS2 5 and the PMOS 50 (b) The structure of the amplification circuit 10 or 27 are in OFF states, and the PMOS 26 is in an ON the constant current circuit 40 is not limited to what state. Furthermore, in the amplification circuit 10B, the is illustrated, but if the same operation is possible, NMOS 29b is in an ON state and the PMOS 13a and it can apply the thing of any circuit structures. the PMOS 29a are connected in parallel. Therefore, op- (c) The connection point, where the capacitor 33 for eration of the voltage regulator of the Fig. 8 in case the 55 phase compensation and the capacitor 34 for phase standby signal SA and the control signal SB are L levels compensation are connected to each other, is not is the same as that of the voltage regulator of Fig. 5. limited to the point illustrated in figures. The con- [0079] When the standby signal SA is L level and the nection point may be set at a point so that an am-

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plification circuit will not be in an oscillation state by ceived, the first amplification circuit may be made into phase compensation. the low consumption current mode. Thereby, in the ap- (d) The PMOS, whose ON/OFF state is controlled plication which does not need security, while power con- by the controls signal S1 and which is connected sumption can be reduced, at the time of standby, reduc- between output node NO and the NMOS 32, may 5 tion of power consumption is further attained by the low be replaced with the NMOS 52 in Fig. 6 and Fig. 8. consumption current mode. (e) The OR 53 in Fig. 8 is omitted and the amplifi- [0088] According to the sixth to eighth embodiments cation circuit 10A and the amplification circuit 10B of the invention, the voltage regulator has the first ad- may be made to control by the standby signal SA. justment means which controls current which flows from In this case, a security mode for operation which 10 an input node to the first node based on the voltage dif- needs security and a low power-consumption oper- ference of the first divided voltage and reference voltage ation mode can be selected by the standby signal and the second adjustment means which controls cur- SA. rent which flows from the first node to the second node based on the voltage difference of the second divided [0083] As explained above in detail, according to the 15 voltage and reference voltage. Thereby, when load cur- first embodiment of the invention, the voltage regulator rent exceeds the supply capability of the constant cur- has the constant current circuit which supplies constant rent source, current of an insufficiency is supplied from current, the first transistor provided in parallel to this the first adjustment means. Therefore, the analysis of constant current circuit, and the second transistor pro- the load circuit by the monitor of load current of opera- vided between an output node and a common potential. 20 tion becomes difficult. Thereby, when load current exceeds the constant cur- [0089] While the preferred form of the present inven- rent, current of an insufficiency is supplied from the first tion has been described, it is to be understood that mod- transistor. Therefore, the increase in power consump- ifications will be apparent to those skilled in the art with- tion is suppressed and the analysis of the load circuit by out departing from the spirit of the invention. The scope the monitor of load current of operation becomes diffi- 25 of the invention, namely, is to be determined solely by cult. the following claims. [0084] According to the second embodiment of the in- vention, the voltage regulator has the first amplification circuit which compares the first divided voltage and a Claims reference voltage and which controls the first transistor, 30 and the second amplification circuit which compares the 1. A voltage regulator comprising: second divided voltage lower than the first divided volt- age and reference voltage and which controls the sec- a constant current circuit which is connected ond transistor. Thereby, since the first transistor is con- between an input node with which a power sup- trolled previously, penetration current which flows from 35 ply voltage is supplied and an output node to power-supply voltage to the common potential through which a load is connected and which supplies the first and the second transistor can be prevented. constant current to the output node; [0085] According to the third embodiment of the in- a first transistor which is provided in parallel to vention, the voltage regulator has a switch means to the constant current circuit and which flows in- stop current which flows to a constant current circuit and 40 sufficient current to the output node when cur- the second transistor according to the control signal. rent flowing through the load is larger than the Thereby, useless consumption current can be lost in the constant current; application which does not need security. a second transistor which is provided between [0086] According to the fourth embodiment of the in- the output node and a common potential node vention, the voltage regulator has a switch means to 45 and which flows surplus current to the common stop current which flows to a constant current circuit and potential node when current flowing through the the second transistor according to a control signal. Fur- load is less than the constant current; and thermore, it has a structure to stop amplification opera- a control circuit which controls a conductive tion of the second amplification circuit with this control state of the first and the second transistors so signal. Thereby, in the application which does not need 50 that an output voltage of the output node is security, consumption current can be reduced further. maintained at constant voltage. [0087] According to the fifth embodiment of the inven- tion, the voltage regulator has a switch means to stop 2. A voltage regulator according to Claim 1, wherein current which flows to a constant current circuit and the the control circuit comprises; second transistor when a standby signal or a control sig- 55 nal is applied. Furthermore, it has a structure so that a voltage dividing circuit which divides the out- operation of the second amplification circuit may be put voltage and which generates a first divided stopped. Furthermore, when a standby signal is re- voltage and a second divided voltage lower

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than the first divided voltage; a second amplification circuit which amplifies a a first amplification circuit which amplifies a voltage difference between a reference voltage voltage difference between the first divided and a second divided voltage and which out- voltage and a reference voltage and which con- puts the second control signal. trols the first transistor; and 5 a second amplification circuit which amplifies a 8. A voltage regulator according to Claim 7, wherein voltage difference between the second divided the first adjustment circuit comprises a P type MOS voltage and the reference voltage and which transistor and wherein the second adjustment cir- controls the second transistor. cuit comprises an N type MOS transistor. 10 3. A voltage regulator according to Claim 1 or 2, further 9. A voltage regulator comprising: comprising a switch which stops current flowing through the constant current circuit and the second a constant current circuit which is connected transistor when a control signal receives. between an input node with which a power sup- 15 ply voltage is supplied and an output node to 4. A voltage regulator according to Claim 3, wherein which a load is connected and which supplies the second amplification circuit stops operation constant current to the output node; thereof when the control signal receives. a first transistor which is provided in parallel to the constant current circuit and which flows cur- 5. A voltage regulator according to Claim 2, further 20 rent of insufficiency to the output node when comprising; current flowing through the load exceeds the constant current; a switch which stops current flowing through a second transistor which is provided between the constant current circuit and the second tran- the output node and a common potential node sistor when a standby signal and a control sig- 25 and which flows current of surplus to the com- nal receive, and mon potential node when current flowing wherein the first amplification circuit en- through the load is not reached to the constant ters into a low power consumption mode when current; and the standby signal receives, and a control circuit which controls a conductive wherein the second amplification circuit 30 state of the first and the second transistors so stops operation thereof when either the stand- that an output voltage of the output node is by signal or the control signal receives. maintained at constant voltage.

6. A semiconductor integrated circuit comprising: 10. A voltage regulator according to Claim 9, wherein 35 the control circuit comprises; an input node which is supplied with a first volt- age; a voltage dividing circuit which divides the out- an output node which is coupled to a first node; put voltage and which generates a first divided a second node which is supplied with a second voltage and a second divided voltage lower voltage lower than the first voltage; 40 than the first divided voltage; a constant current source which is coupled be- a first amplification circuit which amplifies a tween the input node and the first node; voltage difference between the first divided a first adjustment circuit which controls the voltage and a reference voltage and which con- amount of current flowing between the input trols the first transistor; and node and the first node according to a voltage 45 a second amplification circuit which amplifies a level of a first control signal; and voltage difference between the second divided a second adjustment circuit which controls the voltage and the reference voltage and which amount of current flowing between the first controls the second transistor. node and the second node according to a volt- age level of a second control signal. 50 11. A voltage regulator according to Claim 9 or 10, fur- ther comprising a switch which stops current flowing 7. A voltage regulator according to Claim 6, further through the constant current circuit and the second comprising; transistor when a control signal receives.

a first amplification circuit which amplifies a 55 12. A voltage regulator according to one of Claims 9 to voltage difference between a reference voltage 11, wherein the second amplification circuit stops and a first divided voltage and which outputs operation thereof when the control signal receives. the first control signal; and

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13. A voltage regulator according to Claim 10, further comprising;

a switch which stops current flowing through the constant current circuit and the second tran- 5 sistor when a standby signal and a control sig- nal receive, and wherein the first amplification circuit en- ters into a low power consumption mode when the standby signal receives, and 10 wherein the second amplification circuit stops operation thereof when either the standby signal or the control signal receives. 15

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