DOCSLIB.ORG

Western Virginia Regional Design and Construction

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Western Virginia Regional Design and Construction WESTERN VIRGINIA REGIONAL DESIGN AND CONSTRUCTION 2014 STANDARDS ENGINEERING SERVICES 601 S JEFFERSON STREET ROANOKE, VA 24011 (540) 283-2948 WATER & SEWER DEPT 1300 TIDEWATER STREET SALEM, VA 24153 (540) 375-3029 PUBLIC WORKS 804 THIRD STREET VINTON, VA 24179 (540) 983-0646 WESTERN VIRGINIA REGIONAL STANDARDS AND SPECIFICATIONS FOR WATER AND SEWER Table of Contents Request for Waiver, Modification, or Field Change Form Utility Acceptance Certificate Design Standards Water DSW-1 Water Systems…………………………………………………………....... pp 1-10 Design Standards Sanitary Sewer DSS-1 Sanitary Sewer Systems…………………………………………….…….. pp 11-20 DSS-2 Sanitary Sewer Lift Station………………………………………………… pp 21-38 DSS-3 FOG Policy…………………………………………………………………... pp 39-54 Construction Specifications CS-1 General Water and Sewer……………………………………………........ pp 55-62 CS-2 Water Distribution Piping…………………………………………………... pp 63-76 CS-3 Sanitary Sewer Collection Piping…………………………………………. pp 77-90 CS-4 Sanitary Sewer Closed Circuit Television Inspection ………………….. pp 91-100 CS-5 Clearing and Grubbing…………………………………………………….. pp 101-104 CS-6 Rock Excavation ………………………………………………………....... pp 105-108 CS-7 Stream and/or Highway Crossings ………………………………………. pp 109-112 CS-8 Horizontal Directional Drilling (HDD) Methodology………………………. pp 113-120 CS-9 Seeding and Mulching …………………………………………………….. pp 121-126 Water Detail Drawings Sewer Detail Drawings General Water and Sewer Detail Drawings 2014 REQUEST FOR WAIVER, MODIFICATION, OR FIELD CHANGE WESTERN VIRGINIA REGIONAL STANDARDS AND SPECIFICATIONS FOR WATER AND SEWER Item/Standard: Water and Sewer Section Number: Project: Station/Location: Project Inspector: Project Engineer: Person Making Request: Name & Title Company Name Telephone Number Justification/Reason for Request: Participating Utility Inspector Comments: Participating Utility Department Comments: APPROVED DISAPPROVED Participating Utility Representative 2014 Western Virginia Water Authority UTILITY ACCEPTANCE CERTIFICATE This is to certify that the following described improvements have been constructed in accordance with the Western Virginia Water Authority Design and Construction Standards. The contractor, developer and surety remain bound by the terms of any applicable agreement(s), and/or (performance, payment, maintenance) guarantee(s). SUBDIVISION/PROJECT: DEVELOPER: CONTRACTOR: DESIGN FIRM/ENGINEER: Project Type: Approximate Lots Served: Plan Number: Approval Date: DEQ (If Applicable): Construction Start Date: WATER: Pressure Test: Bacteriological Test: Tracer Wire Continuity Test: (Non-metallic pipe only) SEWER: Line Pressure Test: MH Test: Camera Inspection: Date of Receipt: As- Builts: Easements Recorded: DATE OF SUBSTANTIAL COMPLETION: If Punch List is attached, this list of items shall be completed or corrected prior to Final Acceptance. This list may not be all-inclusive, and the failure to include any items on such list does not alter the responsibility of the Contractor to complete all Work in accordance with applicable Agreement(s). Upon Substantial Completion, the Authority may begin use of the accepted water/sewer improvements, however maintenance will remain the responsibility of the Developer/Contractor until Final Acceptance is issued by the Authority. Punch List Items Complete: Maintenance Guarantee Received: DATE OF FINAL ACCEPTANCE: Water Main (length): (8”) (other) Value: $ Water Services (number): (1”) (other) Value: $ Water Hydrants (number): Value: $ Sewer Gravity Main (length): (8”) (Other) Value: $ Sewer Pressure Main (length): ( “) Value: $ Sewer Manholes (number): Value: $ Sewer Services (number): (4”) (6”) Value: $ Other Utility Improvements Accepted: Value: $ Inspector: WVWA Project Manager: C: Contractor, Developer, T Lane, N Carroll, Y Doolittle (WO), B Hutchison & N Clouse (ENG), T Lawfield Project File*, Design Engineer* Building Dept. of Locality*, VDOT*, Fire Marshal of Locality* (*if applicable) Rev:1/1/14 DSW-1 DESIGN STANDARDS FOR WATER SYSTEMS 1.1 GENERAL A. The following standards and specifications represent the minimum requirements for all public water systems within the service area of the Participating Utility, hereinafter “Participating Utility” or “owner”. Before construction is commenced, plans and specifications shall be reviewed and approved by the appropriate participating utility, and all construction shall be in accordance with the approved construction documents. B. Systems shall be designed to meet or exceed Virginia Department of Health Office of Drinking Water, Water Works Regulations, latest edition. C. Water mains shall be located within public rights-of-way or waterline easements, and shall be located no closer than five feet (5’) from the edge of the easement or right-of-way line unless otherwise approved by the Participating Utility. D. Water supply systems, as described above, shall be designed by a Professional Engineer, licensed by the Commonwealth of Virginia whose seal and signature shall be placed on each plan sheet. A Land Surveyor licensed by the Commonwealth of Virginia may design such portions of a water supply system as provided by the Code of Virginia, Title 54, Section 54-17.1, 3(b). E. The Western Virginia Regional Standards and Specifications for Water and Sewer (Standards) shall be followed unless specified deviation therefore is authorized, in writing, by the Participating Utility. Deviations require use of the Request for Waiver, Modification or Field Change Form. When such deviations affect fire protection, approval by the Fire Marshal of the local jurisdiction shall also be obtained. Unless otherwise stated, all standards referenced in this Section shall refer to the latest revision or revised edition of the referenced manual. F. For agreements between the Participating Utility and the Contractor, the term “Participating Utility” shall substitute for “Owner” in all cases. 2.1 MINIMUM WATER MAIN SIZES A. Generally, the minimum water main size is twelve inches (12”) when located along a primary or other major roadway. Eight inch (8”) mains may be used elsewhere, but only when interconnected in a grid system no more than one- thousand-five-hundred feet (1,500’) apart. Six inch (6”) mains may be used in dead end or cul-de-sacs beyond the last fire hydrant, if the block is less than six- hundred feet (600') in length. For streets with cul-de-sacs or dead ends beyond the last fire hydrant, in which all adjacent properties are evaluated and it is determined that the water line cannot and will not be extended in the future, two inch (2”) pipe may be used for the last three-hundred feet (300’) when approved by the Participating Utility. The type of services installed along the two inch (2”) pipe must be evaluated to guarantee adequate flow to meet all existing and future demands at these services. Two-inch lines are not allowed in the City of Salem or Town of Vinton Design Standard - Water Systems 1/1/14 Page 1 of 126 B. Fire hydrants shall not be installed on lines less than six inches (6”) in diameter. Unless specifically approved otherwise by the Fire Marshal, no plantings or erection of other obstructions shall be made within a four-foot (4') radius of any fire hydrant, or at any location that would restrict access to the fire hydrant from the street. The ground surface within this same radius shall be level. 2.2 FIRE HYDRANT LOCATIONS The following are general minimum design guidelines. Specific requirements shall be determined by the Jurisdictional Fire Marshal’s Office. A. In residential areas, hydrants shall be located at street intersections and at intermediate locations where necessary, as determined by the Fire Marshal's Office. In no case shall the distance between fire hydrants, measured along the centerline of accessible streets, be greater than one-thousand feet (1,000'). B. Within one-hundred feet (100') of any standpipe or sprinkler system fire- department connection, where those systems are required in buildings. C. As required by the following schedule as given by use group, the distance shall be measured to the most remote part of the structure the hydrant will serve. Industrial buildings 250 feet School buildings 300 feet Commercial, Churches & Office Buildings 350 feet Apartments, Multi-family & Townhouses 250 feet Single family detached dwellings 500 feet* * Measured along centerline of street to the center of front property line for single- family detached dwellings only. D. All hydrants shall be a minimum of fifty feet (50') away from buildings other than single-family detached dwellings. The location of all new and existing hydrants that are to serve the property shall be shown on the plans. 2.3 WATER SYSTEM DESIGN Water systems shall be designed to adequately supply normal and peak demands for all customers, maintaining a static pressure of not less than twenty-five (25) pounds per square inch at all points of delivery, and shall have adequate capacity to deliver not less than the fire flows listed below, for a minimum of two hours, with a residual pressure of not less than twenty (20) pounds per square inch at the service connection based on the greater of maximum hour or maximum day plus applicable fire flows. In those cases where the existing source of supply cannot deliver fire flows at adequate pressures, the design engineer shall submit a request for waiver. Fire flows shall be analyzed and presented separately, and pipes shall be sized to meet the calculated requirements of simultaneous peak domestic and fire flow. The Participating Utility can require higher design pressure
Load more

Recommended publications
  • UNICORE OPTIMIZATION William Jalby
    UNICORE OPTIMIZATION William Jalby LRC ITA@CA (CEA DAM/ University of Versailles St-Quentin-en-Yvelines) FRANCE 1 Outline The stage Key unicore performance limitations (excluding caches) Multimedia Extensions Compiler Optimizations 2 Abstraction Layers in Modern Systems Application Algorithm/Libraries CS Programming Language Original Compilers/Interpreters domain of Operating System/Virtual Machines Domain of the computer recent architect Instruction Set Architecture (ISA) computer architecture (‘50s-’80s) Microarchitecture (‘90s) Gates/Register-Transfer Level (RTL) Circuits EE Devices Physics Key issue Application Algorithm/Libraries Understand the We have to take into relationship/interaction account the between Architecture intermediate layers Microarchitecture and Applications/Algorithms Microarchitecture KEY TECHNOLOGY: Don’t forget also the lowest layers Performance Measurement and Analysis Performance Measurement and Analysis AN OVERLOOKED ISSUE HARDWARE VIEW: mechanism description and a few portions of codes where it works well (positive view) COMPILER VIEW: aggregate performance number (SPEC), little correlation with hardware Lack of guidelines for writing efficient programs Uniprocessor Performance From Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 4th edition, October, 2006 - VAX: 25%/year 1978 to 1986 - RISC + x86: 52%/year 1986 to 2002 RISC + x86: ??%/year 2002 to present Trends Unicore Performance REF: Mikko Lipasti-University of [source: Intel] Wisconsin Modern Unicore Stage KEY PERFORMANCE
    [Show full text]
  • Computer Architecture Techniques for Power-Efficiency
    MOCL005-FM MOCL005-FM.cls June 27, 2008 8:35 COMPUTER ARCHITECTURE TECHNIQUES FOR POWER-EFFICIENCY i MOCL005-FM MOCL005-FM.cls June 27, 2008 8:35 ii MOCL005-FM MOCL005-FM.cls June 27, 2008 8:35 iii Synthesis Lectures on Computer Architecture Editor Mark D. Hill, University of Wisconsin, Madison Synthesis Lectures on Computer Architecture publishes 50 to 150 page publications on topics pertaining to the science and art of designing, analyzing, selecting and interconnecting hardware components to create computers that meet functional, performance and cost goals. Computer Architecture Techniques for Power-Efficiency Stefanos Kaxiras and Margaret Martonosi 2008 Chip Mutiprocessor Architecture: Techniques to Improve Throughput and Latency Kunle Olukotun, Lance Hammond, James Laudon 2007 Transactional Memory James R. Larus, Ravi Rajwar 2007 Quantum Computing for Computer Architects Tzvetan S. Metodi, Frederic T. Chong 2006 MOCL005-FM MOCL005-FM.cls June 27, 2008 8:35 Copyright © 2008 by Morgan & Claypool All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means—electronic, mechanical, photocopy, recording, or any other except for brief quotations in printed reviews, without the prior permission of the publisher. Computer Architecture Techniques for Power-Efficiency Stefanos Kaxiras and Margaret Martonosi www.morganclaypool.com ISBN: 9781598292084 paper ISBN: 9781598292091 ebook DOI: 10.2200/S00119ED1V01Y200805CAC004 A Publication in the Morgan & Claypool Publishers
    [Show full text]
  • Installation Guide for UNICORE Server Components
    Installation Guide for UNICORE Server Components Installation Guide for UNICORE Server Components UNICORE Team July 2015, UNICORE version 7.3.0 Installation Guide for UNICORE Server Components Contents 1 Introduction1 1.1 Purpose and Target Audience of this Document.................1 1.2 Overview of the UNICORE Servers and some Terminology...........1 1.3 Overview of this Document............................2 2 Installation of Core Services for a Single Site3 2.1 Basic Scenarios..................................3 2.2 Preparation....................................5 2.3 Installation....................................6 2.4 Security Settings................................. 15 2.5 Installation of the Perl TSI and TSI-related Configuration of the UNICORE/X server....................................... 18 2.6 The Connections Between the UNICORE Components............. 20 3 Operation of a UNICORE Installation 22 3.1 Starting...................................... 22 3.2 Stopping...................................... 22 3.3 Monitoring.................................... 22 3.4 User Management................................. 22 3.5 Testing your Installation............................. 23 4 Integration of Another Target System 24 4.1 Configuration of the UNICORE/X Service.................... 24 4.2 Configuration of Target System Interface..................... 25 4.3 Addition of Users to the XUUDB........................ 26 4.4 Additions to the Gateway............................. 26 5 Multi-Site Installation Options 26 5.1 Multiple Registries...............................
    [Show full text]
  • Intel's High-Performance Computing Technologies
    Intel’s High-Performance Computing Technologies 11th ECMWF Workshop Use of HIgh Performance Computing in Meteorology Reading, UK 26-Oct-2004 Dr. Herbert Cornelius Advanced Computing Center Intel EMEA Advanced Computing on Intel® Architecture Intel HPC Technologies October 2004 HPC continues to change … *Other brands and names are the property of their respective owners •2• Advanced Computing on Intel® Architecture Intel HPC Technologies October 2004 Some HPC History 1960s 1970s 1980s 1990s 2000s HPC Systems 1970s 1980s 1990s 2000s Processor proprietary proprietary COTS COTS Memory proprietary proprietary COTS COTS Motherboard proprietary proprietary proprietary COTS Interconnect proprietary proprietary proprietary COTS OS, SW Tools proprietary proprietary proprietary mixed COTS: Commercial off the Shelf (industry standard) *Other brands and names are the property of their respective owners •3• Advanced Computing on Intel® Architecture Intel HPC Technologies October 2004 High-Performance Computing with IA Source: http://www.top500.org/lists/2004/06/2/ Source: http://www.top500.org/lists/2004/06/5/ 4096 (1024x4) Intel® Itanium® 2 processor based system 2500 (1250x2) Intel® Xeon™ processor based system 22.9 TFLOPS peak performance 15.3 TFLOPS peak performance PNNL RIKEN 9 1936 Intel® Itanium® 2 processor cluster 7 2048 Intel® Xeon™ processor cluster 11.6 / 8.6 TFLOPS Rpeak/Rmax 12.5 / 8.7 TFLOPS Rpeak/Rmax *Other brands and names are the property of their respective owners •4• Advanced Computing on Intel® Architecture Intel HPC Technologies
    [Show full text]
  • Implementing Production Grids William E
    Implementing Production Grids William E. Johnston a, The NASA IPG Engineering Team b, and The DOE Science Grid Team c Contents 1 Introduction: Lessons Learned for Building Large-Scale Grids ...................................... 3 5 2 The Grid Context .................................................................................................................. 3 The Anticipated Grid Usage Model Will Determine What Gets Deployed, and When. 7 3.1 Grid Computing Models ............................................................................................................ 7 3 1.1 Export Existing Services .......................................................................................................... 7 3 1.2 Loosely Coupled Processes ..................................................................................................... 7 3.1 3 WorlqTow Managed Processes .............................................................................. 8 3.1 4 Distributed-Pipelined / Coupled processes ............................................................................. 9 3.1 5 Tightly Coupled Processes ........................................................................ 9 3.2 Grid Data Models ..................................................................................................................... 10 3.2.1 Occasional Access to Multiple Tertiary Storage Systems ..................................................... 11 3.2.2 Distributed Analysis of Massive Datasets Followed by Cataloguing and Archiving ...........
    [Show full text]
  • UNICORE D2.3 Platform Requirements
    H2020-ICT-2018-2-825377 UNICORE UNICORE: A Common Code Base and Toolkit for Deployment of Applications to Secure and Reliable Virtual Execution Environments Horizon 2020 - Research and Innovation Framework Programme D2.3 Platform Requirements - Final Due date of deliverable: 30 September 2019 Actual submission date: 30 September 2019 Start date of project 1 January 2019 Duration 36 months Lead contractor for this deliverable Accelleran NV Version 1.0 Confidentiality status “Public” c UNICORE Consortium 2020 Page 1 of (62) Abstract This is the final version of the UNICORE “Platform Requirements - Final” (D2.3) document. The original version (D2.1 Requirements) was published in April 2019. The differences between the two versions of this document are detailed in the Executive Summary. The goal of the EU-funded UNICORE project is to develop a common code-base and toolchain that will enable software developers to rapidly create secure, portable, scalable, high-performance solutions starting from existing applications. The key to this is to compile an application into very light-weight virtual machines - known as unikernels - where there is no traditional operating system, only the specific bits of operating system functionality that the application needs. The resulting unikernels can then be deployed and run on standard high-volume servers or cloud computing infrastructure. The technology developed by the project will be evaluated in a number of trials, spanning several applica- tion domains. This document describes the current state of the art in those application domains from the perspective of the project partners whose businesses encompass those domains. It then goes on to describe the specific target scenarios that will be used to evaluate the technology within each application domain, and how the success of each trial will be judged.
    [Show full text]
  • DC DMV Communication Related to Reinstating Suspended Driver Licenses and Driving Privileges (As of December 10, 2018)
    DC DMV Communication Related to Reinstating Suspended Driver Licenses and Driving Privileges (As of December 10, 2018) In accordance with District Law L22-0175, Traffic and Parking Ticket Penalty Amendment Act of 2017, the DC Department of Motor Vehicles (DC DMV) has reinstated driver licenses and driving privileges for residents and non-residents whose credential was suspended for one of the following reasons: • Failure to pay a moving violation; • Failure to pay a moving violation after being found liable at a hearing; or • Failure to appear for a hearing on a moving violation. DC DMV is mailing notification letters to residents and non-residents affected by the law. District residents who have their driver license or learner permit, including commercial driver license (CDL), reinstated and have outstanding tickets are boot eligible if they have two or more outstanding tickets. If a District resident has an unpaid moving violation in a different jurisdiction, then his or her driving privileges may still be suspended in that jurisdiction until the moving violation is paid. If the resident’s driver license or CDL is not REAL ID compliant (i.e., there is a black star in the upper right-hand corner) and expired, then to renew the credential, the resident will need to provide DC DMV with: • One proof of identity; • One proof of Social Security Number; and • Two proofs of DC residency. If the resident has a name change, then additional documentation, such as a marriage license, divorce order, or name change court order is required. DC DMV only accepts the documents listed on its website at www.dmv.dc.gov.
    [Show full text]
  • Power and Energy Characterization of an Open Source 25-Core Manycore Processor
    Power and Energy Characterization of an Open Source 25-core Manycore Processor Michael McKeown, Alexey Lavrov, Mohammad Shahrad, Paul J. Jackson, Yaosheng Fu∗, Jonathan Balkind, Tri M. Nguyen, Katie Lim, Yanqi Zhouy, David Wentzlaff Princeton University fmmckeown,alavrov,mshahrad,pjj,yfu,jbalkind,trin,kml4,yanqiz,[email protected] ∗ Now at NVIDIA y Now at Baidu Abstract—The end of Dennard’s scaling and the looming power wall have made power and energy primary design CB Chip Bridge (CB) PLL goals for modern processors. Further, new applications such Tile 0 Tile 1 Tile 2 Tile 3 Tile 4 as cloud computing and Internet of Things (IoT) continue to necessitate increased performance and energy efficiency. Manycore processors show potential in addressing some of Tile 5 Tile 6 Tile 7 Tile 8 Tile 9 these issues. However, there is little detailed power and energy data on manycore processors. In this work, we carefully study Tile 10 Tile 11 Tile 12 Tile 13 Tile 14 detailed power and energy characteristics of Piton, a 25-core modern open source academic processor, including voltage Tile 15 Tile 16 Tile 17 Tile 18 Tile 19 versus frequency scaling, energy per instruction (EPI), memory system energy, network-on-chip (NoC) energy, thermal charac- Tile 20 Tile 21 Tile 22 Tile 23 Tile 24 teristics, and application performance and power consumption. This is the first detailed power and energy characterization of (a) (b) an open source manycore design implemented in silicon. The Figure 1. Piton die, wirebonds, and package without epoxy encapsulation open source nature of the processor provides increased value, (a) and annotated CAD tool layout screenshot (b).
    [Show full text]
  • MISP Objects
    MISP Objects MISP Objects Introduction. 7 Funding and Support . 9 MISP objects. 10 ail-leak . 10 ais-info . 11 android-app. 12 android-permission. 13 annotation . 15 anonymisation . 16 asn . 20 attack-pattern . 22 authentication-failure-report . 22 authenticode-signerinfo . 23 av-signature. 24 bank-account. 25 bgp-hijack. 29 bgp-ranking . 30 blog . 30 boleto . 32 btc-transaction . 33 btc-wallet . 34 cap-alert . 35 cap-info. 39 cap-resource . 43 coin-address . 44 command . 46 command-line. 46 cookie . 47 cortex . 48 cortex-taxonomy . 49 course-of-action . 49 covid19-csse-daily-report . 51 covid19-dxy-live-city . 53 covid19-dxy-live-province . 54 cowrie . 55 cpe-asset . 57 1 credential . 67 credit-card . 69 crypto-material. 70 cytomic-orion-file. 73 cytomic-orion-machine . 74 dark-pattern-item. 74 ddos . 75 device . 76 diameter-attack . 77 dkim . 79 dns-record . ..
    [Show full text]
  • Horus: Large-Scale Symmetric Multiprocessing for Opteron Systems
    HORUS: LARGE-SCALE SYMMETRIC MULTIPROCESSING FOR OPTERON SYSTEMS HORUS LETS SERVER VENDORS DESIGN UP TO 32-WAY OPTERON SYSTEMS. BY IMPLEMENTING A LOCAL DIRECTORY STRUCTURE TO FILTER UNNECESSARY PROBES AND BY OFFERING 64 MBYTES OF REMOTE DATA CACHE, THE CHIP SIGNIFICANTLY REDUCES OVERALL SYSTEM TRAFFIC AS WELL AS THE LATENCY FOR A COHERENT HYPERTRANSPORT TRANSACTION. Apart from offering x86 servers a to remote quads. Key to Horus’s performance migration path to 64-bit technology, the is the chip’s ability to cache remote data in its Opteron processor from AMD enables glue- remote data cache (RDC) and the addition of less eight-way symmetric multiprocessing Directory, a cache-coherent directory that (SMP). The performance scaling of impor- eliminates the unnecessary snooping of tant commercial applications is challenging remote Opteron caches. above four-way SMP, however, because of the For enterprise systems, Horus incorporates less-than-full interconnection. Interconnect features such as partitioning; reliability, avail- wiring and packaging is severely taxed with an ability, and serviceability; and communica- eight-way SMP system. tion with the Newisys service processor as part Scaling above an eight-way SMP system of monitoring the system’s health. Rajesh Kota requires fixing both these problems. The In performance simulation tests of Horus Horus application-specific IC, to be released for online transaction processing (OLTP), Rich Oehler in third quarter 2005, offers a solution by transaction latency improved considerably. expanding Opteron’s SMP capability from The average memory access latency of a trans- Newisys Inc. eight-way to 32-way, or from 8 to 32 sockets, action in a four-quad system (16 nodes) with or nodes.1 As the “Work on Symmetric Mul- Horus running an OLTP application was less tiprocessing Systems” sidebar shows, many than three times the average memory access SMP implementations exist, but Horus is the latency in an Opteron-only system with four only chip that targets the Opteron in an SMP Opterons.
    [Show full text]
  • Embedded Multicore: an Introduction
    Embedded Multicore: An Introduction EMBMCRM Rev. 0 07/2009 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support Information in this document is provided solely to enable system and software USA/Europe or Locations Not Listed: implementers to use Freescale Semiconductor products. There are no express or Freescale Semiconductor, Inc. implied copyright licenses granted hereunder to design or fabricate any integrated Technical Information Center, EL516 circuits or integrated circuits based on the information in this document. 2100 East Elliot Road Tempe, Arizona 85284 Freescale Semiconductor reserves the right to make changes without further notice to +1-800-521-6274 or any products herein. Freescale Semiconductor makes no warranty, representation or +1-480-768-2130 www.freescale.com/support guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH any product or circuit, and specifically disclaims any and all liability, including without Technical Information Center limitation consequential or incidental damages. “Typical” parameters which may be Schatzbogen 7 provided in Freescale Semiconductor data sheets and/or specifications can and do 81829 Muenchen, Germany vary in different applications and actual performance may vary over time. All operating +44 1296 380 456 (English) +46 8 52200080 (English) parameters, including “Typicals” must be validated for each customer application by +49 89 92103 559 (German) customer’s technical experts. Freescale Semiconductor does not convey any license +33 1 69 35 48 48 (French) under its patent rights nor the rights of others.
    [Show full text]
  • Certification of Avionics Applications on Multi-Core Processors: Opportunities and Challenges
    ™ AN INTELL COMPANY Certification of Avionics Applications on Multi-core Processors: Opportunities and Challenges WHEN IT MATTERS, IT RUNS ON WIND RIVER CERTIFICATION OF AVIONICS APPLICATIONS ON MULTI-CORE PROCESSORS: OPPORTUNITIES AND CHALLENGES EXECUTIVE SUMMARY Developers of avionics systems are increasingly interested in employing multi-core pro- cessors (MCPs). MCPs are especially suited to the lower size, weight, and power (SWaP) consumption requirements of avionics systems. However, MCPs pose many more system implementation and certification challenges than do typical single-core or multiple dis- crete processor solutions. This paper is intended to provide guidance on the certification challenges of multi-core solutions, as well as an update on the work at Wind River® to develop commercial off-the-shelf (COTS) RTCA DO-178C DAL A certification evidence packages for VxWorks® 653 Multi-core Edition platform. TABLE OF CONTENTS Executive Summary . 2 The Challenge of Multi-core Certification . 3 Business Challenges . 3 Technical Challenges . 3 Certification of an ARINC 653 RTOS on Multi-core Processor Architecture . 5 Wind River VxWorks 653 RTOS Multi-core Requirements . 5 DO-178C DAL A Certification Strategy for VxWorks 653 on QorIQ . 6 Future Challenges . 6 Conclusion . 6 ™ 2 | White Paper AN INTEL COMPANY CERTIFICATION OF AVIONICS APPLICATIONS ON MULTI-CORE PROCESSORS: OPPORTUNITIES AND CHALLENGES THE CHALLENGE OF MULTI-CORE CERTIFICATION hardware costs and the impact of hardware obsolescence, thus Multi-core processors have delivered significant performance providing long-term benefits for a program . gains for general purpose enterprise applications over the last In addition, the use of a COTS DO-178C certification approach decade . However, their use in safety-critical avionics systems and COTS certification packages for an ARINC 653–compliant poses some unique challenges that have slowed adoption and RTOS can also drastically reduce a program’s DO-178C certifi- deployment in this market .
    [Show full text]