Version 1.28 FUJITSU MICROELECTRONICS EUROPE Development tools for 16LX Family
DevKit16 User Guide DEVELOPMENT TOOLS FOR 16LX FAMILY DevKit16 User Guide Table of Content
What is in this Guide...... 4 What is not included in this guide ...... 5 Where to find news, options, next beans, next CPU boards, latest FAQ and support ...... 5 What is included in DevKit16...... 6 Hardware ...... 6 Software...... 6 DevKit16 Features and Technical Specification ...... 8 5 in 1 combo of HW features...... 8 Additional HW features...... 8 Open HW architecture...... 9 Getting Started ...... 10 Technical requirements to run software ...... 10 HW installation...... 10 Default settings for SOFTUNE ...... 11 Default settings for Processor Expert(TM)...... 12 DevKit16 SW overview ...... 12 Softune WorkBench ...... 12 PROCESSOR EXPERT(TM) ...... 12 SW installation ...... 15 Get it running ...... 16 Design application with Processor Expert(TM) and run it using Softune Workbench monitor debugger...... 16 Run first application using Softune WorkBench and FUJITSU monitor debugger...... 16 Run first application using Processor Expert(TM)and its Debugger&Kernel ...... 17 Processor Expert tutorial...... 19 Create your own tutorial (step by step)...... 19 Application Debug ...... 22 Software debuggers...... 22 Benefits of DevKit16 for software debugging...... 23 Softune Workbench and Fujitsu monitor debugger ...... 24 Processor Expert(TM) debug kernel features ...... 25 Flash It!...... 27 Overview of DevKit16 FLASH programming tool ...... 27 Installing the FLASH programming tool...... 28 Installing the FLASH programming tool...... 28 Starting the FLASH programming tool...... 28 Description of controls...... 28 Commonly used settings of the controls...... 30 Necessary Devkit16 mainboard HW settings...... 31 How to burn user program into the FLASH ...... 31 How to burn the SOFTUNE debug monitor...... 32 How to burn the PE debug kernel ...... 33 How to burn the CPU FLASH without Devkit16...... 34 Running burned program ...... 35 FlashTool commands - parameters ...... 35 Notes ...... 35 Error Messages:...... 36 Processor Expert beans IntFLASH and ExtFLASH – runtime support of FLASH access and design time checks...... 37 CPU board for MB90F543 description...... 38 CPU Board overview...... 38 Connectors ...... 39 Jumpers, buttons and switches ...... 42 Default jumper settings...... 45 Main board description...... 46 Main board overview ...... 46 Memories...... 48 FPGA...... 48 CAN interfaces...... 48 UART interfaces...... 48 LED Diodes ...... 49 Audio amplifier and speaker...... 49 Connectors ...... 50 Switches...... 53 Jumpers...... 55 The Mainboard Programmer‘s Reference...... 61 Register addresses and chip selects...... 61 Interrupts ...... 61 Simulated CPU ports (P0, P1, P2, P3 of Fujitsu FLASH CPU)...... 62 Add-on FPGA ports ...... 63 Add-on FPGA output-only port...... 64 User UART...... 65 I2C...... 67 Keyboard controller...... 70 LED display ...... 71 FPGA EEPROM ...... 71 System control registers...... 73 Default jumper settings...... 81 What to do if ...... 82 Get the most from DevKit16 ...... 84 Download the current SW and HW updates ...... 84 Check the net for newest beans...... 84 DevKit16 Power Supply Requirements ...... 85 Warranty and Disclaimer ...... 86 Revision and Error List ...... 88 Appendix...... 90 Chapter 1
What is in this Guide
What you’ll find inside this guide and few words about its organization
evKit16 is designed to help you to design applications with FUJITSU 16LX MCU family members. This guide should lead you – step by D step - to get your results soon. You could print a copy of this document for further use, when you start work with the DevKit16 boards. DevKit16 provides a lot of features, so this guide introduces them using top- down approach. The guide describes how to use DevKit16 for the 16LX series MCU, allowing to get acquainted with the methods for developing and debugging 16LX-driven applications.
Chapter 2: What is included in DevKit16 provides brief information which HW and SW tools are included in package.
Chapter 3: DevKit16 features and technical specification provides necessary technical and operational information
Chapter 4: Getting Started explains how to run your first application on DevKit16 including all steps and HW and SW installation.
Chapter 5: Debug application explains methods how to debug your application on DevKit16.
Chapter 6: FLASH It! explains how to store final application in DevKit16 CPU or external FLASH.
Chapter 7,8: CPU Board Description and Main board Description provide explanation how to control the DevKit16 configurations and detailed description of CPU and main board including all DIP switches, jumpers and connectors.
Chapter 9: Introduction to SW tools explains, what the DevKit16 SW tools could do for you.
4 Chapter 10: Main board Programmers Reference includes description of FPGA registers and their function.
Chapter 11: How to… includes hints for DevKit16 operation, which you should check before call technical support.
Chapter 12: Get the most from DevKit16 provides hints and tips how to benefit from DevKit16 and its options
Chapter 13: Power supply requirements
Chapter 14: Revisions and errors list
Appendix includes schematics of DevKit16 and other technical references
WHAT IS NOT INCLUDED IN THIS GUIDE
This guide is not detailed manual for the CPU, parts and software tools. Please find more in the following resources:
MCU, Softune Workbench and tools – FUJITSU Micros CD ROM (Ver 3.0 or higher)
Processor Expert(TM) and tools – DEVKIT16 Software CD ROM
Parts and other HW components – datasheets of their producers
WHERE TO FIND NEWS, OPTIONS, NEXT BEANS, NEXT CPU BOARDS, LATEST FAQ AND SUPPORT
Please visit DevKit16 WEB site www.processorexpert.com/devkit16 for news and giveaways. You could also register in order to obtain news by mail.
For MCUs and Fujitsu technologies please visit FUJITSU WEB site www.fujitsu-fme.com.
When you need additional CPU personality board please call your nearest FUJITSU subsidiary or authorized FUJITSU distributor. You should specify:
• version of CPU you need
• whether you need CPU to be soldered or mounted in a socket. Socket version is provided in order to allow use of FUJITSU emulator
5 Chapter 2
What is included in DevKit16
Brief overview of what you’ll find inside DevKit16 package
DevKit16 package contains both HW boards and SW tools on CD.
HARDWARE
The DevKit16 HW includes
• CPU personality board (default for MB90F543 MCU)
• Main board
• Serial cable to connect PC and DevKit16 When you need additional CPU board please call your nearest FUJITSU subsidiary or authorized FUJITSU distributor. According to your request there are available CPU boards with soldered CPU or with 100pin socket. Socket versions are intended to support FUJITSU emulator.
SOFTWARE
Two CDs are included in package.
• CD 1: FUJITSU Micros Documentation & Software
• CD 2: DevKit16 Software
CD 1 includes all the
• MCUs informations
• Softune Workbench with C compiler, assembler, linker and other tools. CD 2 provides tools for Rapid Application Development support on DevKit16.
6 • Fujitsu Monitor Debugger for MB90F543 to provide debug for Softune on DevKit16
• Processor Expert(TM)
• Bean Wizard
• Processor Expert(TM) Debug Kernel for MB90F543
• DevKit16 FLASH Programming tool
7 Chapter 3
DevKit16 Features and Technical Specification
This chapter introduces features of DevKit16 and provides necessary technical and operational information for DevKit16.
he FUJITSU DevKit16 concentrates the combination of five most T requested HW development kits features:
5 IN 1 COMBO OF HW FEATURES
• Standard Starter Kit
• FLASH Development Kit
• CAN Development Kit
• Application Board
• Rapid Hardware Prototyping
ADDITIONAL HW FEATURES
• Open HW architecture
• Keeps CPU resources available for user
• Supports single chip debug for CPUs from 16LX family with External Bus Interface
• Supports jumperless CPU mode control
8 • provides large RAM and FLASH with fast download and programming
• provides additional peripheral devices – PC keyboard interface, EEPROM, LED Display, I2C
• Optional low level HW debug support (breakpoints, trace)
OPEN HW ARCHITECTURE
• Two buses for 16LX family members are defined: Interface Bus and Device Bus
• Interface Bus provides compatibility for Main board
• Device bus is located on CPU board and provides compatibility with use of CPU peripherals
• This allows to provide low cost CPU personality boards, which are compatible with the Interface and Device Bus and reflects different MCU pin layout
• Expansion buses/connectors: User Prototype connector with user chip select and bus signals, FPGA User Programmable Pins (40), CPU AD converter connector
• Upgradable FPGA content
Warning: this kit must only be used for test applications in a laboratory environment.
9 Chapter 4
Getting Started
Introduction to DevKit16 philosophy and how to run your first application on DevKit16 including all steps of HW and SW installation.
evKit16 is designed as a low cost but highly functional development platform for FUJITSU 16LX MCU family. It is not a high end D emulator but it provides significant advantages for MCUs with External Bus Interface. In combination with powerful software tools including debuggers it provides enough capacity for fast application development.
TECHNICAL REQUIREMENTS TO RUN SOFTWARE
Please check the specifications which are already available for Fujitsu Softune WorkBench on FUJITSU CD ROM. The Processor Expert(TM) conditions are available in its README.TXT file.
HW INSTALLATION
Please remove carefully CPU board and the Main board from antistatic boxes and connect them according the photo.
Power supply (regulated, 9-12V, center pin=GND )
RS-232
10 Check if all switches and jumpers match the settings as described below in Default Settings for Softune. If there are changes please first check www.processorexpert.com/devkit16 for the latest version of this guide and ! correct the settings according it. Check if your power supply match specifications in Power Supply Requirements chapter. If these requirements are matched, please connect power supply to CPU board power supply connector.
When power is on, you should easily check if
• Red LED on CPU board lights on
• Green LED on Main board lights on without blinking When you experience something different, please check your power supply or try to find solution in chapter How to... When this step went OK, switch power off and connect DevKit16 with PC using attached cable to USER (FPGA) UART and a free serial port on PC, which is not used by other device in PC.
DEFAULT SETTINGS FOR SOFTUNE
For a quick reference, take a look at the following pictures, that shows the (default) setting of the Mainboard and 90F543 CPU board for Softune. For more detailed description, see the figures of CPU board for 90F543 and Mainboard layout in the "CPU Board for MB90F543 description" and "Mainboard description" chapters.
11 DEFAULT SETTINGS FOR PROCESSOR EXPERT(TM)
Softune Workbench and Processor Expert(TM) DevKit16 settings for debugger are compatible with one exception: serial line reset is inverted so J1 (serial line reset polarity selection) must be in the 1-2 position for Softune, but in the 2-3 position for PE. Serial line reset is used for remote reset of DevKit16 by both environments.
The jumper J10 (MSEL) is not used in the current versions of PE kernel or Softune monitor debugger. In the future, there might be a version of an universal kernel, that will support both Softune and PE debuggers. Then, the J10 will have to be SHORT when using the Softune debugger and OFF with the PE.
DEVKIT16 SW OVERVIEW
You will need to install both Softune and Processor Expert(TM) to run the following examples on DevKit16. Please see DevKit16 Features and technical specification to check, if your PC match software requirements. Please also check latest revision list for Softune tools and readme.txt for Processor Expert(TM).
SOFTUNE WORKBENCH
Softune Workbench provides all the classic tools. In order to use it for application debug on DevKit16, FUJITSU Monitor Debugger must be installed in Main board FLASH to establish communication between PC and the debugged target application.
PROCESSOR EXPERT(TM)
What is Processor Processor Expert(TM) provides its own workbench Expert ? including debugger. For the program compilation it uses Softune tools – compiler, assembler, linker- as command line tasks.
This workbench features component oriented application Component oriented application design creation, CPU knowledge system, components library, design time constraints to verify CPU and other HW settings before use it in runtime.
(TM) Management of MCU Main task of Processor Expert is to manage CPU and other HW resources and Devkit16 and to allow you virtual prototyping and design. resources Code generation from beans, ability to maintain user and generated code, event based structure significantly reduce effort in comparison with classic tools.
Generation of C Component = bean is the essential encapsulation of functionality. For instance sources helps to build TimerInt bean encapsulates all CPU resources on appropriate CPU, which are your apps quickly ! able to provide timing and hardware interrupt. MB90F543 CPU provides up to
12 21 such resources, which you can choose using TimerInt property Timer according to the required timing parameters and accuracy in property Interrupt period.
If you need functionality, you can choose appropriate bean and PE offers the possible MCU resources
Figure: Selecting a CPU timing resource for the TimerInt bean
Figure: Setting the interrupt period of the TimerInt bean
13 On Processor Expert(TM) beans palette you’ll find many components, which we call Embedded Beans(TM). This component were selected to cover the most required functionality usually used for microcontroller applications – from handling port bit operations, external interrupts, timer modes up to serial asynchronous/synchronous communications, A/D converter, I2C, CAN and etc.
Bean properties, Bean provides clear interface, which can be controlled by an user in design time methods and events using Beans Inspector. Beans Inspector has several pages for bean properties, methods and events.
By setting the bean properties, user defines future behavior of the bean in runtime. PE checks your setting in desing time - including timing and generated code !
User can also choose which methods will be included in an application, because they are needed - and which not.
Use events to build ISRs Events, if used, can be raised by interrupt from HW resource (timer, SIO,..) or fast by pure software reason (overflow,..) in application runtime. You can enable or disable interrupts using bean methods and define priority for raise of event and for executing its ISR – Interrupt Service Routine. HW ISR provided by bean handles reason of interrupt. If the interrupt vector is shared by two (or more) resources then this ISR provides identification of resource. Then user is notified by calling of user event handling code.
CPU bean CPU bean has special meaning - you can use more instances of it, and each of these instances can hold different setting. This makes the application design time with Processor Expert and any microcontroller very short. First choose and setup CPU bean, add another ones, modify their properties, select methods and events and choose Codesign. Processor Expert generates all code from beans according your settings, which is well commented. You can choose View | View All Generated Sources and in viewer, the CPU module with resources initialization part and other beans modules appears.
PE as a virtual This is of course only part of application code, which was created by „virtual (TM) application engineer application engineer“- Processor Expert CPU knowledge system and solution bank. Solution bank is created from hand written and tested code optimized for efficiency. This solutions are selected and configured in code generation process.
Share your code with Choose View | View/Edit Main&Event code and two modules appear in editor your virtual application – pregenerated main and event module. Enter your code to desired events, engineer ! provide main code, add existing sources – and build application using classic tools (select Tools | Make from the main menu) – compiler, assembler, load to DevKit16, debug it before final burn-in – these are typical steps when working with Processor Expert(TM).
Pictures, files and Another beans help you to include pictures, files, sounds, stringlists to your sounds in your application very quickly. application
14 HW resources on Main board for instance PC-AT Keyboard interface encapsulation are also „beaned“ .
Other beans could be obtained on www.processorexpert.com/devkit16 or created by yourself from your existing sources, for instance FFT (Fast Fourier transform). Another beans can accumulate other existing beans – they can inherit their properties, methods events.
Design your own beans Imagine that you want share a bean with other developers. And such a bean can and share it with others drive LED segment display. Because it is used often for different hardware configurations – on different CPU pins – then it must be portable and indepedent on CPU resources – port pins on which it is connected. To refresh it a timer is needed, also portable.
Such beans are called SW beans. SW beans can be pure SW beans (FFT) or can inherit even multiple beans, which encapsulate HW resources. The advantage is independence on physical layer, portability and share of once written and tested code.
Build your own beans For our example we simply choose BitIO, BitsIO or ByteIO and TimerInt beans from other ones using from delivered bean library as parents. New LED display bean will provide inheritance properties of bean reference type for this bean. This allows in design time for new bean access its parents properties and define physical connection pins or timer resources. Additionally new bean will have its own properties and methods. Methods can be constructed using parent beans methods. The same situation is with events.
Beans Wizard Don’t be afraid about the complexity of this – simply choose from Processor Expert Tools menu Beans Wizard tool, which arranges all for you. You should only enter the code of methods and events, save new bean and install it on Beans Palette or share it with others. The interested beans could be offered for other users using DevKit16 support WEB site.
Additional information about Processor Expert and beans libraries please find in its online help or in www.processorexpert.com site.
SW INSTALLATION
Each software – Softune and Processor Expert(TM) has its own installation. You should find 16bit tools full installation on FUJITSU Softune CD and run its setup.exe. On DevKit16 CD choose directory “Install” and run setup.exe. Installation will navigate you, for documentation reading you need to install also Acrobat Reader and Microsoft compressed help support.
15 GET IT RUNNING
After successful installation, switch the power supply of DevKit16 on, check the red power LED on the CPU and connection with PC. When the Devkit16 with its default settings (see fig. 2) is connected to the PC, it is held in the reset state – the LED diode D11 is shining until the debug session in Softune is started. Before the next step you can try to move the J1 jumper to the 2-3 position, so the D11 goes off and on the Mainboard LED display, the Fujitsu Monitor Debugger version number in the form of “X.X.” appears (the current version number in the time of writing this manual was “1.3.”). Then you can put the J1 back to 1–2 position.
If the version number is not in the form of “X.X.” (the last point is important), it means that there is the Processor Expert kernel or other program burned in the Mainboard FLASH. In such a case, you must burn the Fujitsu debug monitor into the Devkit16 - please refer to the chapter 6 (Flash It), paragraph “How to burn Fujitsu debug monitor”.
DESIGN APPLICATION WITH PROCESSOR EXPERT(TM) AND RUN IT USING SOFTUNE WORKBENCH MONITOR DEBUGGER
Run Processor Expert(TM), choose Open existing project from startup screen and select under PE\Projects\Demo.Leds\LEDS.pe. Please choose Options | Environment and Project Options. This opens Options window on Environment options page. Uncheck item „Succesful Make and Build automatically starts PE debug“ and confirm OK.
Choose Tools | Build or Ctrl-B. After successful Build choose Tools | Fujitsu Softune Workbench (default hot key F11). After Softune Workbench starts, you could notice that the same project is open in Softune.
RUN FIRST APPLICATION USING SOFTUNE WORKBENCH AND FUJITSU MONITOR DEBUGGER
In Softune Workbench, build the project using Ctrl-F8. Project settings for debugger are prepared for you, the only thing you must set up are the debug communication properties - in Project | Setup, page Debug – select the setup name from the Build setup name list, in the next dialogs, choose “Monitor debugger”, COM1 or COM2, 9600Bd, Auto load …, and click Finish.
Note: in the Processor Expert™ installation, there is also the 38400 Bd version of the Fujitsu debug monitor available, but the 9600 Bd version is burned to the Devkit16 by default.
After setting the communication properties, select Debug | Start Debug and wait till debugging session is started. If it went OK, you should see window with
16 Start.asm with marked position of Program Counter. Run program using F5 shortcut key. You should see diagnostic LEDs blinking in various manner.
If there is a communication error message, please check your connection with the DevKit16. For further information please check Softune documentation and chapter What to do if...
RUN FIRST APPLICATION USING PROCESSOR EXPERT(TM)AND ITS DEBUGGER&KERNEL
To use debug capabilities of Processor Expert(TM) for 16LX family including high speed (115200Bd) download, we need to burn Processor Expert(TM) Debug Kernel to DevKit16 Main board FLASH instead of Fujitsu Monitor Debugger.
In Processor Expert(TM) choose Tools | Burn PE Debug Kernel IR. This will run DevKit16 FLASH Programming tool with correct parameters in Auto program mode. For more detailed description about burning the PE debug kernel, refer to chapter 6, section “How to burn the PE debug kernel”).
You should change the Main board System Configuration DIP switch as follows:
• setting for CPU FLASH programming mode
ON
1 2 3 4 5 6 7 8
• Set the J1 jumper to the 2-3 position
Note: the CPU FLASH is not being programmed, this mode is used only to access Main board FLASH
Then, press OK. If everything went OK, the message box „Run burned program?“ appears. Then choose button „Don’t Run“. For troubleshooting please check the DevKit16 FLASH Programming Tool chapter or How to... one.
Note, that you should use similar way to burn the FUJITSU Softune Monitor Debugger back to Main board FLASH. In Processor Expert menu choose Tools | Burn Fujitsu monitor to Ext.Flash
17 Now you should change Main board System configuration DIP switch as follows:
• setting for CPU external bus mode, FLASH in UMB
ON
1 2 3 4 5 6 7 8
Now, load the „Demo.LEDs“ project in Processor Expert. Check if there is no reported error after project loads, press F9 shortcut key, which starts codesign, builds the project and starts the debugger. You should see the disassembler window with Start.asm and actual PC position after start. Choose Debug | Run or Ctrl-F9 to run program.
If it is running correctly you should see demo with diagnostic LEDs on Main board.
If there is an error – Processor Expert provides approach to detect it. Double click on error message(s) inside error window. If the reason is a component, you’ll be navigated to it by selecting bean in Project panel and opening its Bean Inspector. Item related to error is marked by red color, so related Inspector’s page and its item could be located.
The usual problem appears when you install Softune to another then recommended default path.
Error: Application not found: xxxxxx is reported.
Path to Softune tools should be correctly set - see Project panel CPUs, double click on active CPU icon, Beans Inspector | Compiler, property Tools Directory.
More please find inside Processor Expert(TM) Help.
18 PROCESSOR EXPERT TUTORIAL
Tutorial project for Processor Expert and DevKit16 is located in directory ProcessorExpert\Projects\Demo.Tutorial\LED.pe. This demo project contains two BitIO beans connected to LEDs on DevKit16 and ExtInt bean connected on INT2. The LEDs are toggled on external interrupt. The interrupt is generated by the PC keyboard.
CREATE YOUR OWN TUTORIAL (STEP BY STEP)
In this short course you can learn how to create simple project including CPU, two BitIO beans and ExtInt bean. BitIO beans are set as output and control the LEDs and ExtInt bean captures the external interrupt and switches the LEDs.
This project is also located in Processor Expert sub-directory Project\Demo.Tutorial\.
• Open Processor Expert from Window's Start menu.
• Open new project. Press button Open new project on startup panel or use command in main menu | File | New project.
• Select CPU configuration. There are several prepared projects included in the Processor Expert. These projects contain typical CPU settings and two configurations: one configuration for debug and second one for release (final) version of the application. Select project: MB90540 16-bit external bus.
• Add the first bean: Select Input/Output page on the Beans Palette in the Processor Expert main window. Click on the button BitIO to add BitIO bean into current project.
• Set-up the bean. Open bean inspector using command main menu | View | Inspector or press Ctrl+I and select page Properties. Change following values for properties:
Bean name RedLED Pin for I/O P47_SCK2 Direction Output
Select page Methods and choose only method NegVal as generated and other methods as not generated.
19 • Add next beans: BitIO and ExtInt and set-up the properties and methods according following tables. To set content of the bean inspector click on the bean name in the project panel. BitIO: Bean name GreenLED Pin for I/O P46_SOT2 Direction Output Init. Value 1
The only one generated method : NegVal Note: DevKit16 contains only red LEDs conntected to the I/O ports of the CPU. Do not be confused from the name of the bean.
ExtInt: Bean name Button Pin for I/O P92_INT2 Generate interrupt on rising edge
Select methods: Enable, Disable. Select events: OnInterrupt.
• Codesign. If there are no errors in your project select command main menu | Codesign | Codesign or press Ctrl+G to codesign code. All drivers are generated during codesign. Note: Processor Expert requires to save the project before codesign. You can do it using command File | Save project or press Ctrl+S. If you do not save project before codesign Processor Expert ask you to do it automatically.
• Edit user code. Select command main menu | Edit | Edit Event & Main Code or press Ctrl+U to open internal editor and edit the generated code. Two files will be opened: event module EVENT.C and main module (name of the main module is the same as name of the project).
20 Insert following code into main function located in main module: void main(void) { /* enable PC keyboard in FPGA */ *(__far byte *)0xEBUL|=0x10; /* enable ExtInt bean */ Button_Enable(); /* loop */ for(;;); } Then double-click on the Beans | Button:ExtInt | OnInterrupt item in the project panel tree and the event's handling routine will be selected in the editor. Drag&drop methods NegVal from beans GreenLED and RedLED into ButtonOnInterrupt event routine using mouse: void ButtonOnInterrupt(void) { RedLED_NegVal(); GreenLED_NegVal(); }
• Compile. Select command main menu | Tools | Make or press F9 to run internal make. Make uses Softune command line tools to compile and link generated and user code. Note: Processor Expert requires to save all files in internal editor. You can do this unis command editor local menu | File | Save or press Ctrl+S. If you check option main menu | Options | Environemnt Options | Autosave file before running codesign or external tool Processor Expert saves all files automatically.
• Debug. Check the settings of jumpers on the DevKit16, connect your PC with your DevKit16 board using serial cable, connect power supply to DevKi16 and select command main menu | Debug | Start Debug. If you find any problem with initialization of the debugger please refer to debugger documentation: open Cpu Inspector - page Debugger and press F1. Note: You can check option: main menu | Options | Environment Options | Successful make or build automatically start PE Debug to start debugger automatically after make or build.
21 Chapter 5
Application Debug
Overview of debug tools for DevKit16 and their features
he application could be debugged on DevKit16 by using five basic approaches. High end debugging requires FUJITSU emulator and CPU T personality board with socket. Another way – low end - is simulation; Softune Workbench provides MCU instruction simulator, but it doesn’t simulate MCU peripherals in current version. It is very useful to simulate algorithms. Very experienced developers often use technique of their own monitoring of running program behavior using character oriented (display) device. This approach is also supported by DevKit16 and optional VGA graphic card, which allows connect standard VGA display to DevKit16 and provides fast buffered access (much faster than serial line). But inside this chapter we’ll concentrate to so called „software debugging techniques“ which are supported by both Softune Workbench and Processor Expert(TM) environments.
SOFTWARE DEBUGGERS
Software debuggers provide good ratio functionality/cost. The target system is equipped with small debug kernel, which provides back-end for PC Debugger – front-end. CPU software interrupts are used for breakpoints, stepping functions. To realize this function, user code must be located in RAM type memory. 16LX MCUs provides „ROM Correction Modules“ peripheral, which could be used for two hardware breakpoints. Unfortunately this is not enough to realize usual debug functions and more, this solution works for internal memory only.
The simplest kernels are „live“ only when user program is stopped, so there is no activity during application runtime. The better solution provides ability to monitor/modify selected variables on demand even in application runtime. This feature significantly reduces debug effort, because for instance PID regulator could be tuned during runtime. This kind of interface is usually needed for distributed control and visualization systems.
Advantage of software debuggers is that they could be adapted for your own microprocessor system.
22 BENEFITS OF DEVKIT16 FOR SOFTWARE DEBUGGING
DevKit16 provides the same feature as high end emulator – application thinks, that works with single chip and runs program in ROM or FLASH, but in fact the program is running in Main board RAM in final address space under software debugger control or as standalone.
This is possible using CPU simulated ports P0-P3 for application instead of „native“ ones. The MCU then can work in External Bus Mode and use all Main board resources.
Non-single chip applications can benefit from large Main board RAM, FLASH and use Prototype connector with prepared chip select, MCU bus signals.
The Main board logic also provides hardware breakpoints (in default version of FPGA only one – please check DevKit16 WEB for FPGA upgrades) which works for CPU External Bus Interface and provides break on read or write or both accesses.
The argument, that this hardware breakpoint cannot include MCU RAM based variables means minor limitation, because critical variables could be linked by tools to appear in Main board RAM. Other limitation is that breakpoint uses external interrupt line of CPU, which should run on top priority.
The software debugger kernel is started after reset (from Main board FLASH in UMB) then RAM is swapped with FLASH, which means RAM appears on UMB and FLASH with kernel in LMB. Then the application code can be downloaded into Main board RAM (in UMB). The application is debugged at addresses where it will burned.
Running the application in RAM immediately after reset (USW switch ON) In Softune or Processor Expert (TM) debug session, you can run your application immediately after reset (so it behaves as it was burned in the FLASH). The application runs from external RAM (in UMB) without debugging. To do this, you should remove all breakpoints first. Then, start debug in your debugger front-end to download application code into DevKit16. Set the USW switch to „ON“ and then press RESET button on the Main board.
Softune - Abort When USW switch is OFF – using reset button will start monitor debugger in LMB. The UKEY button is connected to the interrupt line 0 and can be used to abort Softune monitor debugger session.
To be able to debug using debug kernel or Softune monitor, it must be burned in FLASH using DevKit16 FLASH Programming tool. See chapter Flash it! for more information about burning code into flash.
23 In the next sections we will discuss basic features of debugging using Softune Workbench and Processor Expert (TM).
SOFTUNE WORKBENCH AND FUJITSU MONITOR DEBUGGER
The DevKit16 is equipped with its adaptation of Fujitsu Monitor Debugger. This adaptation features with:
• Communication speed 9600Bd or 38400Bd
• Using of FPGA UART for debug, so CPU UART(s) are available for user
• User application is debugged in final place in memory
• Frontend is Fujitsu Softune WorkBench
• For user program is available area: 0F82000H to 0FFFFFFH
• Interrupt vector table (IVT) is located on: 0FFFC00H
• For Mon. Debugger code is reserved FLASH segment 0FFH (UMB) 13H(LMB)
• IVT entries, which cannot be overwritten (for 543 CPU):
• reset • ROM Correction
• exception
• 15 – external interrupt 0,1
• Breakpoints references are stored in CPU memory range
• For other information please check FUJITSU documentation.
Note: It is necessary to use Softune version: v30L22
24 PROCESSOR EXPERT(TM) DEBUG KERNEL FEATURES
Processor Expert(TM) provides extensive support of debugging with up to 256 „software“ breakpoints, also serves HW breakpoints provided by FPGA, runtime access to application variables, C or assembler level of debugging, etc. Please for more information find Processor Expert Online Help.
PE debug kernel was developed as very tiny (3.5KB) but powerful solution, which features with high-speed communication and capacity for on demand runtime access to application variables. This access is provided by FPGA UART interrupt, which is running on selected priority, so no CPU timer and its periodic ISR overhead is used. There is list of another advantages of PE Debug kernel:
• Communication speeds up to 115200Bd.
• Using of FPGA UART for debug, so CPU UART(s) are available for user.
• User application is debugged in final place in memory.
• Frontend is Processor Expert (TM).
25 • In frontend can be choosed kind of runtime variable access – none, on demand, periodic 1s, periodic 10ms.
• Frontend provides high level functionality to see variables values also when application is stopped – in programmers editor just point the variable and as hint appears its value.
• For user program and data is available area: 0F82000H to 0FFFFFFH.
• Interrupt vector table is located on: 0FFFC00H.
• Kernel code starts at 0FFC000H or 13C000H respectively in Main board FLASH.
• IVT entries, which cannot be overwritten (for 543 CPU):
• 8 – reset
• 9 – ROM Correction, INT9
• 10 – exception
• 15 – external interrupt 0,1
• No more CPU resources are used in PE Debug kernel.
• Breakpoints references are stored in Frontend.
• For other information, please check help for the DevKit16 debugger.
262626 Chapter 6
Flash It!
The DevKit16 FLASH Programming Tool is a standalone tool that can be used to program both the external FLASH (256kB) located on the Mainboard and internal FLASH (128kB) provided by the MB90F543 CPU.
OVERVIEW OF DEVKIT16 FLASH PROGRAMMING TOOL
DevKit16 FLASH Programming Tool provides standard operations for CPU Internal FLASH memory, Main board FLASH or both.
When the PC↔DevKit16 communication uses the Mainboard FPGA UART, the programming operation can run on the highest speed of PC serial port 115200Bd.
27 To achieve this speed or to allow Mainboard FLASH programming, it must be possible to access Mainboard FPGA I/O peripherals, so the CPU external bus must be available (if you still need the P0-P3 ports for your application, you should use the Simulated ports instead). If the CPU external bus access is not possible, the communication will run only on 9600Bd (10 times slower) and only CPU internal FLASH can be programmed.
Note: none of the PE tools uses the CPU internal FLASH for its internal processing - we decided to reserve this memory just for an user.
INSTALLING THE FLASH PROGRAMMING TOOL
Currently, there are three versions of Flashtool: 1.0, which was distributed with the PE 2.32, Flashtool 1.1, which was in the beta version of PE 2.34 and Flashtool 1.2. From the Flashtool version 1.2 and higher, the version number is displayed in the flashtool window title bar. With the previous versions, the version number can be found by displaying the properties of the Flashtool.exe file (in the Windows Explorer, press right mouse button on the Flashtool.exe file and select Properties).
INSTALLING THE FLASH PROGRAMMING TOOL
The FLASH programming tool (Flashtool) is installed during Processor Expert installation. User can even choose not to install the PE but the FLASH tool only. In such a case, only files and directories necessary for using Flashtool with Devkit16 is installed (including both Fujitsu debug monitor and PE debug kernel ABI files).
The latest update for Flashtool can also be downloaded from the PE web site – see http:/www.processorexpert.com/devkit16
STARTING THE FLASH PROGRAMMING TOOL
From within the Processor Expert environment, application can be easily burned into the FLASH - just click on the Tools | Fujitsu DevKit16 Flash Programming. The FLASH Programming Tool will be run in an non- interactive mode, with PE setting all the necessary parameters automatically.
But, if you do not want to use PE environment for programming the FLASH, FLASH tool can be run in standalone mode. If you want to do this, go to the PE folder in the Windows Start menu and choose FlashTool.
DESCRIPTION OF CONTROLS
External bus free ? – If the external bus is free (no device is connected to it) the internal and external FLASH can be programmed (with communication speed 115200Bd). If not, only internal FLASH can be programmed with communication speed 9600Bd.
28 Select FLASH for programming – Select FLASH memory(ies) to be programmed – CPU (internal FLASH), Main board (external FLASH) or both (internal & external FLASH)
COM Port – Select the right COM port where you have a serial cable for communication with DevKit16.
CPU Frequency – Select the actual CPU crystal oscillator frequency. This determines the speed of serial communication.
Connect – Downloads the FLASH TOOL communication & processing kernel into the RAM, then is possible write user program into the FLASH. Before downloading the kernel, reset the CPU.
Erase whole – Erases whole FLASH - internal if „internal FLASH“ is selected, external if „external FLASH“ is selected or both if mixed mode is selected („internal & external FLASH“ )
Erase blocks – erases only selected blocks.
Blank check – checks if the selected blocks are blank. If no block is selected, then whole FLASH is checked
View memory – displays the selected range of memory (in hex numbers)
Search – Searches for user values in defined memory range
Open *.abs – Loads the absolute project which contains the user program prepared for burning into the FLASH
Write file – Writes the data from abs file into the selected FLASH memory.
Read & compare – Compares data in abs file and data in FLASH memory. If a difference is found, user is informed. After successful comparing you may Run the application without changing switches. See bellow.
Auto – It encapsulates the buttons „Erase blocks“, „Write file“ and „Read & compare“. It will erase only those blocks of FLASH memory, which aren‘t blank and which are used. Unused or clear blocks aren‘t erased. After successful burning and comparing you may Run the application without changing switches. See bellow.
Abs info – displays window with information of blocks in abs file (their location, length and type). You can see the hexadecimal view of the data in the abs file (with double-click or click by right mouse button on the selected block).
Action – Displays current action
Status of the previous action - Displays status of the last action
29 Progress - Current state of running action.
COMMONLY USED SETTINGS OF THE CONTROLS
• If you want to burn Softune debug monitor or PE debug kernel, please check the paragraph “How to burn the Softune debug monitor” (or “How to burn PE debug kernel”, respectively) first. In these paragraphs, there is a description of a non-interactive mode of the Flashtool that can be very useful when you need to burn these programs frequently. However, if you want to burn these programs interactively, continue reading this section.
Note: Prior to the Flashtool version 1.1, there used to be a special command line option "-move 13 ff", which had to be used to run the Flashtool.exe for burning the Fujitsu debug monitor. Even though this command line was encapsulated in a flash tool configuration file (*.ftc) so it was hidden to most of the users, in Flashtool 1.1 and higher versions this command line is not needed anymore. If you have any version of Flashtool prior to the 1.2, you can download the latest Flashtool installation package from the PE Web site.
• If you use standard Devkit16 (CPU board in connection with Mainboard) without any additional HW, that could cause the AD bus contention, set the “External bus free” radio button to “Yes” in Flashtool. If you use a standalone CPU board with a RS-232 adaptor on the K7 connector or an additional HW, that could cause the AD bus contention, set the “External bus free” radio button to “No”. In this case, the communication speed will be limited to 9600 Bd.
• Select which FLASH will be programmed (internal, external or both in case of a mixed mode application). E.g., when burning Fujitsu debug monitor or PE debug kernel, “external FLASH” must be chosen.
• Set the right COM port where you have a serial cable connected to DevKit16
• Set the CPU frequency
• Select required location of the Mainboard FLASH according to your project settings. The possible choices for external FLASH mode or mixed mode are:
1. external FLASH 200BC - Base address FC0000
2. external FLASH 200BC - Base address F80000 (mixed mode)
3. external FLASH 200BC - Base 100000
30 E.g., when burning Fujitsu debug monitor or PE debug kernel, select the “Base address FC0000” option.
Note: special care must be taken when burning a mixed mode application. In mixed mode, both internal and external FLASH memories are accessible in the MCU memory space. With the “external FLASH 200BC - Base address FC0000” option, the internal FLASH memory space overlaps a part of the external FLASH memory. In this case, Flashtool is unable to distinguish which FLASH should be actually burned in the overlapped area. Therefore, user should always leave the “external FLASH 200BC - Base address F80000 (mixed mode)” option ON when burning a mixed mode application. (For further details about Devkit16 and its memory maps see the UserGuideDevkit16.PDF manual, chapter “Mainboard Programmer’s Reference”.
• Now, you can click on the button „Connect “
• Flashtool is now ready to start the desired operations
NECESSARY DEVKIT16 MAINBOARD HW SETTINGS
• PC must be connected to the Devkit16 USER UART connector.
• The J1 jumper must be in the 2-3 position (the PE debugger position) and all the other jumpers must be placed according to Figure 2 on page 77
• The mainboard System configuration DIP switches must be set to “Serial FLASH Programming mode”, UART1 and 8 bit ext. FLASH access:
ON
1 2 3 4 5 6 7 8
• FPGA must be enabled – the J29 jumper must be opened.
• Now, reset system using the RST button
HOW TO BURN USER PROGRAM INTO THE FLASH
Using FlashTool Set up the Flashtool controls and Devkit16 according to the previous paragraph.
Click on button „Open *.abs” and open the compiled project
31 Click on button „Auto“ to auto erase FLASH, writing the program and verifying.
Using Processor Expert Successfully codesigned and compiled project from Processor Expert environment can be directly burned into internal/external flash using command from Tools menu. Target flash selection and path to ABS-file is generated to configuration file according to the project settings.
HOW TO BURN THE SOFTUNE DEBUG MONITOR
The current version of the Softune Debug monitor is provided in two variants, that differs in their communication speed: the first (SoftuneMonitor38400_xxx.abi, where xxx is the CPU type) communicates on 38400 Bd, the second (SoftuneMonitor9600_xxx.abi, where xxx is the CPU type) uses only 9600 Bd. When using the 38400 Bd variant, the Devkit16 UART must be configured for RTS/CTS hardware flow control mode (J9 must be in the 2-3 position), otherwise some data can be lost during the communication. To burn the Softune debug monitor to the Devkit16 external FLASH, follow these steps:
1. From the PE environment:
For the 38400 variant:
From the Tools menu, choose the item „Burn Softune Monitor for MB90xxx into Devkit16 Ext. FLASH (38400 Bd) “, where xxx stands for the CPU type (e.g., 543 or 497).
For the 9600Bd variant:
From the Tools menu, choose the item „Burn Softune Monitor for MB90xxx into Devkit16 Ext. FLASH (9600 Bd) “, where xxx stands for the CPU type (e.g., 543 or 497)..
2. Without PE
Without PE, the monitor debugger must be burned using command line:
• change the current directory to the Processor Expert installation directory (for example, c:\Program Files\PE)
• run the following command: flashtool -cfg Config\FlashTool\FujitsuDevKit16\SoftuneMonitor38400_xxx.ftc for the 38400 Bd variant (where xxx is the CPU type) or flashtool -cfg Config\FlashTool\FujitsuDevKit16\SoftuneMonitor9600_xxx.ftc for the 9600 Bd variant (where xxx is the CPU type).
32 This command runs the FlashTool with all the necessary configuration options for the debug monitor already set. FlashTool then asks for setting the CPU mode to the serial programming mode and after confirmation, it burns the debug monitor automatically to the external FLASH.
Note: If you have the Flashtool 1.1 (or higher) version, you can use the SM38400.BAT batch file to burn the 38400 Bd monitor debugger and SM9600.BAT file to burn the 9600 Bd version. These batch files are in the installation directory of the PE. You can also download the FLASHTOOL.ZIP package from the PE web site – this package contains the latest update of Flashtool and includes also these batch files.
HOW TO BURN THE PE DEBUG KERNEL
The current version of the PE Debug kernel is provided in two variants, that differs in the location of its variables: the first (PEdebugKernel_IR_xxx.abi, where xxx is the CPU type) uses internal RAM, so it is suitable for user applications, that require maximum free space in the external memory. The second (PEdebugKernel_ER_xxx.abi, where xxx is the CPU type) uses external RAM and it is applicable in cases, when user wants to debug application, that uses the internal RAM. Because the debugging in internal RAM does not allow using the FPGA breakpoint logic, some features of the PE debugger will not work (e.g., „Break on access“ function in the Watches window). Therefore, in most cases we recommend to place all the user variables and program to the external memory, and use the first (internal RAM) variant of the PE debug kernel.
To burn the PE debug kernel to the Devkit16 external FLASH, follow these steps:
1. From the PE environment:
For the internal RAM variant:
From the Tools menu, choose the item „Burn PE Debug Kernel into Devkit16 Ext. FLASH (ver:IR) “.
For the External RAM variant::
From the Tools menu, choose the item „Burn PE Debug Kernel into Devkit16 Ext. FLASH (ver:ER) “.
2. Without PE
Without PE, the debug kernel must be burned using command line:
• change the current directory to the Processor Expert installation directory (for example, c:\Program Files\PE)
33 • run the following command: flashtool -cfg Config\FlashTool\FujitsuDevKit16\PEdebugKernel_IR.ftc for the internal RAM variant or flashtool -cfg Config\FlashTool\FujitsuDevKit16\PEdebugKernel_ER.ftc for the external RAM variant.
Note: From the Flashtool 1.1 (or higher) version, you can use the PEDBG_IR.BAT batch file to burn the debug kernel with internal RAM variables and PEDBG_ER.BAT file to burn the external RAM version. These batch files are in the installation directory of the PE. You can also download the latest FLASHTOOL.ZIP package from the PE web site, which includes also these batch files.
HOW TO BURN THE CPU FLASH WITHOUT DEVKIT16
The Flashtool also allows burning the CPU internal FLASH without the need for using the Devkit16 Mainboard. This is important in the moment when you have an application board of your own and you want to verify if the application you have written is working well on your board.
The application board must have a serial RS-232 interface connected to the CPU UART interface dedicated to the communication in the serial asynchronous mode. Refer to the following table to find out, which CPU uses which UART for this purpose:
CPU type UART used MB90F497 UART1 MB90F543 UART1 MB90F549 UART1 MB90F553 UART0 MB90F562 UART1 MB90F574 UART0 MB90F583 UART0 MB90F591 UART0 MB90F594 UART0 MB90F598 UART1 Note: In the Flashtool 1.2, only the F543 and F497 CPUs are supported
The user application board also must have a mode logic, which would allow to set the state of MD0–2 and P00, P01 CPU pins.
For burning the CPU internal FLASH, you should do the following steps:
• connect your application board RS-232 serial interface to the PC
• set the asynchronous serial programming mode (MD0–2 = „011“ and P00–01 = „00“)
34 • In the Flashtool, set the „External bus free ?“ radio button to „No“. This will set the internal FLASH programming mode using the UART1 interface (instead the FPGA User UART, which is used when „External bus free=Yes).
• Now, follow the steps described in the „How to burn user program into the FLASH” section of this chapter.
RUNNING BURNED PROGRAM
After successful comparing abs file with datas in the FLASH (button Read & compare) or after successful Auto-writing abs file (button Auto) you can run your program in two ways:
1. Manual – set the DIP switches to right values (it depends on choosed mode internal FLASH, external FLASH, mixed mode and 8/16 bit external bus). FlashTool will display their values.
2. Automatic – You may let the FlashTool to reset the mainboard in the right mode without changing switches.
3. How does the FlashTool know the right mode? This information about the mode is stored in the abs file (exactly: in the vector table).
FLASHTOOL COMMANDS - PARAMETERS
FlashTool.exe [-move
1. move – data which are placed in segment "from" will be placed into the segment "to". The "from", "to" are hexadecimal numbers ( 00-FF )
2. cfg – automatically writes program compiled in Processor Expert. File "filename" is created by Processor Expert and contains all information, which are necessary for burning program into the FLASH.
NOTES
For more details about:
DevKit16 memory, I/O mapping and simulated ports see the chapter “Mainboard Programmer’s Reference”
CPU modes and hardwired vector in external FLASH see the CPU documentation.
For project settings concerning the segmentation, see Softune compiler and linker and manuals for segmentation description.
35 ERROR MESSAGES:
Cannot open configuration file Flash.cfg – when the Flash Tool starts, it needs the Flash.cfg configuration file. The full path of the missing file is displayed. Check if you have correctly installed the Flash Tool. Note: this file has nothing to do with the "-cfg" command line switch !
Cannot load file "config\FlashTool\KernelBoot.abi" from disk! – the kernel which is downloaded into the target system is not found. Check if you have correctly installed the Flash Tool.
For mixed mode the internal Flash and the external Flash cannot be in the same address range - Overlap of CPU and external FLASH is not allowed combination, because is not clear which memory should be programmed.
Warning! Code outside of selected FLASH range – the user code is linked to adressess which are outside of the selected FLASH, this code cannot be burned. Set the right FLASH or recompile program to correct addresses.
The abs file has been compiled for ‚internal FLASH‘– the user code is prepared for running in internal FLASH, but different mode is selected. Set the right mode.
The abs file has been compiled for ‚external FLASH‘– the user code is prepared for running in external FLASH, but different mode is selected. Set the right mode.
The abs file has been compiled for ‚mixed mode‘ – the user code is prepared for running in mixed mode (internal and external FLASH), but but different mode is selected. Set the right mode.
Error in communication - disconnected cable, COM port occupied by another program, etc.
MCU busy - the DevKit16 is busy and cannot download kernel into the RAM.
Command error - the BI-Rom doesn‘t support downloading into the RAM
Writing error - error while writing
Time out - the DevKit16 BI-ROM is not responding
Bad checksum - bad checksum of data – the communication cable is possible damaged or unstable
Unknown error - unexpected error during communication
36 Error in communication - disconnected cable, COM port occupied by another program, etc.
Debug already inited - internal error – the last communication wasn‘t closed correctly. Try to restart DevKit16 programming tool
Not supported - not supported command – possible old version of kernel.
No answer from kernel - kernel is not responding – try repeat programing cycle again
Time out - kernel is not responding – restart the mainboard
Unknown error - unexpected error during communication
PROCESSOR EXPERT BEANS INTFLASH AND EXTFLASH – RUNTIME SUPPORT OF FLASH ACCESS AND DESIGN TIME CHECKS
These beans from Processor Expert(TM) accomplish the tasks with programming of runtime write operations for FLASH. Please see more in Processor Expert(TM) Online Help and provided examples in PE.
37 Chapter 7
CPU board for MB90F543 description
This chapter provides detailed description of CPU board for MB90F543 including all DIP switches, jumpers and connectors. For other CPU board types, please see the documentation supplied with them.
CPU board can work standalone or in connection with the Main board. If the Main board is in use, please switch all switches on CPU board configuration DIP to OFF.
CPU BOARD OVERVIEW
CPU personality board is designed as low cost board, which provides compatibility on Interface Bus and the Device Bus level for different CPUs. Additionally headers pin compatible to CPU pins are provided.
• connectors for all CPU pins
• a Bus Interface connector for main board connection
• a Device Bus connector
• a power supply supervisor IC with reset generation
• RST, HST buttons
• CPU configuration switch
• High speed (in socket) and low speed quartzes
• support of CPU Serial FLASH Programming
• power supply regulators 5V or 3.3V, depending on CPU used
38 • power supply connector for external power source
Hi-speed crystal Device Bus
Low-speed crystal GND RST & HST
DC power supply CPU Pins
CPU serial interface
Jumpers
DIP switches VCC
Interface Bus
This part contains description of CPU board for MB90F543CPU.
• Connectors
• Jumpers, buttons and switches
• Board layout
CONNECTORS
K1: Bus Interface connector This connector serves for connecting the CPU board to the Main board connection.
Note: For the pinout of this connector, please see the attachments section of this manual.
K2: Device Bus connector This connector provides connection CPU peripherals.
39 K7: CPU Serial interface connector
AD00 1 2 AD01 MD0 3 4 MD2 SERRES 5 6 SIN SOT 7 8 SCK VCC 9 10 GND
The serial interface connector should be used only when the CPU board is not connected to the mainboard, because mainboard connects its own serial (RS232) interface to the UART0 or UART1 CPU signals. To be able to use the K7 connector, please refer to the description of J7, J8, J9 jumpers later in this section.
Warning: if you want to use the K7 connector when Mainboard is connected to the CPU board, you have to disconnect the serial interface selected by J7-9 from the RS232 drivers on the Mainboard. To achieve this, remove jumpers on positions 3-4, 5-6 from both the J21 and J22 headers on the Mainboard. Also, when the Async. Serial programming mode is set on the Mainboard System control DIP switches, the FPGA UART RS232 driver is connected to UART0 or UART1 (depending on the setting of the UART0/1 switch) after reset. If you want to use K7 also in that case, remove the 3-4, 5-6 jumpers on the J23 as well.
K9: power supply connector GND +9V
Before applying the power to the Devkit16, check the polarity of your power chord plug – the GND must be in the center, while the +9V on the shell of the connector. Even thought the DevKit16 power lines are protected by a diode on the power input, do not ever apply power with the opposite polarity. Also, make sure that the power supply complies to the specifications in chapter CPU Board Power Supply Requirements.
40 K3, K4, K5, K6: CPU pins connectors
K3 K4
A16 1 2 A17 INT6 31 32 INT7 A18 3 4 A19 ADTG 33 34 AVCC A20 5 6 A21 AVR+ 35 36 AVR- A22 7 8 A23 AVss 37 38 AN0 ALE 9 10 #RD AN1 39 40 AN2 GND 11 12 #WRL AN3 41 42 Vss #WRH 13 14 HRQ AN4 43 44 AN5 #HAK 15 16 RDY AN6 45 46 AN7 CLK 17 18 SOT0 TIN0 47 48 TOT0 SCK0 19 20 SIN0 MD0 49 50 MD1 SIN1 21 22 SCK1 FVCC 23 24 SOT1 SOT2 25 26 SCK2 SOT2 25 26 SIN2 INT4 25 26 INT5
K5 K6
VSS 81 82 X0 MD2 51 52 #HST X1 83 84 VCC IN0 53 54 IN1 AD00 85 86 AD01 IN2 54 56 IN3 AD02 87 88 AD03 IN4 57 58 IN5 AD04 89 90 AD05 OUT2/IN6 59 60 OUT3/IN7 AD06 91 92 AD07 PPG0 61 62 PPG1 AD08 93 94 AD09 PPG2 63 64 PPG3 AD10 95 96 AD11 OUT0 65 66 OUT1 AD12 97 98 AD13 TIN1 67 68 TOT1 AD14 99 100 AD15 INT0 69 70 INT1 INT2 71 72 INT3 TX0 73 74 RX0 TX1 75 76 RX1 RST 77 78 PA0 X1A 79 80 X0A
J10: VCC connector
1: VCC 2: VCC 3: VCC
41 J11: GND connector
1: GND 2: GND 3: GND 4: GND 5: GND 6: GND
JUMPERS, BUTTONS AND SWITCHES
J13: Supply for the whole board When SHORT, the +5V from the voltage regulator is connected to board VCC. This jumper must be removed when using an external +5V power supply to avoid current flowing back to the regulator.
J2: Supply for CPU When SHORT, the VCC is connected to CPU’s VCC pins. Before removing this jumper, remove the J3 (AVCC to CPU) jumper as well to completely disconnect the power from the CPU.
J3: Analog Supply for CPU When SHORT, board’s VCC is connected to CPU’s AVcc pin.
J4: Analog Ground for CPU When SHORT, board’s GND is connected to CPU’s AGND pin.
J5: Analog Reference Voltage (+) for CPU When SHORT, board’s VCC is connected to CPU’s AVR+ pin. When removed, the voltage at the AVR+ pin is set to 4V
J6: Analog Reference Voltage (-) for CPU When SHORT, board’s GND is connected to CPU’s AVR- pin. When removed, the voltage at the AVR- pin is set to 0.9V.
J7, J8, J9: UART0/1 selection for the K7 connector These jumpers select, which of the two UART0, UART1 interfaces’ signals will be connected to the pins of the K7 connector. If all of these jumpers are in
1-2 position - the UART1 interface signals will be connected to the K7
2-3 position – the UART0 interface signals will be connected to the K7 connector.
Note: The J7 jumper selects between SCK1 and SCK0, J8 between SIN1 and SIN0 and J9 between SOT1 and SOT0
42 Warning: if you want to use the K7 connector when Mainboard is connected to the CPU board, you have to disconnect the selected serial interface (UART0 or UART1) from the RS232 drivers on the Mainboard. To achieve this, remove jumpers on positions 3-4, 5-6 from both the J21 and J22 headers on the Mainboard. Also, when the Mainboard is connected to the CPU board and the Async. Serial programming mode is set on the Mainboard System control DIP switches, the FPGA UART is connected to UART0 or UART1 (depending on the setting of the UART0/1 switch) after reset. If you want to use K7 also in that case, remove the 3-4, 5-6 jumpers on the J23.
Default setting: the UART1 signals are connected to the K7.
J19, J20: I2C software emulation jumpers These jumpers allow to use Mainboard’s I2C connector/EEPROM memory even in the case, when CPU itself doesn’t provide the I2C interface. When both of these jumpers are SHORT, the CPU’s HRQ signal is connected to the Mainboard’s SDA signal (via J19) and #HAK signal is connected to SCL signal. An user can then program the #HAK, HRQ signals to behave as I2C interface.
J15, J16: Low speed XTAL jumpers When short, these jumpers connect the 32.768 kHz crystal to the Bus Interface connector X1A, X0A pins.
J17, J18: High speed XTAL jumpers When short, these jumpers connect the 4MHz crystal to the Bus Interface connector X0, X1 pins.
SW1 – Reset button This button can be used for reseting the CPU.
SW2 – Hardware standby button While this button is pressed, the CPU stays in the standby mode (all oscillators are stopped, all I/O pins are set to high impedance state, special purpose registers such as the accumulator are reset to their default values, but content of internal RAM is preserved)
SW3 – CPU DIP switches
1: MD0 2: MD1 3: MD2 8 7 6 5 4 3 2 1 4: S-R 5: S-H 6: H-R ON 7: AD00 (P00) 8: AD01 (P01)
43 These switches should be used only when using the CPU board without Mainboard, or with the FPGA disabled (see the description of J29 in the Mainboard section).
1:MD0, 2:MD1, 3:MD2 – these switches are connected to CPU pins MD0, MD1, MD2. In the ON position, a switch pulls the signal connected to it to log ‘0’. The setting of these switches affects the mode of the processor. The description of all the modes is in the following table:
MD2 MD1 MD0 AD00 AD01 Mode name Reset vector Ext. bus /P00 /P01 area witdth ON ON ON OFF OFF External vector mode 0 External 8 ON ON OFF OFF OFF External vector mode 1 External 16 ON OFF ON OFF OFF External vector mode 2 External 16 ON OFF OFF OFF OFF Internal vector mode Internal (Mode data) OFF ON ON X X Reserved OFF ON OFF X X Reserved OFF OFF ON ON ON Async serial programming OFF OFF OFF X X Reserved
4: S-R – if ON, this switch connects the RES pin of the K7 connector to the CPU’s #RST signal.
5: S-H – if ON, this switch connects the RES pin of the K7 connector to the CPU’s #HST signal.
6. H-R – if ON, the #RST and #HST signals are connected together.
7: AD00, 8:AD01 – if ON, the AD00/P00 and AD01/P01 signals are pulled to log. ‘0’ level. This setting must be done for bringing processor to the Serial programming mode.
44 8 7 6 5 4 3 2 1
ON
Figure 1: CPU board layout and default jumper settings
DEFAULT JUMPER SETTINGS
These jumpers come in the SHORT position as a default factory setting:
J2: The CPU is connected to the +5V power supply through this jumper J3: The CPU AVCC supply pin is connected +5V power supply through this jumper J4: The CPU AGND supply pin is connected to the GND through this jumper J5: The CPU AVR+ pin is connected to the +5V voltage through this jumper J6: The CPU AVR- pin is connected to the 0V voltage through this jumper J7-9: The CPU UART1 signals are connected to the K7 connector J13: The board is powered from the +5V from the power supply voltage regulator J19: The CPU HRQ pin is connected to the SDA Mainboard signal J20: The CPU #HAK pin is connected to the SCL Mainboard signal
45 Chapter 8
Main board description
MAIN BOARD OVERVIEW
The Mainboard contains these features:
• 512K of additional RAM with 16bit access, 0 wait
• 128K of additional FLASH with configurable 8/16 bit access, 0 wait
• System Control DIP switch for manual operation
• programmable configurations of external memory organization with support of
1. boot from FLASH or RAM
2. small model with mirror of bank FF to bank 0 for area 4000H- 0FFFFH
• additional four ports to be used instead of CPU's P0, P1, P2, P3 in order to support CPU single chip mode debugging using external bus mode of CPU
• three RS232 interfaces, 2 dedicated for CPU, one for Main board UART (DB9)
• two high-speed CAN drivers and connectors (DB9)
• CAN and RS232 drivers can be replaced by user ones
• serial EEPROM 1kx8 (24C08 type)
• 2 digit LED display with buffer
• UART with 16550 “mimic” and RTS/CTS hardware handshake
• additional I2C is provided for software creation support and EEPROM control
46 • PC-AT keyboard interface with connector
• Amplifier and speaker for sound generation using CPU periph. - sound generator or PPG
• 8 test LEDs as in CAN100 board, custom FPGA status LED
• LED for indication of RESET from RS232
• user key
• a header for CPU A/D converter including AD trigger, references, power supply
• prototype header for prototype boards with user chip selects
• amplifier and speaker
• USB connector (not mounted by default)
• Simulated CPU ports header
• Custom IC (FPGA) User Programmable Pins connector
• Automatic serial interface change from User UART to CPU UARTx when CPU FLASH programming mode is entered
CAN1 Sim. CPU ports User Prototype connector
UART1
User Interface UART bus
UART0
FPGA pins A/D connector Keyboard CAN1
47 MEMORIES
• There are four 128kx8 SRAM memory chips mounted on the board by default, which makes 512kB in total. Optionally, 512kx8 SRAM memory chips can be mounted on the board to extend the SRAM memory amount to 2MB.
• The MB29F008 FLASH memory provides 256kx8 or 128kx16 bits of permanent memory. The selection between 8 and 16 bit access is done by the FL8/16 DIP switch on the mainboard.
For the memory maps in selected CPU modes, see the “Mainboard Programmer’s Reference” chapter.
FPGA
FPGA integrates the biggest portion of the Mainboard functionality. It is a user programmable HW chip, which can be reprogrammed unlimited number of times. In fact, it is reprogrammed each time the power is applied to the board or the Mainboard reset button is pressed. To change the FPGA configuration, the IC9 FPGA EEPROM must be reprogrammed. This can be done by the FPGA EEPROM programming tool.
For details about FPGA registers, see the “Mainboard Programmer’s Reference” chapter.
CAN INTERFACES
There are two CAN interfaces – CAN0 and CAN1. The 82C250 chips are used to interface the CPU CAN0 and CAN1 signals to a CAN network.
The P3, P4 potentiometers are used to control rise and fall slope of the CANH, CANL signals and the standby mode of the 82C250 chip. To set the high-speed mode of the 82C250 interface, set the P3 (P4) potentiometer to the rightmost position (if you don’t know the current position, just turn it 20-times clockwise). To set the standby mode, set the potentiometer to the leftmost position. Setting in between the 0.3-0.75 range of the potentiometer scale will set the value of slope-limiting.
The default setting for the P3, P4 potentiometers is the rigtmost position (high- speed mode).
UART INTERFACES
There are three UART interfaces provided on the Mainboard – two for the UART0, UART1 CPU signals and one for the User (FPGA) UART. The UART0&1 interfaces do not support neither CTS/RTS, neither the DTR, DSR signals. The User UART support RTS/CTS signals for the hardware flow control. This allows communication on the highest possible baud rates.
48 For detailed description of the configuration jumpers, connectors and FPGA User UART registers, see the next chapters.
LED DIODES
There are 11 LED diodes on the Mainboard: 8 of them are connected to the P4 CPU port in the same way as LEDs on the Fujitsu CAN100 board. These diodes can be disconnected from the port by removing the R1 resistor array from its socket. The following table shows which CPU signal is assigned to certain diode:
Diode Signal name CPU Port D7 SCK2 P47 D6 SOT2 P46 D5 SOT1 P45 D4 SCK1 P44 D3 SIN1 P43 D2 SIN0 P42 D1 SCK0 P41 D0 SOT0 P40
The other diodes are:
FGPA status LED (D9) – this diode indicates the status of the FPGA after reset. If the CPU mode pins MD0-MD2 are left high during the reset so the FPGA can set the CPU mode required by user, the LED is shining without blinking. However, if the MD0-MD2 pins are pulled low (by DIP switches on the CPU board, for example), the LED is blinking with approximately 1s period.
Serial line reset LEDs (D10, D11) – if the serial line reset function is enabled by appropriate jumpers (see the “Serial line reset jumpers” description in this chapter) and the reset is activated by serial line, the LED will shine. The D10 diode is connected to the UART0&1 serial line reset, the D11 is connected to the USER UART.
AUDIO AMPLIFIER AND SPEAKER
As an audio amplifier, the LM386 low voltage audio power amplifier is used. This audio amplifier can be connected to the piezoelectric buzzer KPB1220, that is mounted on the board (on the SP1 position) by the J17 jumper, or to an external speaker or audio amplifier by the K16 connector (for details, see the “Connectors” section of this chapter). The audio amplifier chip was used to ensure good sound quality when using a CPU with a built-in sound generator. The volume of the generated sound can be regulated by the P1 potentiometer.
Warning: ensure that the maximum output power of the LM386 chip (300mW with 8Ω load) will not be exceeded with an external speaker.
49 CONNECTORS
The board provides many connectors for interfacing to an user hardware or standard devices like PC keyboard, RS232 communication line or CAN network. The connectors “Prototype connector”, “Simulated CPU ports”, “A/D connector” and “FPGA User Programmable Pins” are positioned in a way that makes the design of an user prototype board easy – the connectors are supposed to be placed on the outline of the prototype board and are in the 2.54 mm grid.
K15-Prototype connector This connector allows the user to connect his prototype board to the AD bus of the MB90F543 processor. The description of the pins follows:
VCC 1 2 GND CSU1 3 4 CSU2 INT5 5 6 INT4 #CSU0 7 8 #WRL #RD 9 10 ALE A00 11 12 A01 A02 13 14 A03 A04 15 16 A05 A06 17 18 A07 AD07 19 20 AD06 AD05 21 22 AD04 AD03 23 24 AD02 AD01 25 26 AD00
K10-Simulated CPU ports These two connectors contain the simulated CPU ports P0-P3.
SP0 0 1 2 SP0 1 SP2 0 1 2 SP2 1 SP0 2 3 4 SP0 3 SP2 2 3 4 SP2 3 SP0 4 5 6 SP0 5 SP2 4 5 6 SP2 5 SP0 6 7 8 SP0 7 SP2 6 7 8 SP2 7 SP1 0 9 10 SP1 1 SP3 0 9 10 SP3 1 SP1 2 11 12 SP1 3 SP3 2 11 12 SP3 3 SP1 4 13 14 SP1 5 SP3 4 13 14 SP3 5 SP1 7 15 16 SP1 6 SP3 7 15 16 SP3 6
50 K8-A/D connector This connector provides an access to the A/D port signals of the CPU:
AVCC 1 2 AVCC AGND 3 4 AGND AVR+ 5 6 AVR+ ADTG 7 8 AVR- AN0 9 10 AN1 AN2 11 12 AN3 AN4 13 14 AN5 AN6 15 16 AN7
K11-FPGA User Programmable Pins This connector allows an user to access the Xilinx user programmable input/output pins. Its pinout is shown on the next figure:
UP0 1 2 UP1 UP2 3 4 UP3- UP4 5 6 UP5 UP6 7 8 UP7 UP8 9 10 UP9 UP10 11 12 UP11 UP12 13 14 UP13 UP14 15 16 UP15 UP16 17 18 UP17 UP18 19 20 UP19 VCC 21 22 GND UP20 23 24 UP21 UP22 25 26 UP23 UP24 27 28 UP25 UP26 29 30 UP27 UP28 31 32 UP29 UP30 33 34 UP31 UP32 35 36 UP33 UP34 37 38 UP35 UP36 39 40 UP37
51 K2, K3-CAN connectors These connectors are of the “Canon 9 male” type. The pinout is following:
Pin 2: CANL Pin 7: CANH
Note: All the other pins are left unconnected.
K5, K6, K7-RS232 interfaces These connectors are of the “Canon 9 female” type. The pinout is following:
1: NC 2: RX 3: TX 4: DTR (Reset) 5: GND 6: DSR 7: RTS 8: CTS 9: NC
K17-PC/AT keyboard connector This connector is of the “DIN-5” type:
1: CLOCK 2: DATA 3: NC 4: GND 5: VCC
K19-USB connector The type of the USB connector is “B series”. This allows connecting the board to a PC computer using a standard USB cable. 2 1 1: VBUS 2: D- 3: D+ 3 4 4: GND 5: SHLD
Note: None of the USB interface parts are mounted on the board by default.
52 K14-I2C connector The type of this connector is “Header 4x1”. The pinout is following:
1: VCC 2: SDA 3: SCL 4: GND
K12-FPGA JTAG port This connector allows testing of FPGA and its user-created configuration. User can use Xilinx standard cables for this purpose.
K13-FPGA programming connector This connector allows reprogramming the FPGA with an user-created configuration. User can use Xilinx standard cable for this purpose. For description of how to do that, see the chapter “FPGA programming”
K16-Audio Out connector
GND AUD
This connector allows connecting an external speaker.
SWITCHES
System control DIP switches
These switches are used for choosing the initial mode of the CPU after the “hard” reset (caused by power-on or the Main board reset button).
1: UMD0 2: UMD1 ON 3: UMD2 4: FLASH8/16
5: ADR/IO 1 2 3 4 5 6 7 8 6: SWAP 7: UART0/1 8: UKEY
1:UMD0, 2:UMD1, 3:UMD2 - The setting of these switches affects the mode of the processor after reset – when the Mainboard’s reset button is pushed or power applied to the board, the state of these switches is copied to the MD0- MD2 pins of the CPU. When a switch is ON, the appropriate signal will be pulled to log. ‘0’. The description of the modes is in the following table:
53 UMD2 UMD1 UMD0 Mode name Reset vector area External data bus witdth ON ON ON External vector mode 0 External 8 ON ON OFF External vector mode 1 External 16 ON OFF ON External vector mode 2 External 16 ON OFF OFF Internal vector mode Internal (Mode data) OFF ON ON Reserved OFF ON OFF Reserved OFF OFF ON Async serial programming OFF OFF OFF Reserved *When FPGA detects this setting, it sets the logic levels on the CPU port P0 in the way that P00 and P01 pins of the CPU are pulled to ‘0’. This invokes the asynchronous serial programming mode of the CPU. 4:FLASH8/16 - If this switch is ON, the external FLASH memory interface is configured to 16 bit mode.
5:ADR/IO - If this switch is ON, the A16-A23 CPU pins can be switched to general I/O mode. Any memory access above the 00FFFFh address is mirrored to the 4000h-FFFFh area. The decode logic (FPGA) ignores the A16-A23 address signals and the MirrorFF bit setting. This switch allows to use the port P2 (A16-A23 signals) as general I/O without giving up the external RAM/FLASH memory. It can be useful for developing mixed mode applications with only one 64k external RAM memory bank, that need more I/O pins than the CPU would provide with all the external bus pins used.
Note: This is not mirroring function similar to CPU one. To control Mirror please see The Main board Programmers reference bit MirrorFF in System Configuration Register.
54 6:SWAP - When this switch is OFF, the external FLASH memory is mapped to the UMB and the SRAM is mapped the LMB. If the switch is ON, these memory areas are swapped.
7:UART0/1 - In the Async Serial Programming mode if the switch is ON, the serial communication goes to the UART1 port of the CPU. If the switch is OFF, it goes to the UART0. Note, that serial cable is still connected to the User UART interface connector, so that the user doesn’t have to change its position.
8:USW - The state of this switch (OR-ed with the state of UKEY), can be read in the SCDS register (address C0H). Both Fujitsu debug monitor and PE debug kernel use this switch to find out whether to run the user program or not after reset.
When this switch is ON after the reset, the kernel runs the user program (if there is any). When it is OFF, the kernel waits for communication with PC.
After the user program is run, the user can use the USW switch (and/or User Key button) as one of his program’s input.
Note: for compatibility reasons, the User key state and the User switch state are logically OR-ed to form the value of the USW bit in the SCDS register (address C0H). Therefore during the reset, holding the User key will have the same effect as switching the USW to ON (though, this OR-ing will not be supported in the future, so the USW and UKEY will be totally independent). The state of the User Key can be still independently read from the Hardware Status Register (address C0H).
Factory default setting: See the figure above: the setting 2 (UMD1) = ON, 3 (UMD2)=ON, 4(FLASH8/16)=ON means that the CPU will start in the ‘External vector mode 1’ and the external FLASH memory interface is configured to 16 bits mode. The memory model is standard, with external FLASH in the UMB and SRAM in LMB.
Reset button: This button resets the whole system – CPU and FPGA, so it should be used as a “hard” reset. To reset the CPU only, please use the reset button on the CPU board.
JUMPERS
J9: User UART RTS-CTS loopback UART jumpers: In the 1-2 position, this jumper makes the RTS-CTS loopback on the FPGA RS232 interface.
In the 2-3 position, it connects the RTS signal to the User UART and thus allows the hardware flow control to work properly.
55 J7: UART0 RTS-CTS loopback
When SHORT, this jumper makes the RTS-CTS loopback on the UART0 RS- 232 interface.
J8: UART1 RTS-CTS loopback
When SHORT, this jumper makes the RTS-CTS loopback on the UART1 RS- 232 interface
J21, J22, J23: UARTs to RS232 drivers connection jumpers
These jumper headers are intended to provide access to the UART0, UART1 and User UART signals. An user can disconnect these signals from the RS-232 interfaces and connect an serial interface of his own to these signals – e.g. a MIDI interface.
J21 pinout: GND 1 2 GND SOT0 3 4 to RS2320 input for RX0 SIN0 5 6 from RS2320 output for TX0 To UART0&1 reset 8 from RS2320 output for DTR0 VCC 9 10 VCC
Factory default setting: 3-4 short, 5-6 short
The GND and VCC signals are provided as supply pins for the user-built serial interface.
J22 pinout:
GND 1 2 GND SOT1 3 4 to RS2321 input for RX1 SIN1 5 6 from RS2321 output for TX1 NC 7 8 NC VCC 9 10 VCC
Factory default setting: 3-4 short, 5-6 short
The GND and VCC signals are provided as supply pins for the user-built serial interface.
56 J23 pinout: GND 1 2 GND SOTU 3 4 to RS232F input SINU 5 6 from RS232F output To User UART reset 8 from RS232F output for VCC 9 10 VCC RTSU 11 12 from RS232F output CTSU 13 14 from RS232F output NC 15 16 NC
Factory default setting: 3-4 short, 5-6 short, 11-12 short, 13-14 short
Note: jumper names are valid for the Main board version 1.3. If your motherboard version is different form that one, please download a new version of this document
Serial line reset The Serial line reset function is used by both the PE and Softune debugger. Its jumpers: purpose is to allow reseting the board through the debugger communication interface. The Serial line reset function is provided on all the three RS232 interfaces – UART0, UART1 and User UART (DTR lines of these interfaces are dedicated to this function). However, it is possible to use only two of these ports concurrently: the User UART and one of the UART0 or UART1. For each of these two ports, the reset polarity of the DTR line can be choosen.
UART 0&1 serial J5: Port selection (UART 0-1) for the Serial line reset line reset jumpers: In 1-2 position, the DTR0 line of the UART0 RS-232 interface is connected to the J21, pin 8.
In 2-3 position, the DTR1 line of the UART1 RS-232 interface is connected to the J21, pin 8.
Note: the selected DTRx line is connected to the UART reset logic only if there is a jumper in the 7-8 position on the J21 header.
J2: UART0&1 Serial line reset - polarity selection In the 1-2 position, the “1” level on the selected DTRx line will cause the CPU reset,
In the 2-3 position, the “0” level on the selected DTRx line will cause the CPU reset.
57 Note: If the reset condition set by these jumpers is met, the D10 LED diode will shine and the CPU will be reset.
User UART serial J1: User UART Serial line reset - polarity selection line reset jumpers: In the 1-2 position, the “1” level on the DTRF line will cause the CPU reset.
In the 2-3 position, the “0” level on the DTRF line will cause the CPU reset.
If the reset condition set by this jumper is met, the D11 LED diode will shine and the CPU will be reset.
Note: The User UART DTRF line is connected to the User UART reset logic only if there is a jumper in the 7-8 position on the J23 header.
2 2 I2C interface The J14, J15 jumpers select one of the two available I C interfaces –CPU’s I C jumpers: or FPGA’s one. This way, the selected interface is connected to serial EEPROM and I2C connector as well.
J14: SCL source selection In the 1-2 position, the FPGA I2C interface is selected as the source for the SCL signal.
In 2-3 position, the CPU’s I2C interface is selected.
J15: SDA source selection In the 1-2 position, the FPGA I2C interface is selected as the source for the SDA signal.
In 2-3 position, the CPU’s I2C interface is selected.
J13: WP setting If short, this jumper pulls down the WP (write protect) pin of the serial EEPROM.
Note: For the description of the Write protect feature, see the EEPROM datasheet.
Audio amplifier J38: Audio signal source selection jumpers: In the 1-2 position, the PPG0 pin of the CPU is selected as input for the audioamplifier.
In the 2-3 position, the SGO pin of the CPU is selected.
Note: the MB90F543 CPU does not have the SGO (sound generator output) pin.
58 J17: Speaker connection jumper
If short, the amplifier output is connected to the built-in speaker.
CAN interface J26: RX0 to INT4 connection jumpers: When short, the RX0 line of the CAN0 interface is connected to the INT4. This allows the programmer to use the “wake-up” mode of the CPU CAN interface.
J27: RX1 to INT5 connection
When short, the RX1 line of the CAN1 interface is connected to the INT5. This allows the programmer to use the “wake-up” mode of the CPU CAN interface.
J28: RX0, RX1 to INT4 connection
When short, the logical OR of the RX0 and RX1 line of both CAN interfaces is connected to the INT4.
J25, J24: CPU CAN signals to CAN drivers connection jumpers
These jumper headers are intended to provide access to CPU’s CAN0 and CAN1 interface signals. An user can disconnect these signals from the PCA82C250 CAN bus transceivers and connect them to a CAN bus transceiver of his own. The pinout of J25, J24 is following:
J25 pinout: GND 1 2 GND TX0 3 4 to CAN0 RX0 5 6 from CAN0 transiever NC 7 8RxD NC VCC 9 10 VCC
Factory default setting: 3-4 short, 5-6 short
The GND and VCC signals are provided as supply pins for the user-built CAN transceiver.
J24 pinout: GND 1 2 GND TX1 3 4 to CAN1 RX1 5 6 from CAN1 transceiver NC 7 8RxD NC VCC 9 10 VCC
59 Miscellaneous J4: Programming mode(PRMODE) enable jumpers: When REMOVED, the FPGA EEPROM works as an ordinary serial configuration PROM. When SHORT, the FPGA EEPROM is switched to the programming mode. In this mode it can be accessed as an I2C serial memory. The details about the EEPROM programming can be found in the FPGA EEPROM chapter.
J6: FPGA configuration mode (XMODE) When REMOVED, the FPGA is configured by the content of the FPGA configuration serial PROM. When SHORT, the FPGA is configured by a standard parallel port cable.
NOTE: The XMODE signal is connected also to the pin 5 of the FPGA programming connector K13, so when using a special (user made) cable, it is not necessary to use the J6 jumper.
J11: SDA to FPGA EEPROM DIN connection When SHORT, the FPGA EEPROM DIN pin is connected to the SDA signal on the Mainboard.
J12: SCL to FPGA EEPROM CCLK connection When SHORT, the FPGA EEPROM CCLK pin is connected to the SCL signal on the Mainboard.
J29: FPGA enable If this jumper is SHORT, all the FPGA output pins are tristated, so the FPGA is in fact disconnected from the CPU.
NOTE: FPGA registers can be still written.
J10: Monitor Selection Jumper For details on this jumper, see the Hardware Status Register description.
60 ChapterChapter 99
The Mainboard Programmer‘s Reference
This section describes internal registers of the FPGA chip, which provides the biggest portion of the Mainboard functionality. The FPGA is connected to the CPU external bus, so it is necessary to program all the CPU external bus pins (including the CLK and /WRL pins) to the external bus mode with the 8-bit access to the 0C0H-0FFH area. In Processor Expert environment, this is done automatically when using any of the “MB90540 external bus” project templates.
REGISTER ADDRESSES AND CHIP SELECTS
FPGA I/O space is mapped to CPU bank 0 and starts from 0C0H
System Control Registers: 0C0H – 0C8H I2C: 0C9H – 0CFH UART: 0D0H – 0D3H Add-on FPGA output only port: 0D7H Simulated CPU ports: 0D8H – 0DFH Add-on FPGA ports: 0E0H – 0E7H Keyboard Controller: 0EAH, 0EBH FPGA EEPROM : 0EFH WWLED: 0E8H, 0E9H CSUSERIO*: 0F0H – 0FFH *The CSUSERIO signal is generated by the FPGA when accessing this area. It is provided on the Prototype connector.
INTERRUPTS
The interrupts in the following table are used by the Mainboard and should not be used by an user harware:
INT0 Hardware breakpoint, User Key Button INT1 User (FPGA) UART INT2 Keyboard INT3 FPGA I2C
61 SIMULATED CPU PORTS (P0, P1, P2, P3 OF FUJITSU FLASH CPU)
Registers
Base Address: 000000H for CPU native ports, 0000D8H for simulated CPU ports
(1) Port data registers PDR0 7 6 5 4 3 2 1 0 Initial Acces value s
Addr.: D8H P07 P06 P05 P04 P03 P02 P01 P00 00 H R/W
PDR1 15 14 13 12 11 10 9 8 Initial Acces value s
Addr.: D9H P17 P16 P15 P14 P13 P12 P11 P10 00 H R/W
PDR2 7 6 5 4 3 2 1 0 Initial Acces value s
Addr: DA H P27 P26 P25 P24 P23 P22 P21 P20 00 H R/W
PDR3 15 14 13 12 11 10 9 8 Initial Acces value s
Addr:DB H P37 P36 P35 P34 P33 P32 P31 P30 00 H R/W
Note: R/W for I/O ports means the following:
Input mode Read: The level at the corresponding pin is read.
Write: Data is written to an output latch, but not to the pin.
Output mode Read: The level at the corresponding pin is read. In most cases it will be the value written to the pin as last, the only exception can happen when the pin is erroneously pulled hard to VCC or GND.
Write: Data is written to an output latch and output to the corresponding pin.
(2) Port direction registers
DDR0 7 6 5 4 3 2 1 0 Initial Acces value s
Addr.: DC H D07 D06 D05 D04 D03 D02 D01 D00 00 H R/W
DDR1 15 14 13 12 11 10 9 8 Initial Acces value s
Addr.: DD H D17 D16 D15 D14 D13 D12 D11 D10 00 H R/W
DDR2 7 6 5 4 3 2 1 0 Initial Acces value s
Addr.: DE H D27 D26 D25 D24 D23 D22 D21 D20 00 H R/W
62
DDR3 15 14 13 12 11 10 9 8 Initial Acces value s
Addr.: DF H D37 D36 D35 D34 D33 D32 D31 D30 00 H R/W
When reading the register, last value written to it is returned.
Pins are controlled as described below:
0 = Input mode
1 = Output mode
Note: Pull-up resistors 47K are internally connected to port pins.
ADD-ON FPGA PORTS
These ports are provided with FPGA content version 1 and can be found on FPGA User Programmable Pins connector.
Registers
Base Address: 0000E0H
(1) Port data registers PDR4 7 6 5 4 3 2 1 0 Initial Access value
Address:E0H P07 P06 P05 P04 P03 P02 P01 P00 00 H R/W
PDR5 15 14 13 12 11 10 9 8 Initial Access value
Address: E1H P17 P16 P15 P14 P13 P12 P11 P10 00 H R/W
PDR6 7 6 5 4 3 2 1 0 Initial Access value
Address: E2 H P27 P26 P25 P24 P23 P22 P21 P20 00 H R/W
PDR7 15 14 13 12 11 10 9 8 Initial Access value
Address: E3 H P37 P36 P35 P34 P33 P32 P31 P30 00 H R/W
63 ADD-ON FPGA OUTPUT-ONLY PORT
On the remaining 6 FPGA User programmable pins there is an ouput only, 6bit port:
(1) Port data register OPDR 7 6 5 4 3 2 1 0 Initial Access value
Address:D7H EN OP5 OP4 OP3 OP2 OP1 OP0 --- 00 H W
When the “EN” bit is set to “0”, the OP0-5 pins are tristated. When the “EN” bit is set to “1”, the pins work as outputs of the register.
The pinout for add-on ports is following:
P00 1 2 P01 P02 3 4 P03 P04 5 6 P05 P06 7 8 P07 P10 9 10 P11 P12 11 12 P13 P14 13 14 P15 P16 15 16 P17 P20 17 18 P21 P22 19 20 P23 VCC 21 22 GND P24 23 24 P25 P26 25 26 P27 P30 27 28 P31 P32 29 30 P33 P34 31 32 P35 P36 33 34 P37 OP0 35 36 OP1 OP2 37 38 OP3 OP3 39 40 OP5
R/W for I/O ports means the following:
Input mode Read: The level at the corresponding pin is read.
Write: Data is written to an output latch, but not to the pin.
64 Output mode Read: The level at the corresponding pin is read. In most cases it will be the value written to the pin as last, the only exception can happen when the pin is erroneously pulled hard to VCC or GND.
Write: Data is written to an output latch and output to the corresponding pin.
(2) Port direction registers DDR4 7 6 5 4 3 2 1 0 Initial Access value
Address: E4 H D07 D06 D05 D04 D03 D02 D01 D00 00 H W
DDR5 15 14 13 12 11 10 9 8 Initial Access value
Address: E5 H D17 D16 D15 D14 D13 D12 D11 D10 00 H W
DDR6 7 6 5 4 3 2 1 0 Initial Access value
Address:E6H D27 D26 D25 D24 D23 D22 D21 D20 00 H W
DDR7 15 14 13 12 11 10 9 8 Initial Access value
Address:+E7 H D37 D36 D35 D34 D33 D32 D31 D30 00 H W
When reading the register, last value written to it is returned. Pins are controlled as described below: 0: Input mode 1: Output mode
Note: The port direction registers are WRITE ONLY. Pull-up resistors 47K are internally connected to port pins.
USER UART
The User UART has the ”mimic” of a simplified 16550C serial asynchronous UART. The main differences are:
• received and transmitted data are double buffered, not FIFOed in 16 bytes long buffer
• only basic serial stream mode is provided (1 start, 8 data bits, 1 stop bit)
• Send Break and Break Indicate functions supported
• the number of baud rates is limited to 16
• Hardware flow control CTS, RTS signals are used by default
• no DSR, DTR signals
65 Registers Base Address: 0000D0H
(1) Data register
SDAT 7 6 5 4 3 2 1 0
Address: D0 H SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Initial Value (X) (X) (X) (X) (X) (X) (X) (X)
Note: R/W for I/O ports means the following:
Read: The data from the receive buffer is read. Read clears the DR bit in the status register.
Write: Data are written to the transmit buffer.
(2) Line control register
LCR 7 6 5 4 3 2 1 0
Address: D1 H SBRK ETBEI ERBEI ------Read/Write (R/W) (R/W) (R/W) (---) (---) (---) (---) (---) Initial Value (0) (0) (0) (---) (---) (---) (---) (---)
[Bit 7] SBRK: Send Break signal (start bit=0, databits=00H, stop bit=0) is transmitted when this bit is set
[Bit 6] ETBEI: Enable Transmit Buffer Empty Interrupt. If this bit is set, the interrupt INT1 is activated whenever the THRE bit of the LSR register goes high.
[Bit 5] ERBEI: Enable Receive Buffer Full Interrupt. If this bit is set, the interrupt INT1 is activated whenever the DR bit of the LSR register goes high.
Note: When both ETBEI='0' and ERBEI='0', the INT1 pin will stay in high impedance state with a 47k pullup connected to it.
(3) Line status register
LSR 7 6 5 4 3 2 1 0
Address: D2 H TEMT THRE ------BI FE OE DR Read/Write (R) (R) (---) (---) (R) (R) (R) (R) Initial Value (1) (1) (---) (---) (0) (0) (0) (0)
[Bit 7] TEMT: This bit is set when transmit register and transmit shift register are empty. It can be cleared by writing data to the SDAT register.
[Bit 6] THRE: This bit is set when transmit register is empty. It can be cleared by writing data to the SDAT register.
66 [Bit 5] BI: Break Indicate bit is set when a Break Signal was received. It can be cleared by reading the LSR
[Bit 4] FE: Framing error bit is set when stop bit is 0 during normal character (not a Break Signal) reception. Can be cleared by reading the LSR
[Bit 3] OE: Overrun error bit is set when a new character is received but the previous has not been read from the SDAT register yet.
[Bit 2] DR: Data Ready bit is set when there is a new character in the receive buffer.
(4) Baud register
BDR 7 6 5 4 3 2 1 0
Address: D3 H ------BD3 BD2 BD1 BD0 Read/Write (---) (---) (---) (---) (R/W) (R/W) (R/W) (R/W) Initial Value (---) (---) (---) (---) (0) (0) (0) (0)
The BD3-BD0 bits form the Baud Rate divisor BD. The resulting baud rate can be computed as
Baudrate=115200/BD. In the next table you can find the most typical values of BD:
BD Rate 0 disable baud generator 1 115 200 2 57600 3 38400 6 19200 12 9600
I 2 C
The I2C interface is provided for acceleration of operations with the I2C EEPROM memory that is mounted on the Mainboard. Therefore, the interface was simplified to save the FPGA resources, that can be used for user design. The interface implementation is based on the Philips I2C specification ver. 2.0 with these limitations:
Slave mode is not supported
Multi-master mode of operation is not supported
67 (1) Bus status register
IBSR 7 6 5 4 3 2 1 0
Address: C9 H BB ------LRB TRX ------
Read/Write (R) (---) (---) (R) (R) (---) (---) (---) Initial Value (0) (---) (---) (0) (1) (---) (---) (---)
[Bit 7] BB: Bus Busy 0: The Stop condition was transmitted (initial value) 1: The Start condition was transmitted
This bit should be polled when the MS bit of the IBCR register is changed by user.
[Bit 4] LRB: Last Received Bit This bit stores the acknowledge bit (the acknowledge bit is the 9th bit of the data byte).
[Bit 3] TRX: Transmit/Receive This bit indicates data transmitting and receiving. 0: Receive mode - the current (or the next) transfer will be reception of a byte from a slave. 1: Transmit mode [initial value] - the current transfer will be transmission to the slave.
This bit is set when the first byte after a START condition is written to the IDAR register. It contains the state of the LSB bit of the first byte.
(2) Bus control register
IBCR 7 6 5 4 3 2 1 0
Address: CA H ------SCC MTS ACK -- INTE INT
Read/Write (---) (---) (R/W) (R/W) (R/W) (---) (R/W) (R/W) Initial Value (---) (---) (0) (0) (0) (---) (0) (0)
[Bit 5] SCC: Start Condition Continue This bit generates the start condition.
• Write 0: Not applicable [Initial value] 1: The start condition is generated and address data transfer is started. • Read An '1' will be read out of this bit if it was previously written to it, until the start condition is generated. After finishing the Start condition transmission, this bit is reset to '0'.
68 [Bit 4] MS: Master Transfer Start This bit controls I2C data transfer.
0: The stop condition is generated and address data transfer terminated. 1: The start condition is generated and address data transfer started.
[Bit 3] ACK: Acknowledge This bit enables acknowledge generation when data is received.
• Write 0: Acknowledge is not generated. 1: Acknowledge is generated.
[Bit 1] INTE: INTEnable This bit enables the INT3 interrupt generation after a transfer is terminated.
0: the interrupt is disabled (initial value), the INT3 pin stays in the high impedance state with 47k pullup. 1: the interrupt is enabled - when the INT bit goes to '1', the INT3 interrupt is generated
[Bit 0] INT: INTerrupt This is a transfer end interrupt request flag. • Write 0: To clear the flag, write '0' to this bit until reading it will return '0'. In the interrupt handler routine, this must be done prior to any other operation of the I2C interface. Otherwise, the next Transfer End condition will be lost. 1: Not applicable (the flag is set, and if the INTE bit is '1', the INT3 interrupt is generated) • Read 0: The transfer is not terminated 1: This bit is set when an one-byte transfer (including the acknowledge bit) is terminated.
(3) Clock control register
ICCR 7 6 5 4 3 2 1 0
Address: CBH ------CS3 CS2 CS1 CS0
Read/Write (---) (---) (---) (---) (R/W) (R/W) (R/W) (R/W) Initial Value (---) (---) (---) (---) (X) (X) (X) (X)
The value of CS3-CS0 bits of this register form a divider of the base I2C clock - 384 kHz. The resulting SCL clock frequency can be then computed as:
69 fSCL=384 000/CS[3:0]
The actual SCL clock frequency is dependent on the speed of devices that are connected to the I2C bus – see the “Clock synchronization” issue in the Philips’s I2C bus specification.
(4) Data register
IDAR 7 6 5 4 3 2 1 0
Address: CC H D7 D6 D5 D4 D3 D2 D1 D0
Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial Value (X) (X) (X) (X) (X) (X) (X) (X)
This register is used for serial transfer. Data is transferred from MSB. When data is received (TRX=0) the receive shift register is directly read, so receive data is valid only when the INT bit is set. Data for transmitting are written directly to the transmit shift register.
KEYBOARD CONTROLLER
The keyboard controller provides an interface to a standard PC-AT keyboard. When a key is pressed on the keyboard, the controller receives a SCAN code of that key and stores it in the KBDR register. Then it generates the interrupt INT2. The interrupt handling routine should buffer the SCAN codes and decode them.
Base Address: EAH
(1) Keyboard data register KBDR 7 6 5 4 3 2 1 0
Address: EA H D7 D6 D5 D4 D3 D2 D1 D0 Read/Write R R R R R R R R Initial Value (X) (X) (X) (X) (X) (X) (X) (X)
(2) Keyboard control register KBDR 7 6 5 4 3 2 1 0
Address: EB H ------INTE ------Read/Write ------R/W ------Initial Value (---) (---) (---) (0) (---) (---) (---) (---)
[Bit 4] INTE: Keyboard interrupt enable This bit enables a bus error interrupt
0 : Interrupt is disabled - the INT2 pin stays in high impedance state, with a 47k pullup. 1 : Interrupt is enabled – if the INTE bit is 1 and a scan code is received from the keyboard, the INT2 interrupt is generated. occurs
70
LED DISPLAY
Base Address: E8H
(1) LED display data registers The double 7-segment LED display is controlled by two 8-bits wide, write-only registers LEDDR0 and LEDDR1.
LEDDR0 7 6 5 4 3 2 1 0 [7:0]
Address: E8 H 1H 1G 1F 1E 1D 1C 1B 1A Read/Write W W W W W W W W Initial Value (X) (X) (X) (X) (X) (X) (X) (X)
LEDDR1 7 6 5 4 3 2 1 0 [7:0]
Address: E9 H 2H 2G 2F 2E 2D 2C 2B 2A
Read/Write W W W W W W W W Initial Value (X) (X) (X) (X) (X) (X) (X) (X)
If a bit in this register is ‘0’, the corresponding LED display segment is ON. E.g., clearing bit 2 of the LEDDR1 register will switch the segment 2C on.
The segment annotation is standard:
2A 1A
2F 2B 1F 1B 2G 1G 2E 2C 1E 1C
2D 2H 1D 1H
FPGA EEPROM
The FPGA is configured from the AT17C256 serial configuration EEPROM memory everytime the power is applied to the board or the board is restarted by the Mainboard reset button. To modify the content of the FPGA EEPROM, the following steps must be done:
1. On the mainboard, place a jumper to the J4 position. This will set the FPGA EEPROM to the special programming mode. While in this mode, the EEPROM can't be used as a FPGA configuration memory - it behaves as a standard, 256kbit I2C EEPROM memory. Therefore, if the
71 Mainboard reset button is pressed or power is removed and then applied again to the board while J4 is SHORT, the FPGA will not be configured so the Mainboard will not work properly. To return to the standard configuration mode, J4 must be removed.
2. On the CPU board, check the J19, J20. Both of them must be ON. On the mainboard, place two jumpers to the J11, J12 positions. This will connect the I2C SCL, SDA lines to the FPGA EEPROM.
3. Or (instead of the step 2), use the FPGA EEPROM programming register to program the EEPROM.
Warning: Although the EEPROM can't be erased by chance, because the programming mode must be set by the J4 jumper, user is not supposed to access this register. Instead, he/she should use the "FPGA EEPROM programming tool". For availability of the tool, please check the Processor Expert WWW site.
(1) FPGA EEPROM programming register This register is used by the FPGA EEPROM programming tool. Its description here is included only for reference. Please, avoid writing to this register - it can cause erasing of the FPGA EEPROM content and thus non- functionality of the whole board.
FEPR[7:0] 7 6 5 4 3 2 1 0
Address: EF H SDAB SCLK PEN ------B Read/Write R/W R/W R/W ------Initial Value (1) (1) (0) (---) (---) (---) (---) (---)
[Bit 7] SDAB: SDA line data bit • Write 0: FPGA EEPROM SDA line is pulled to '0' 1: The FPGA EEPROM SDA line is released the the 'H' state (managed by a 10k pullup) • Read The state of the SDA line is read out
[Bit 6] SCLB: SCL line data bit • Write0 0: FPGA EEPROM SCL line is pulled to '0' 1: The FPGA EEPROM SCL line is released the the 'H' state (managed by a 10k pullup) • Read The state of the SCL line is read out
[Bit 5] PEN: Programming enable 0: The programming is disabled even with the J4 jumper short. 1: If the J4 jumper is SHORT, the programming is enabled.
72 SYSTEM CONTROL REGISTERS
The system control registers allows to check and control Devkit16 configuration.
(1) System control DIP switches status SCDS[7:0] 7 6 5 4 3 2 1 0
Address: C0H USW UART0/1 SWAP FLASH8/16 Adr/Io UMD2 UMD1 UMD0 Read/Write (R) (R) (R) (R) (R) (R) (R) (R) Initial Value (X) (X) (X) (X) (X) (X) (X) (X)
This register allows to read the current state of mainboard System control DIP switches (SW1).
Writing to this register has no meaning.
(2) System Configuration Register SCR[7:0] 7 6 5 4 3 2 1 0
Address: C1H RESET MirrorFF SWAP FLASH8/16 Adr/Io MD2 MD1 MD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value (0) (1) (X) (X) (X) (X) (X) (X)
The value in this register controls the system configuration.
MD0-MD2: these bits directly control the state of CPU pins MD0- MD2. The initial value of this register is affected by the state of the mainboard System control DIP switches (SW1) – when the power is applied to the mainboard or mainboard Reset button is pressed, the state of UMD0-2, FLASH8/16, SMALL and SWAP switches is copied to it. ADR/IO: When '1', the A16-A23 CPU pins can be switched to general I/O mode. For description of this feature, see the "Mainboard User Reference" chapter. When '0', the A16-A23 pins are expected to behave as address signals. FLASH 8/16: if 1 then 16bit access is selected for main board FLASH
Note: setting of this bit should correspond with the CPU external data bus width configuration of the memory space where the mainboard’s FLASH memory is mapped - see the “Bus control signal selection register” description on page 277 in the “F2MC-16LX Family, 16-Bit Microcontroller MB90540/545 series hardware manual”.
SWAP FLASH/RAM: if 1 then Main board RAM is mapped to upper memory block - UMB, Main board FLASH is in LMB else RAM is LMB and FLASH is UMB. MirrorFF: if 1 then any access to address range 4000H - 0FFFFH is mapped to the FF4000H-FFFFFFH range. The
73 mirror function is analogic to CPU one and is similary default on after reset. When small model is selected, then FPGA decoding logic works as described on The Mainboard User Reference chapter for SMALL. RESET: when a ‘0’ to ‘1’ occurs on this bit, the CPU will be reset (a 100ms pulse will be generated on the #RST CPU pin). This bit is always ‘0’ when being read.
Initial Values description: • after power-on or system reset, the bits 0 - 5 holds values from User Switches Status register • after software reset CPU is set to mode defined by actual values of MD0-MD2 • if MD0-MD2 are set to values defined for CPU Serial programming mode, FPGA sets the logic levels on the CPU port P0 in the way that P00 and P01 pins of the CPU are pulled to ‘0’. This invokes the asynchronous serial programming mode of the CPU.
Note: if the FPGA detects that some of the CPU signals MD0-2, P00,P01 are set to ”0” by CPU board switches during reset time, it holds RST to ”0” and periodically flashes the green LED “FPGA st.” (D9) on the Main board. Please switch all CPU board switches on SW3 to OFF when Main board is used.
74 Memory maps for most frequently used modes:
FFFFFFH Int. FLASH – FF bank FFFFFFH Int. FLASH – FF bank FF0000H FF0000H FEFFFFH Int. FLASH – FE bank FE0000H FEFFFFH Int. FLASH – FE bank FBFFFFH FE0000H
HMB Ext. FLASH 256K F80000H
FPGA res. E00000H 800000H 7FFFFFH 2FFFFFH FPGA res. 180000H 180000H Ext. RAM 512K 100000H 100000H
LMB 00FFFFH FLASH - image of 00FFFFH FLASH - image of 004000H bank FF 004000H bank FF Peripheral Peripheral 003900H 003900H External External 002000H 002000H 0018FFH Int. RAM 6K 0018FFH Int. RAM 6K 000100H 000100H External-FPGA 0000BFH 0000BFH Peripheral Peripheral 000000H 000000H Single chip mode (FPGA disabled) Internal ROM and external bus mode (mixed mode)
FFFFFFH FFFFFFH Ext. FLASH 256K FC0000H Ext. RAM 512K FPGA res. F80000H E00000H FPGA res. E00000H
2FFFFFH FPGA res. FPGA res. 2FFFFFH 180000H Ext. RAM 512K 140000H 100000H Ext. FLASH 256K 100000H
00FFFFH 00FFFFH 004000H 004000H Peripheral Peripheral 003900H External 003900H 002000H External 002000H 0018FFH Int. RAM 6K Int. RAM 6K 0018FFH 000100H 000100H External-FPGA External-FPGA 0000BFH 0000BFH Peripheral Peripheral 000000H 000000H External bus mode External bus mode with SWAP on
75 FFFFFFH Ext. FLASH 256K Ext. RAM 512K FFFFFFH FC0000H FPGA res. F80000H E00000H FPGA res. E00000H
2FFFFFH 2FFFFFH FPGA res. FPGA res. Ext. RAM 512K 180000H 140000H 100000H Ext. FLASH 256K 100000H
00FFFFH FLASH - image of FLASH - image of 00FFFFH FF4000-FFFFFF 004000H FF4000-FFFFFF 004000H Peripheral Peripheral 003900H External 003900H 002000H External 002000H 0018FFH Int. RAM 6K Int. RAM 6K 0018FFH 000100H 000100H External-FPGA External-FPGA 0000BFH 0000BFH Peripheral Peripheral 000000H 000000H
External bus mode with MIRROR on External bus mode with MIRROR on (SWAP off) and SWAP on
The address decoding and memory chip selects generation is done in the FPGA. Since the Devkit16 Mainboard can be delivered with external SRAM memories of 512K or 2M size, the FPGA decodes the address in a way that it reserves a 2M block in both the high memory block (HMB, 800000H-FFFFFFH) and lower memory block (LMB, 010000H-800000H). In the LMB it is the 100000H-2FFFFFH area, in HMB it is E00000-FFFFFF. With the 512K version of the Mainboard, the SRAM memory will therefore be mirrored in these areas four times and the 256K FLASH eight times. For example, accessing address 100000H will do the same as address 180000H, 200000H and 280000H in the SRAM memory (SWAP is off). Also, addresses E00000H, E40000H, E80000H and so on will work the same for the 256K FLASH memory.
This allows using the whole 256K of FLASH (or 512K of SRAM when SWAP is ON) in the mixed mode, when there is the internal FLASH on addresses FC0000H-FFFFFFH - the external memory can be accessed on lower addresses in the 2M block, e.g. E00000H.
The Adr/IO switch allows to use the A16-A23 CPU pins as a general I/O mode pins. If the switch is on, any memory access above the 00FFFFh address is mirrored to the 4000h-FFFFh area. The decode logic (FPGA) ignores the A16- A23 address signals and the MirrorFF bit setting. This switch allows to use the port P2 (A16-A23 signals) as general I/O without giving up the external RAM/FLASH memory. It can be useful for developing mixed mode applications with only one 64k external RAM memory bank, that need more I/O
76 pins than the CPU would provide with all the external bus pins used. The memory map for the Adr/IO switch ON mode is shown on the following figure:
FFFFFFH
Not Available
100000H
Iimage of the area 00FFFFH FF4000-FFFFFF 004000H Peripheral 003900H External 002000H
0018FFH Int. RAM 6K 000100H External-FPGA 0000BFH Peripheral 000000H
External bus mode with Adr/IO on
(5) FPGA content version 76543210
Address:C2H Xilinx content version Read/Write (R)
The FPGA content version can be found in the PE "Help - About" dialog, when the debugger is started.
(6) Mainboard version 76543210
Address:C3H Mainboard version Read/Write (R)
• For the Mainboard v. 1.1, there is 11H in this register.
• For the Mainboard v. 1.2, there is 12H.
• For the Mainboard v. 1.3, there is 13H, and so on.
77 (7) Hardware Breakpoint Control Register 76543210
Address:C4H ------HBI BONWR BONRD Read/Write (---) (---) (---) (---) (---) (R/W) (R/W) (R/W) Initial Value (---) (---) (---) (---) (---) (X) (0) (0)
Interrupt INT0 can be generated when external bus address matches value in Hardware Breakpoint Address Registers and when minimum one of BONWR (Break on Write) or BONRD (Break on Read) are ”1”. Interrupt is generated as positive impulse (”0”->”1”->”0”).
When the BONWR='0' and BONRD='0' and UKIE='0', the INT0 pin will stay in high impedance state with only 47k pullup connected to it.
[Bit 2] HBI – this bit can be used to distinguish if the INT0 interrupt was caused by the Hardware breakpoint or the User Key. If HBI=1, the interrupt was caused by the Hardware breakpoint. If HBI=0, the interrupt was caused by the User Key. If both HBI and UKI (see the Hardware Status register) are log. ‘1’, the interrupt was caused by both pressing the User Key and the Hardware breakpoint.
Note: only addresses A0-15 are compared when small model is selected (System Configuration Register).
(8) Hardware Breakpoint Address Registers 76543210
Address: C5H A7 A6 A5 A4 A3 A2 A1 A0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial Value (?) (?) (?) (?) (?) (?) (?) (?)
76543210
Address:C6H A15 A14 A13 A12 A11 A10 A9 A8 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial Value (?) (?) (?) (?) (?) (?) (?) (?)
76543210
Address:C7H A23 A22 A21 A20 A19 A18 A17 A16 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial Value (?) (?) (?) (?) (?) (?) (?) (?)
(9) Hardware Status Register 76543210
Address:C8H ------UKEY UKI UKIE MSEL Read/Write ------R (R/W) (R) Initial Value (---) (---) (---) (---) (---) (0) (0) (X)
[Bit 0] MSEL – this bit holds the value of the MSEL jumper J10. When the jumper is short, this bit is ‘0’, otherwise it is ‘1’. When both the PE kernel and Fujitsu Softune monitor are present in the external FLASH memory,
78 this bit is used by the PE kernel to decide whether to run the Fujitsu Softune Monitor or not. When MSEL=’0’, the Softune monitor will be run, otherwise (MSEL=’1’) the PE kernel remain active.
[Bit 1] UKIE – when ‘1’, pressing the User Key button (or switching the User Key DIP switch ON) will produce a 25ms pulse on the INT0 CPU signal. When both UKIE = '0' and (BONRD='0' and BONWR='0'), the INT0 CPU signal stays in high impedance state with only 47k pullup connected to it.
[Bit 2] UKI – this bit can used to distinguish, if the INT0 interrupt was caused by the User Key or the Hardware Breakpoint (or both, see Hardware Breakpoint Control register). If UKI=1, the interrupt was caused by the User Key. If both UKI and HBI (see the Hardware Breakpoint Control register) are log. ‘1’, the interrupt was caused by both pressing the User Key and the Hardware breakpoint.
[Bit 3] UKEY – this bit indicates the status of the User Key Button. Read: 0: The user key is not pressed 1: The user key is pressed
79 ON
1 2 3 4 5 6 7 8
Fig. 2:The Mainboard layout with default jumper setting (for Softune)
80 DEFAULT JUMPER SETTINGS
These jumpers come in the SHORT position as a default factory setting:
J1: The User UART serial line reset polarity is set for Softune. J5: The DTR line of UART1 serial interface is selected as a source for the serial line reset J9: The RTS-CTS hardware flow control is selected (not the loopback) J10: The Softune monitor is selected J17: The Speaker is connected to the output of the audio amplifier J21: 3-4, 5-6 The SIN0, SOT0 signals are connected to the UART0 RS232 driver J22: 3-4, 5-6 The SIN1, SOT1 signals are connected to the UART1 RS232 driver J22: 7-8 The UART0&1 Serial line reset is connected to the reset logic J23: 3-4, 5-6 The User UART SINU, SOTU signals are connected to the User UART RS232 driver J23: 7-8 The User UART Serial line reset is connected to the reset logic J23: 11-12, 13-14 The User UART CTSU, RTSU signals are connected to the User UART RS232 driver J24: 3-4, 5-6 The CAN0 RX, TX signals are connected to the CAN0 bus interface J25: 3-4, 5-6 The CAN1 RX, TX signals are connected to the CAN1 bus interface J38: 1-2 The PPG0 is chosen as the source for the audio apmlifier
81 Chapter 10
What to do if ...
This chapter includes hints for DevKit16 operation, which should be checked before call technical support
• The green LED on the Mainboard is blinking. What should I do ? 1. The MD0-MD2 CPU pins are pulled to '0' by some device. Check the MD0-MD2 DIP switches on the CPU board - they must be all "OFF". • The Mainboard does not work. What to do ? 1. Check if the green diode shines without blinking. If it does, switch the MD0 switch on the CPU "ON" and press reset. If the diode blinks, FPGA is working and you can proceed with the next steps. If it doesn't, there is something wrong - check your power supply voltage, jumpers J4, J11, J12, J29 (all must be “OFF”) and the FPGA EEPROM. Try to burn the default FPGA content to the EEPROM. If this doesn't help, you must contact our support. 2. Switch MD0 to OFF and set the Serial programming mode on the Mainboard DIP switches. Set all the jumpers to their default positions (see the CPU and Mainboard layout figures), and the J1 jumper to the 2-3 position. Connect the serial cable to the USER UART port 3. Run the FlashTool. Set the "External bus free" to "yes" and press "Connect". If you pass this step successfully, it means that CPU is working properly. If not, there is something wrong with the PC to CPU communication. Once more, check all of the mainboard jumpers and also your PC communication interface, if you can. • The Processor Expert™ debugger doesn’t start (kernel does not response) 1. Check the communication cable. It has to be connected properly on both sides. Also, close all programs that could possibly use the communication port you are trying to use. 2. Check the serial line reset LED diodes (D11 and D10). If they shine, the mainboard is reset by serial line. In that case,
82 check the configuration of J1, J2 jumpers – both of them should be in the 2-3 position. 3. Check the kernel version you have burned in FLASH. For Processor Expert 2.34, the kernel version must be “1.3” (this number is displayed on the LED display, when you reset the mainboard). • The Fujitsu Softune debugger doesn’t start - the “Invalid communication status (or cable connection)” error message appears 1. Check the communication cable. It has to be connected properly on both sides. Also, close all programs that could possibly use the communication port you are trying to use. 2. Check the serial line reset LED diodes (D11 and D10). The D11 should shine until the debug session is started, the D10 should be always OFF. If this is not true, check the configuration of J1, J2 jumpers – J1 should be the 1-2 position, J2 in the 2-3 position as displayed on the fig. 2. 3. Check the debug monitor version you have burned in FLASH. For Softune V30L24, the monitor version must be “1.3.” (this number is displayed on the LED display, when you move the J1 to the 2-3 position). • Check the FAQs on the Processor Expert WWW site
83 Chapter 11
Get the most from DevKit16
This chapter provides hints and tips how to benefit more from DevKit16 and its options.
DOWNLOAD THE CURRENT SW AND HW UPDATES
For bug fixes in SW and HW, please check this link: www.processorexpert.com/devkit16
Here you should find the most current versions of debug monitor & kernel and also FPGA contents.
CHECK THE NET FOR NEWEST BEANS
You can download beans with extra feature on our website. Just follow this link: www.processorexpert.com/devkit16/Professional
84 Chapter 12
DevKit16 Power Supply Requirements
DevKit16 doesn’t come with power supply, please check, if your one match the requirements before you plug it to DevKit16!
• Power supply voltage: 9V
• Power supply current (CPU board MB90F543 with Main board):
• Single chip CPU mode, no external peripheral connected: 290mA max.
• External bus mode, no peripheral connected: 350mA
• External bus with:
" keyboard connected: 450mA typical, but can vary with the keyboard used (most of modern AT keyboard uses max. 100mA. User should check his keyboard current requirements before connecting the keyboard to the DevKit16 Mainboard).
" keyboard and VGA interface connected: 650mA
WE RECOMMEND USING 9V STABILIZED POWER SUPPLY WITH 1.5A (MIN.) OUTPUT CURRENT. IF THE POWER SUPPLY CAN NOT DELIVER CURRENTS AS SPECIFIED IN THE SPECIFICATION ABOVE, THE DEVKIT16 WILL NOT WORK PROPERLY – THE BOARD WILL BE PERIODICALLY RESET BY THE MB3771 POWER SUPPLY SUPERVISOR.
Warning: If the DevKit16 is powered using the on-board stabilizer, the supply current must not exceed the 1A limit of the stabilizer. Before connecting any peripheral to the DevKit16, please check that its power supply current requirements doesn’t does not cause this limit to be exceeded.
85 Chapter 13
Warranty and Disclaimer
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts its warranties and its liability for the DEVKIT16 and all its deliverables (eg. software, application examples, target boards, evaluation boards, etc.), its performance and any consequential damages, on the use of the Product in accordance with (i) the terms of the License Agreement and the Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the Product and any consequential damages in cases of unauthorised decompiling and/or reverse engineering and/or disassembling. Note, the DEVKIT16 and all its deliverables are intended and must only be used in an evaluation laboratory environment.
1. Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in accordance with the accompanying written materials for a period of 90 days form the date of receipt by the customer. Concerning the hardware components of the Product, Fujitsu Microelectronics Europe GmbH warrants that the Product will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of 1 year from the date of receipt by the customer.
2. Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire liability and the customer´s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH´s sole discretion, either return of the purchase price and the license fee, or replacement of the Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the customer´s use or the transport. However, this warranty is excluded if the defect has resulted from an accident not attributable to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH.
86 3. To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH disclaims all other warranties, whether expressed or implied, in particular, but not limited to, warranties of merchantability and fitness for a particular purpose for which the Product is not designated.
4. To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH´s and its suppliers´ liability is restricted to intention and gross negligence.
NO LIABILITY FOR CONSEQUENTIAL DAMAGES
To the maximum extent permitted by applicable law, in no event shall Fujitsu Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever (including but without limitation, consequential and/or indirect damages for personal injury, assets of substantial value, loss of profits, interruption of business operation, loss of information, or any other monetary or pecuniary loss) arising from the use of the Product.
Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect.
87 Chapter 14
Revision and Error List
The bugs and improvements that need to be observed when working with this tool:
Date Revisions - Errors Revised Version 05.08.1999 Describes Devkit16 ver 1.1 V1.0 10.09.1999 Describes Devkit16 ver 1.2 V1.1 16.12.1999 Describes Devkit16 ver 1.3 V1.2 10.02.2000 • Schematics bug on page 89 : J5 was incorrectly V1.21 labeled as J1. • Added J1 description on p. 18 and 27 13.02.2000 • Changes done on pages 25-34 to make the V1.22 description of Flash tool more comprehensive. • The table “Device Bus (K2) and Interface Bus (K1 ) connectors pins” on pages 86, 87, 88 was not consistent with the schematics. • Schematics bug on page 90 : J11 was connected to SDA instead of SCL and J12 to SCL instead of SDA. 15.02.2000 Points about burning Fujitsu debug monitor and PE V1.23 debug kernel added to the paragraph “Commonly used settings of the controls” (Chapter Flash It, page 27).
16.02.2000 From the PE 2.34 version and higher (or with the V1.24 latest Flashtool update), the special command line option "-move 13 ff" is not needed when burning the Fujitsu debug monitor. This revision is reflecting that new feature.
03.03.2000 • From PE 2.34 and higher, full support for CPU 90F497 was added. A new CPU board for this processor is distributed. This revision reflects
88 these facts. V1.25
• An error was found in the chapter “Mainboard description” – the Prototype connector had different pinout than the one in the schematics (the schematics are correct, however)
04.03.2000 An error in the FLASH end address in the SWAP V1.26 mode - on the page 73, FLASH ends at 140000H (not 180000H)
11.05.2000 • In the chapter 4, paragraph “Get it running”, the V1.27 Softune Workbench is recommended to be run first (with the “Demo.LEDs” project). However, the Softune *.PRJ file is generated by the PE during codesign process, so the PE must be run first. The paragraph was updated to reflect this change. Also, the communication settings for the Softune debug monitor are described there
• In the chapter 6, the section “How to burn the CPU FLASH without Devkit16” was added
• The chapter “What to do if” was updated
18.12.2000 • The pinout of the A/D connector on page 51 has V1.28 been corrected
• MCU board schematics has been corrected
89 Chapter 15
Appendix
Here you will find schematics of the CPU board for MB90F543, the Main board schematics, Interface bus and Device Bus description
Device Bus (K2) and Interface Bus (K1 ) connectors pins:
DIN Conn. Device Bus Interface Bus PIN PIN NO. CPU Pin Nr. Function CPU PIN Nr. SIGNAL 2nd Function A1 18 SOT0 85 AD00 P00 B1 19 SCK0 86 AD01 P01 C1 20 SIN0 87 AD02 P02 A2 24 SOT1 88 AD03 P03 B2 22 SCK1 89 AD04 P04 C2 21 SIN1 90 AD05 P05 A3 91 AD06 P06 B3 92 AD07 P07 C3 93 AD08 P10 A4 69 INT0 94 AD09 P11 B4 70 INT1 95 AD10 P12 C4 71 INT2 96 AD11 P13 A5 72 INT3 97 AD12 P14 B5 29 INT4 98 AD13 P15 C5 30 INT5 99 AD14 P16 A6 31 INT6 100 AD15 P17 B6 32 INT7 1 A16 P20 C6 25 SOT2 2 A17 P21 A7 26 SCK2 3 A18 P22 B7 28 SIN2 4 A19 P23 C7 5 A20 P24 A8 6 A21 P25 B8 7 A22 P26 C8 8 A23 P27 A9 9 ALE P30 B9 10 \RD P31 C9 12 \WRL P32 A10 13 \WRH P33
90 DIN Conn. Device Bus Interface Bus PIN PIN NO. CPU Pin Nr. Function CPU PIN Nr. SIGNAL 2nd Function B10 14 HRQ P34 C10 15 \HAK P35 A11 47 TIN0 16 RDY P36 B11 48 TOT0 17 CLK P37 C11 GND GND GND A12 67 TIN1 18 SOT0 P40 B12 68 TOT1 19 SCK0 P41 C12 20 SIN0 P42 A13 24 SOT1 P45 B13 53 IN0 22 SCK1 P44 C13 54 IN1 21 SIN1 P43 A14 55 IN2 25 SOT2 P46 B14 56 IN3 26 SCK2 P47 C14 57 IN4 28 SIN2 P50 A15 58 IN5 SDA B15 59 OUT2/IN6 SCL C15 60 OUT3/IN7 61 PPG0 P80 A16 65 OUT0 62 PPG1 P81 B16 66 OUT1 67 TIN1 P86 C16 VCC VCC A17 59 OUT3/IN7 33 ADTG P55 C17 60 OUT2/IN6 68 TOT1 P87 C17 AVCC 34 AVCC A18 35 AVR+ B18 36 AVR- C18 AGND 37 AGND A19 38 AN0 P60 B19 39 AN1 P61 C19 GND GND GND C20 40 AN2 P62 A21 41 AN3 P63 C20 43 AN4 P64 A21 44 AN5 P65 B21 45 AN6 P66 C21 46 AN7 P67 A22 61 PPG0 77 \RST B22 62 PPG1 52 \HST C22 63 PPG2 69 INT0 P90 A23 64 PPG3 70 INT1 P91 B23 71 INT2 P92 C23 72 INT3 P93 A24 73 TX0 29 INT4 P51 B24 74 RX0 30 INT5 P52 C24 75 TX1 31 INT6 P53 A25 76 RX1 32 INT7 P54 B25 53 IN0 P70 C25 54 IN1 P71 A26 55 IN2 P72 B26 56 IN3 P73
91 DIN Conn. Device Bus Interface Bus PIN PIN NO. CPU Pin Nr. Function CPU PIN Nr. SIGNAL 2nd Function C26 59 OUT2/IN6 P76 A27 60 OUT3/IN7 P77 B27 NC(SGO) C27 NC(SGA) A28 73 TX0 P94 B28 74 RX0 P95 C28 75 TX1 P96 A29 76 RX1 P97 B29 79 X1AJ C29 80 X0AJ A30 82 X0J B30 83 X1J C30 VCC VCC A31 49 MD0 B31 50 MD1 C31 NC A32 51 MD2 B32 NC C32 GND GND
92 K2 DIN_41612 C30 A31 B31 C31 A32 B32 C32 A1 B1 C1 A2 B2 C2 A3 B3 C3 A4 B4 C4 A5 B5 C5 A6 B6 C6 A7 B7 C7 A8 B8 C8 A9 B9 C9 A10 B10 C10 A11 B11 C11 A12 B12 C12 A13 B13 C13 A14 B14 C14 A15 B15 C15 A16 B16 C16 A17 B17 C17 A18 B18 C18 A19 B19 C19 A20 B20 C20 A21 B21 C21 A22 B22 C22 A23 B23 C23 A24 B24 C24 A25 B25 C25 A26 B26 C26 A27 B27 C27 A28 B28 C28 A29 B29 C29 A30 B30 INT0 INT1 INT2 INT3 INT4 INT5 SCK2 SIN2 SOT0 SCK0 SIN0 SOT1 SCK1 SIN1 INT6 INT7 SOT2 TIN0 TOT0 TIN1 TOT1 IN0 IN1 IN2 IN3 IN4 IN5 OUT2/IN6 OUT3/IN7 OUT0 OUT1 VCC OUT3/IN7 OUT2/IN6 PPG0 PPG1 PPG2 PPG3 TX0 RX0 TX1 RX1 VCC GND AVCC AGND GND GND
K1 DIN_41612 A9 B9 C9 A10 B10 C10 A11 B11 C11 A12 B12 C12 A13 B13 C13 A14 B14 C14 A15 B15 C15 A16 B16 C16 A17 B17 C17 A18 B18 C18 A19 B19 C19 A20 B20 C20 A21 B21 C21 A22 B22 C22 A23 B23 C23 A24 B24 C24 A25 B25 C25 A26 B26 C26 A27 B27 C27 A28 B28 C28 A29 B29 C29 A30 B30 C30 A31 B31 C31 A32 B32 C32 A1 B1 C1 A2 B2 C2 A3 B3 C3 A4 B4 C4 A5 B5 C5 A6 B6 C6 A7 B7 C7 A8 B8 C8 AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 A16 A17 A18 A19 A20 A21 A22 A23 ALE #RD #WRL #WRH HRQ #HAK RDY CLK GND SOT0 SCK0 SIN0 SOT1 SCK1 SIN1 SOT2 SCK2 SIN2 SDA SCL PPG0 PPG1 TIN1 VCC ADTG TOT1 AVCC AVR+ AVR- AGND AN0 AN1 GND AN2 AN3 AN4 AN5 AN6 AN7 RSTX #HST INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 IN0 IN1 IN2 IN3 OUT2/IN6 OUT3/IN7 SGO SGA TX0 RX0 TX1 RX1 X1AJ X0AJ X0J X1J VCC GND MD0 MD1 MD2
SOUND J15 JUMPER2 K9 K375A J19 J20 X0A X0AJ
IC1 1 JUMPER2 JUMPER2 AD00 85 18 SOT0 CH1 1 1
P00/AD00 P40/SOT0 SDA SCL J16 1 2 AD01 86 19 SCK0 P01/AD01 P41/SCK0 JUMPER2 2 AD02 87 20 SIN0 P02/AD02 P42/SIN0 HRQ #HAK X1A X1AJ 1
AD03 88 21 SIN1 1 P03/AD03 P43/SIN1 AD04 89 22 SCK1 SK 129 25.4mm P04/AD04 P44/SCK1 AD05 90 24 SOT1 J17 PL2 +5V P05/AD05 P45/SOT1 JUMPER2 PL3 AD06 91 25 SOT2 1 1 2 2 P06/AD06 P46/SOT2 X0 X0J
AD07 92 26 SCK2 1 +5V P07/AD07 P47/SCK2 D4 D6 A K A K J13 J18 AD08 93 28 SIN2 IC3 JUMPER2 P10/AD08 P50/SIN2 JUMPER2 1N4007 SMD 1N4007 SMD AD09 94 29 INT4 LM7805 P11/AD09 P51/INT4 X1 X1J D5 D7 1
AD10 95 30 INT5 1 A K A K IN OUT VCC P12/AD10 P52/INT5 IN OUT AD11 96 31 INT6 P13/AD11 P53/INT6 1N4007 SMD 1N4007 SMD AD12 97 32 INT7 VCC
P14/AD12 P54/INT7 GND AD13 98 33 ADTG C11 GND 1 2 C16 C15 P15/AD13 P55/ADTG AD14 99 47 TIN0 100N 100N 100N P16/AD14 P56/TIN0 AD15 100 48 TOT0 J5 C10 IC2 R15 GND PL1 +5V C18 P17/AD15 P57/TOT0 J3 JUMPER2 10M/25V 1 8 RSTX 10K 100M/25V JUMPER2 CT RESET GND A16 1 34 AVCC 1 2 7 P20/A16 AVcc VCC VSC VSA A17 2 1 3 6 GND GND GND GND P21/A17 OUTC VSB/RESIN A18 3 35 AVR+ R1 R3 4 5 R16 P22/A18 AVR+ GND VCC A19 4 220R 1K 3K6 P23/A19 J8 JUMPER3 A20 5 GND MB3771 P24/A20 SIN1 A21 6 36 AVR- GND PWRD P25/A21 AVR- 1 A22 7 1 R4 P26/A22 K7 A23 8 37 AGND 220R P27/A23 AVss BOXHEADER 5X2
1 GND SIN0 ALE 9 38 AN0 R2 K3 K5 P30/ALE P60/AN0 AD00 AD01 #RD 10 39 AN1 1K J6 J4 1 2 A16 A17 MD2 #HST P31/#RD P61/AN1 MD0 MD2 1 2 1 2 #WRL 12 40 AN2 JUMPER2 D2 3 4 A18 A19 IN0 IN1 P32/#WRL/#WR P62/AN2 JUMPER2 SERRES A K 3 4 3 4 #WRH 13 41 AN3 5 6 A20 A21 IN2 IN3 P33/#WRH P63/AN3 5 6 5 6 HRQ 14 43 AN4 1N4148 SMD 7 8 A22 A23 IN4 IN5 P34/HRQ P64/AN4 SW1 J9 JUMPER3 7 8 7 8 #HAK 15 44 AN5 9 10 ALE #RD OUT2/IN6 OUT3/IN7 P35/#HAK P65/AN5 PB1720 SCK1 9 10 9 10 RDY 16 45 AN6 GND #WRL PPG0 PPG1 P36/RDY P66/AN6 VCC GND 1 11 12 11 12 CLK 17 46 AN7 #WRH HRQ PPG2 PPG3 P37/CLK P67/AN7 13 14 13 14 GND #HAK RDY OUT0 OUT1 GND 15 16 15 16 INT0 69 53 IN0 CLK SOT0 TIN1 TOT1 P90/INT0 P70/IN0 SCK0 17 18 17 18 INT1 70 54 IN1 SCK0 SIN0 INT0 INT1 P91/INT1 P71/IN1 19 20 19 20 INT2 71 55 IN2 SIN1 SCK1 INT2 INT3 P92/INT2 P72/IN2 C12 J7 JUMPER3 21 22 21 22 INT3 72 56 IN3 FVCC SOT1 TX0 RX0 P93/INT3 P73/IN3 RSTX 100N 23 24 23 24 TX0 73 57 IN4 SOT2 SCK2 TX1 RX1 P94/TX0 P74/IN4 SOT1 25 26 25 26 RX0 74 58 IN5 C SIN2 RSTX PA0 P95/RX0 P75/IN5 1 27 28 27 28 TX1 75 59 OUT2/IN6 INT4 INT5 X1A X0A P96/TX1 P76/OUT2/IN6 29 30 29 30 RX1 76 60 OUT3/IN7 P97/RX1 P77/OUT3/IN7 #HST HEADER 15X2 HEADER 15X2 SOT0 RSTX 77 61 PPG0 #RST P80/PPG0 62 PPG1 C13 K4 K6 P81/PPG1 100N PA0 78 63 PPG2 INT6 INT7 GND X0 PA0 P82/PPG2 1 2 1 2 64 PPG3 ADTG AVCC X1 FVCC P83/PPG3 SW2 GND 3 4 3 4 MD0 49 65 OUT0 AVR+ AVR- AD00 AD01 MD0 P84/OUT0 PB1720 5 6 5 6 MD1 50 66 OUT1 AGND AN0 AD02 AD03 MD1 P85/OUT1 7 8 7 8 MD2 51 67 TIN1 AN1 AN2 AD04 AD05 MD2 P86/TIN1 9 10 9 10 68 TOT1 AN3 GND AD06 AD07 P87/TOT1 GND 11 12 11 12 X1 #HST 52 VCC VCC J11 AN4 AN5 AD08 AD09 #HST C1 13 14 13 14 C7 22pF 4MHz 27 C 10M/25V VCC J10 AN6 AN7 AD10 AD11 C AVCC 1 15 16 15 16 X1 83 1 R6 TIN0 TOT0 AD12 AD13 GND X1 C2 1 2 17 18 17 18 23 100N A J2 VCC SW3 1K MD0 MD1 AD14 AD15 VCC 2 3 19 20 19 20 A
X0 82 84 D1 R8 10K MD0 1 16 GND XO VCC JUMPER2 3 4 GND R9 10K MD1 2 15 HEADER 10X2 HEADER 10X2 1N4148 SMD 1N4148 4 5 C6 22pF FVCC R10 10K MD2 3 14 6 X1A 79 11 R11 10K RSTX 4 13 HEADER 4 GND X1A VSS K 42 R12 10K #HST 5 12 SERRES GND HEADER 6 X2 VSS X0A80 81 GND #HST6 11 RSTX GND X0A VSS C4 C3 C5 R13 10K AD00 7 10 D3 C9 22pF 32.768KHz MB90540 GND 100N 100N 10M/25V R14 10K AD01 8 9 LED 5mm Title C8 22pF K Devkit16 - CPU Board SW DIP-8 GND GND Size Number Revision A3 Ver. 1 3 Date: 18-Dec-2000 Sheet of File: D:\Designs\Unis\Pcb\cpuboard13\Cpuboard13.ddbDrawn By:
93 1 2 3 4 5 6
K1 Bus Interface Connector DIN_41612 B24 C24 A25 B25 C25 A26 B26 C26 A27 B27 C27 A28 B28 C28 A29 B29 C29 A30 B30 C30 A31 B31 C31 A32 B32 C32 A1 B1 C1 A2 B2 C2 A3 B3 C3 A4 B4 C4 A5 B5 C5 A6 B6 C6 A7 B7 C7 A8 B8 C8 A9 B9 C9 A10 B10 C10 A11 B11 C11 A12 B12 C12 A13 B13 C13 A14 B14 C14 A15 B15 C15 A16 B16 C16 A17 B17 C17 A18 B18 C18 A19 B19 C19 A20 B20 C20 A21 B21 C21 A22 B22 C22 A23 B23 C23 A24
D D AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 A16 A17 A18 A19 A20 A21 A22 A23 ALE #RD #WRL #WRH HRQ #HAK RDY CLK GND SOT0 SCK0 SIN0 SOT1 SCK1 SIN1 SOT2 SCK2 SIN2 SDA SCL PPG0 PPG1 TIN1 VCC ADTG TOT1 AVCC AVR+ AVR- AGND AN0 AN1 GND AN2 AN3 AN4 AN5 AN6 AN7 #RST #HST INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 IN0 IN1 IN2 IN3 IN6 IN7 SGO SGA TX0 RX0 TX1 RX1 X1 AJ X0 AJ X0 J X1 J VCC MD0 MD1 MD2 GND
AD Header VCC
#WRH R79 10K K8 AVCC AVCC CAN_Sound 1 2 #WRL R78 10K AGND AGND CAN_Snd.sch 3 4 AVR+ AVR+ 5 6 ADTG AVR- PC compatible keyboard 7 8 RX1 AN0 AN1 9 10 TX1 AN2 AN3 11 12 AN4 AN5 13 14 RX0 AN6 AN7 15 16 J38 TX0 SGO VCC HEADER 8X2 1 C AudioIn C R90 RDY 10K PPG0 K17 FPGA FPGA.sch USER0 1 R91 0R USER0 USER1 2 R92 0R USER1 #RST #RST 3 #HST Serial_IF Serial_IF.sch 4 R93 0R GND 5 R94 0R VCC #UARTSW[0..1] #UARTSW[0..1] MD[0..2] MINIDIN SER[0..8] 47P 47P 47P CTSU CTSU RTSU RTSU C92 C91 C90 SINU SINU SOTU SOTU INT6 GND
BusCtrl[0..7]
J20 J19 1
A[16..23] RY/BY 1 JUMPER2 SP[0..37] AD[0..15] BYTE SP01 SP00 LEDDisp_EEPROM 2 1 AD15/A00 SP03 SP02 LEDEeprom.sch 4 3 CSLED[0..1] CSFLASH SP05 SP04 6 5 CSLED[0..1] CSRAM[0..1] SP07 SP06 8 7 AD[0..7] Prototype connector SP11 SP10 B 10 9 B SDA SDA INT[0..7] SP13 SP12 12 11 SCL SCL SP15 SP14 VCC U? 14 13 CSU[0..2] SP17 SP16 3 2 16 15 IN OUT SDAU SDAU 1 K15 ADJ SCLU SCLU K20 HEADER 8X2 R80 VCC GND 1 2 LM317P(3) 240R CSU1 CSU2 Addr_IO 3 4 C93 C94 INT5 INT4 5 6 100n 100n #CSU0 #WRL 7 8 R81 #RD ALE 9 10 K10 HEADER 8X2 GND 470R GND A00 A01 11 12 SP36 SP37 A02 A03 15 16 Memories 13 14 SP34 SP35 VCC A04 A05 13 14 Memories.sch 15 16 SP32 SP33 GND A06 A07 11 12 R44 17 18 SP30 SP31 PDIUSBP11 IC25 AD07 AD06 9 10 1K5 19 20 SP26 SP27 K18 AD[0..15] CSRAM[0..1] AD05 AD04 7 8 21 22 SP24 SP25 SUSPND 2 14 R43 VCC K19 A[16..23] CSFLASH AD03 AD02 5 6 1 #OE VCC 23 24 SP22 SP23 VM 9 1K5 AD15/A00 AD01 AD00 3 4 2 SPEED 1 25 26 SP20 SP21 VP 6 10 BusCtrl[0..7] BYTE 1 2 3 SUSPND D- 2 RCV 13 11 RY/BY HEADER 13X2 4 VMO D+ 3 #USBOE 12 3 Addr_IO 5 VPO RCV 4 Simulated ports 0-3 SPEED 4 6 VP VPO 7 5 GND HEADER 4 7 GND VM VMO 8 A GND A HEADER 8 Title DevKit16 Mainboard Size Number Revision B Ver. 1 3 Date: 11-Nov-1999 Sheet of File: D:\Devkit16v13.Ddb Drawn By: 1 2 3 4 56
94 1 2 3 4 5 6 7 8
SER[ 0..8]
SI NU IC19D IC18D IC19B IC18B 4066 SOIC 4066 SOIC 4066SOIC 4066 SOIC SOTU SI N0 8 9 SI NU SI N1 8 9 SI NU SOT0 11 10 SOTU SOT1 11 10 SOTU I O I O I O I O D D #UARTSW[0..1] C C C C CTSU 6 6 RTSU UARTSW0 UARTSW1 12 UARTSW0 12 UARTSW1
IC19C IC18C IC19A IC18A 4066 SOIC 4066 SOIC 4066 SOIC 4066 SOIC SI N0 4 3 SI N0D SI N1 4 3 SI N1D SOT0 1 2 SOT0D SOT1 1 2 SOT1D I O I O I O I O IC20B C C C C #UARTSW0 3 4 UARTSW0 5 5 #UARTSW0 #UARTSW1 13 #UARTSW0 13 #UARTSW1 74HCT04 SOIC
IC20A
#UARTSW1 1 2 UARTSW1
C21 IC13 C23 74HCT04 SOIC 100n 1 2 100n C1+ V+ 3 USER UART Interface C1- C22 4 6 C24 C2+ V- 100n 5 100n C2- GND C GND J23 GND 11 14 J9 K6 C T1IN T1OUT 10 7 RTS JUMPER3 RTS GND 5
1 2 T2IN T2OUT 1 PCGND SOTU 9 3 4 SI NU 12 13 4 5 6 R1OUT R1IN PCDSR 9 8 CTS 8 7 8 R2OUT R2IN PCRTS 3 VCC 9 10 VCC PCRXD RTSU C25 CTS 7 11 12 PCCTS CTSU 15 16 VCC 2 13 14 GND VCC PCTXD #RESPU 6 15 16 PCDTR CAN 100 Compatible LEDs GND MAX232A 100nGND 1 VCC HEADER 5X2 1 CAN 9 Z 90 SCK2 K D7 A2 LED 3mm Red
SOT2 K D6 A3 LED 3mm Red
SOT1 K D5 A4 LED 3mm Red J1 IC27D C28 SCK1 K D4 A5 1 C26 IC14 100n LED 3mm Red 100n JUMPER3 9 8 #RST 1 2 C1+ V+ 3 C29 CPU UART0,1 Interface SI N1 K D3 A6 IC20D C1- R46 4 6 LED 3mm Red C2+ V- 100n 9 8 1K 5 K5 74HCT05 C2- HEADER 5X2 GND GND 5 B SI N0 K D2 A7 C27 100n B GND J22 GND 11 14 9 LED 3mm Red T1IN T1OUT 10 7 4 74HCT04 SOIC 1 2 GND T2IN T2OUT K D11 A SOT1D 8 SCK0 K D1 A8 3 4 SI N1D 12 13 3 LED 3mm Red 5 6 R1OUT R1IN GND 9 8 #RESPU 7
7 8 R2OUT R2IN 1 LED 3mm Red 2 SOT0 K D0 A9 9 10 C30 100n #RESP1 6 LED 3mm Red R1 VCC VCC 15 16 VCC 1 GND VCC J8 1K JUMPER2 GND MAX232A GND CAN 9 Z 90
J2 IC27F 1 K4 JUMPER3 13 12 #RST GND 5 IC20E C31 IC15 C33 9 R48 100n 1 2 100n J7 4 C1+ V+ JUMPER2 11 10 1K 3 8 74HCT05 C1- 4 6 3 C32 C2+ V- C34 100n 5 100n 7
C2- 1 74HCT04 SOIC GND 2 K D10 A GND J21 GND 11 14 #RESP0 6 T1IN T1OUT CAN 9 Z 90 10 7 1 1 2 GND T2IN T2OUT GND SOT0D 3 4 LED 3mm Red SI N0D 12 13 5 6 R1OUT R1IN 9 8 #RESP0 7 8 R2OUT R2IN 9 10 C35 1 100n J5 VCC HEADER 5X2 VCC 15 16 VCC JUMPER3 A GND VCC A GND MAX232A GND #RESP1
Title DevKit16 Mainboard - Serial IF Size NumberVer. 1 Revision 3 A3 Date: 10-Feb-2000 Sheet of File: D:\Devkit16v13.Ddb Drawn By: 1 2 3 4 5 6 78
95 1 2 3 4
VCC VCC H H
VCC R101 C11 10k 100n J4 CCLK
R57 1 PRMODE IC24B 10k 8 7 VCC GND MODE 4 IC9 VCC 6 4 CE IC27E R59 #LDC 5 6 1 DIN IC20F CEO VCC VP P DATA 2 CCLK 10k USW R31 10k CLK 74HCT32 3 #INIT #PROG 13 12 11 10 #RST UART0/1 R32 10k RESET/OE SWAP R33 10k
GND VCC AdrIOSW R34 10k AT17C256 74HCT04 SOIC 74HCT05 FLASH8/16 R35 10k UMD2 R36 10k 5 IC27A UMD1 R37 10k GND R9 D9 UMD0 R38 10k SCL J11 CCLK DIN 1 2 K 1kA
SCL 1 SDA DIN
G SDA 1 G J12 VCC VCC 74HCT05 FPGA Status 74HCT04 SOIC R101 IC20C System Control DIP Switch R42 R41 R40 10K FPGA prog. 10k 10k 10k SW1 K13 5 6 MODE USW 9 8 VCC 1 UART0/1 10 7 GND 1J6 2 SWAP 11 6 CCLK 3 AdrIOSW 12 5 4 FPGA MODE FLASH8/16 13 4 XMODE 5 UMD2 14 3 GND DONE GND 6 UMD1 15 2 DIN VCC 7 UMD0 16 1 #PROG 8 #INIT 9 SW DIP-8 Mainboard Reset IC6 26 53 78 105 130 156 183 208 SW3 HEADER 9 52 90 UMD0 MODE IO90 F PB1720 93 UMD1 F VCC VCC VCC VCC VCC VCC VCC VCC IO93 GND JTAG 106 94 UMD2 PROG IO94 K12 104 95 FLASH8/16 DONE IO95 VCC 77 96 AdrIOSW 1 INIT/IO IO96 GND 56 97 SWAP 2 HDC/IO IO97 #LDC 60 98 UART0/1 3 LDC/IO IO98 #UARTSW[0..1] TCK 99 #UARTSW0 4 IO99 153 100 #UARTSW1 IC24C 5 DIN/IO IO100 TDO 154 101 USW 9 6 SGCK4/DOUT/IO IO101 MSEL TDI 155 107 MSEL J10
8 7 CCLK IO107 1 GND 109 SDAU 10 8 IO109 VCC TMS TCK 7 110 SCLU IC27C 9 TCK/IO IO110 TDI 6 112 GND TDI/IO IO112 74HCT32 HEADER 9 TMS 16 113 SCLO 5 6 TMS/IO IO113 SCLU TDO 157 114 SDAO TDO/IO IO114 1 4 115 USER0 IC24D OE VCC IO115 USER0 CLK 2 116 USER1 12 C10 IC21 PGCK1/IO IO116 USER1 74CHT05 ALE 55 117 SOTU IC27B 11 PGCK2/IO IO117 SOTU 100n 2 3 CLKX 108 119 SINU 13 GND OUT PGCK3/IO IO119 SINU UP17 160 120 RTSU 3 4 PGCK4/IO IO120 RTSU SDAU E 6.144MHz 122 CTSU E IO122 CTSU 74HCT32 #WRL207 123 UP00 GND SGCK1/IO IO123 SP25 49 124 UP01 SGCK2/IO IO124 74CHT05 FPGAEN 102 125 UP02 SGCK3/IO IO125 126 UP03 IO126 RDY 3 127 UP04 FPGA 1J29 IO3 IO127 #WRH 4 128 UP05 ENABLE IO4 IO128 #CSU0 5 129 UP06 K11 IO5 IO129 A23 8 132 UP07 UP00 UP01 IO8 IO132 1 2 A22 9 133 UP08 UP02 UP03 GND IO9 IO133 3 4 A21 10 134 UP09 UP04 UP05 IO10 IO134 5 6 A20 11 135 UP10 UP06 UP07 IO11 IO135 7 8 A19 14 136 UP11 UP08 UP09 IO14 IO136 9 10 A18 15 137 UP12 UP10 UP11 IO15 IO137 11 12 A17 17 138 UP13 UP12 UP13 IO17 IO138 13 14 A16 19 139 UP14 UP14 UP15 IO19 IO139 15 16 ADDR_IO 20 141 UP15 UP16 UP17 A[16..23] IO20 IO141 17 18 #RD 21 142 UP16 UP18 UP19 IO21 IO142 19 20 Addr_IO RY/BY 22 145 INT6 VCC GND IO22 IO145 21 22 D #CSFLASH 23 146 INT7 UP20 UP21 D BusCtrl[0..7] IO23 IO146 23 24 BYTE 24 147 INT1 UP22 UP23 CSFLASH IO24 IO147 25 26 AD15/A00 27 148 INT3 UP24 UP25 BYTE IO27 IO148 27 28 AD07 28 149 INT2 UP26 UP27 AD15/A00 IO28 IO149 29 30 AD00 29 150 INT0 UP28 UP29 IO29 IO150 31 32 AD01 30 151 INT4 UP30 UP31 IO30 IO151 33 34 AD06 31 152 INT5 UP32 UP33 IO31 IO152 35 36 AD02 32 159 UP34 UP35 IO32 IO159 37 38 AD05 34 161 UP18 UP36 UP37 IO34 IO161 39 40 AD03 35 162 UP19 IO35 IO162 AD04 36 163 CCLK HEADER 20X2 IO36 IO163 SP37 37 164 UKEY IO37 IO164 SP36 40 166 UP20 IO40 IO166 SP35 41 167 UP21 INT[0..7] IO41 IO167 SP34 42 168 UP22 IO42 IO168 SP33 43 169 UP23 IO43 IO169 SP32 44 171 UP24 IO44 IO171 SP31 45 172 UP25 IO45 IO172 User Key SP30 46 174 UP26 IO46 IO174 SP27 47 175 UP27 C IO47 IO175 C SP26 48 176 UP28 SW2 IO48 IO176 SP24 57 177 UP29 PB1720 IO57 IO177 SP23 58 178 UP30 IO58 IO178 SP22 59 179 UP31 IO59 IO179 SP21 61 180 UP32 IO61 IO180 SP20 62 181 UP33 IO62 IO181 SP17 63 184 UP34 IO63 IO184 SP16 64 185 UP35 IO64 IO185 SP15 67 186 UP36 IO67 IO186 SP14 68 187 UP37 IO68 IO187 SP13 69 188 #RST IO69 IO188 SP12 70 189 #HST IO70 IO189 #RST SP11 72 190 MD2 IO72 IO190 SP10 73 191 MD1 #HST IO73 IO191 SP07 74 193 MD0 IO74 IO193 SP06 75 194 #CSRAM0 IO75 IO194 MD[0..2] SP05 76 196 #CSRAM1 IO76 IO196 SP04 80 197 AD15 IO80 IO197 SP03 81 198 AD14 CSRAM0..1] B IO81 IO198 B SP02 82 199 AD13 IO82 IO199 SP01 83 200 AD12 IO83 IO200 SP00 84 201 AD11 IO84 IO201 CSLED0 85 204 AD10 SP[0..37] IO85 IO204 CSLED1 87 205 AD9 IO87 IO205 AD[0..15] CSU1 88 206 AD8 IO88 IO206 CSU2 89
IO89GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND CSLED[0..1]
CSU[0..2] 1 13 25 38 51 66 79 91 103 118 131 143 158 170 182 195
GND XCS20-4 TQ(208)C
Title A DevKit16 Mainboard - FPGA A Size Number Revision A3 Ver. 1 3 Date: 3-Feb-2000 Sheet of File: D:\Devkit16v13.Ddb Drawn By: 1 2 34
96 1 2 3 4
D LED Display D
IC16 IC17 AD00 2 19 DI1A AD06 2 19 DI2G D1 Q1 D1 Q1 AD01 3 18 DI1B AD05 3 18 DI2F D2 Q2 D2 Q2 AD02 4 17 DI1C AD04 4 17 DI2E D3 Q3 D3 Q3 AD03 5 16 DI1D AD07 5 16 DI2H D4 Q4 D4 Q4 AD07 6 15 DI1H AD03 6 15 DI2D D5 Q5 D5 Q5 AD04 7 14 DI1E AD02 7 14 DI2C D6 Q6 D6 Q6 AD05 8 13 DI1F AD01 8 13 DI2B D7 Q7 D7 Q7 AD06 9 12 DI1G AD00 9 12 DI2A D8 Q8 D8 Q8 CSLED011 CSLED1 11 C C 1 1 R19 OC R29 OC 10k GND 74HCT573M 10k GND 74HCT573M
DISP1 VCC DI2A 1k R11 16 14 A1 AN1 DI2B R12 15 1k B1 DI2C R13 3 1k C1 DI2D 2 1k R14 D1 DI2E 1k 1 R15 E1 DI2F 1k R16 18 F1 C DI2G 1k R17 17 C G1 DI2H 1k 4 R18 H1 VCC DI1A 1k R21 11 13 A2 AN2 DI1B 1k 10 R22 B2 DI1C 1k 8 R23 C2 DI1D 1k R24 6 D2 DI1E 1k R25 5 E2 DI1F 1k R26 12 F2 DI1G 1k R27 7 G2 DI1H 1k R28 9 H2 L-BD-A812RD
AD[0..7]
CSLED[0..1] SDAU Serial EEPROM SCLU VCC SDA JUMPER3 SCL SDA J14 J15 JUMPER3 1 1 B SCL SCL R95 1k B SDA R96 1k SCLU R97 1k SDAU R98 1k
VCC IC10 SCLU SDAU 8 6 SCLB VCC K14 VCC SCL 1 A0 1 2 5 SDAB SCLB A1 SDA 2 3 SDAB A2 J13 JUMPER2 3 4 7 1 GND WP 4 GND 24C08B-E/SN VCC GND GND HEADER 4 R54 I2C Header 10k
A A
Title DevKit16 Mainboard - LED Disp. and EEPROM Size NumberVer. 1 Revision 3 A4 Date: 11-Nov-1999 Sheet of File: D:\Devkit16v13.Ddb Drawn By: 1 2 34
97 1 2 3 4
SRAM
IC1 IC2 A01 12 13 AD08 A01 12 13 AD08 A0 I/O1 A0 I/O1 A02 11 14 AD09 A02 11 14 AD09 A1 I/O2 A1 I/O2 D A03 10 15 AD10 A03 10 15 AD10 D A2 I/O3 A2 I/O3 A04 9 17 AD11 A04 9 17 AD11 A3 I/O4 A3 I/O4 A05 8 18 AD12 A05 8 18 AD12 A4 I/O5 A4 I/O5 VCC A06 7 19 AD13 A06 7 19 AD13 A5 I/O6 A5 I/O6 A07 6 20 AD14 A07 6 20 AD14 A6 I/O7 A6 I/O7 A08 5 21 AD15 A08 5 21 AD15 A7 I/O8 A7 I/O8 A09 27 A09 27 A8 A8 R52 A10 26 A10 26 A9 A9 10K A11 23 A11 23 A10 A10 A12 25 A12 25 A11 A11 A18MR51 N/A18 A13 4 A13 4 A12 A12 A14 28 1 A19MA14 28 1 A19M 0R A13 NC A13 NC A15 3 A15 3 A14 A14 A16M 31 A16M 31 A15 A15 A17M2 VCC A17M 2 VCC A16 A16 32 32 VCC VCC #CSRAM022 #CSRAM1 22 CS1 CS1 N/A1830 N/A18 30 CS2 CS2 #RD24 #RD 24 OE OE IC23B #WRH29 16 #WRH 29 16 WE VSS WE VSS A17 4 6 A17M TC551001CP-55 GND TC551001CP-55 GND Addr_IO 5 IC3 IC4 A01 12 13 AD05 A01 12 13 AD05 74AC32 A0 I/O1 A0 I/O1 IC23C A02 11 14 AD03 A02 11 14 AD03 A1 I/O2 A1 I/O2 A19 9 A03 10 15 AD01 A03 10 15 AD01 A2 I/O3 A2 I/O3 8 A19M A04 9 17 AD00 A04 9 17 AD00 A3 I/O4 A3 I/O4 Addr_IO 10 A05 8 18 AD02 A05 8 18 AD02 A4 I/O5 A4 I/O5 C A06 7 19 AD04 A06 7 19 AD04 C A5 I/O6 A5 I/O6 A07 6 20 AD06 A07 6 20 AD06 74AC32 A6 I/O7 A6 I/O7 IC23A A08 5 21 AD07 A08 5 21 AD07 A7 I/O8 A7 I/O8 A18 1 A09 27 A09 27 A8 A8 3 A18M A10 26 A10 26 A9 A9 Addr_IO 2 A11 23 A11 23 A10 A10 A12 25 A12 25 A11 A11 A13 4 A13 4 74AC32 A12 A12 IC23D A14 28 1 A19M A14 28 1 A19M A13 NC A13 NC A16 12 A15 3 A15 3 A14 A14 11 A16M A16M 31 A16M 31 A15 A15 Addr_IO 13 A17M2 VCC A17M 2 VCC A16 A16 32 32 VCC VCC #CSRAM0 22 #CSRAM1 22 74AC32 CS1 CS1 N/A18 30 N/A18 30 CS2 CS2 #RD 24 #RD 24 OE OE #WRL 29 16 #WRL 29 16 WE VSS WE VSS TC551001CP-55 GND TC551001CP-55 GND
IC7 FLASH AD00 9 8D AD01 8 7D IC5 AD02 7 12 A00 6D 8Q A01 11 15 AD00 AD03 6 13 A01 A0 DQ0 5D 7Q A02 10 17 AD01 AD04 5 14 A02 A1 DQ1 4D 6Q A03 9 19 AD02 AD05 4 15 A03 A2 DQ2 3D 5Q A04 8 21 AD03 B AD06 3 16 A04 A3 DQ3 B 2D 4Q A05 7 24 AD04 AD07 2 17 A05 A4 DQ4 1D 3Q A06 6 26 AD05 18 A06 A5 DQ5 2Q A07 5 28 AD06 ALE 11 19 A07 A6 DQ6 C 1Q A08 4 30 AD07 1 A7 DQ7 OC A09 42 A8 A10 41 16 AD08 GND SN74HCT573M A9 DQ8 A11 40 18 AD09 A10 DQ9 A12 39 20 AD10 A11 DQ10 A13 38 22 AD11 IC8 A12 DQ11 A14 37 25 AD12 AD08 9 A13 DQ12 8D A15 36 27 AD13 AD09 8 A14 DQ13 7D A16M 35 29 AD14 AD10 7 12 A08 A15 DQ14 6D 8Q A17M 34 31 AD15/A00 AD11 6 13 A09 A16 DQ15/A-1 5D 7Q AD12 5 14 A10 4D 6Q #CSFLASH 12 AD13 4 15 A11 #CE 3D 5Q #RD 14 1 A18M AD14 3 16 A12 #OE NC 2D 4Q BYTE 33 3 AD15 2 17 A13 #BYTE NC 1D 3Q R70 #WRL 43 18 A14 #WE 2Q VCC 10K 23 ALE 11 19 A15 VCC VCC C 1Q RY/BY 2 1 RY/#BY OC 32 GND #RST 44 13 GND SN74HCT573M #RESET GND MBM29F200BA-70PF GND AD[0..15]
A[16..23]
A AD[0..15] CSRAM[0..1] A
A[16..23] CSFLASH
BusCtrl[0..7] BYTE Title Addr_IO AD15/A00 DevKit16 Mainboard - Memories Siz e Number Revision A4 Ver. 1 3 Date: 11-Nov-1999 Sheet of File: D:\Devkit16v13.Ddb Drawn By: 1 2 34
98 1 2 3 4
D D Audioamplifer + speaker
C61 10uF/10V R63 VCC 1K2
R61 6 IC22
100K 2 1 8 LM386 C63 - J17 250uF/10V JUMPER2 AudioIn V
P1 R60 GND 5 SP1 10K 10K 1 KPB1220 3 G B + C62 GND 50K 4 7 C60 K16 4K7 HEADER 2 1 GND R62 AUDIO OUT 2 GND 10 GND GND
GND
C C
RX1 TX1 CAN Interface RX0
TX0
P3 47K
GND
GND J25 GND IC12 K2 1 2 TX0 1 7 5 3 4 TxD CANH RX0 4 9 J26 5 6 RxD INT4 1 4 7 8 5 8 JUMPER2 9 10 Vref 8 3 Rs VCC HEADER 5X2 VCC 3 7 VCC 2 6 2 B GND CANL B 6 IC24A PCA 82C250T 1 1 J28 3 1 INT4 VCC CAN 9 V 90 2 JUMPER2 74HCT32 GND
GND J24 GND IC11 K3 1 2 TX1 1 7 5 3 4 TxD CANH RX1 4 9 J27 5 6 RxD INT5 1 4 7 8 5 8 JUMPER2 9 10 Vref 8 3 Rs VCC HEADER 5X2 VCC 3 7 VCC 2 6 2 GND CANL 6 PCA 82C250T 1
CAN 9 V 90
P4 47K
A A GND
Title DevKit16 Mainboard - CAN and sound IF Size NumberVer. 1 Revision A4 3 Date: 17-Jan-2000 Sheet of File: D:\Devkit16v13.Ddb Drawn By: 1 2 34
99