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Rigorous Engineering for Hardware Edinburgh Research Explorer Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process Citation for published version: Nienhuis, K, Joannou, A, Bauereiss, T, Fox, A, Roe, M, Campbell, B, Naylor, M, Norton, RM, Moore, SW, Neumann, PG, Stark, I, Watson, RNM & Sewell, P 2020, Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process. in 2020 IEEE Symposium on Security and Privacy (SP). Institute of Electrical and Electronics Engineers (IEEE), San Francisco, CA, USA, pp. 1003-1020, 41st IEEE Symposium on Security and Privacy, San Francisco, California, United States, 18/05/20. https://doi.org/10.1109/SP40000.2020.00055 Digital Object Identifier (DOI): 10.1109/SP40000.2020.00055 Link: Link to publication record in Edinburgh Research Explorer Document Version: Peer reviewed version Published In: 2020 IEEE Symposium on Security and Privacy (SP) General rights Copyright for the publications made accessible via the Edinburgh Research Explorer is retained by the author(s) and / or other copyright owners and it is a condition of accessing these publications that users recognise and abide by the legal requirements associated with these rights. Take down policy The University of Edinburgh has made every reasonable effort to ensure that Edinburgh Research Explorer content complies with UK legislation. If you believe that the public display of this file breaches copyright please contact [email protected] providing details, and we will remove access to the work immediately and investigate your claim. Download date: 01. Oct. 2021 Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process Kyndylan Nienhuis∗, Alexandre Joannou∗, Thomas Bauereiss∗, Anthony Foxy, Michael Roe∗, Brian Campbellz, Matthew Naylor∗, Robert M. Norton∗, Simon W. Moore∗, Peter G. Neumannx, Ian Starkz, Robert N. M. Watson∗, and Peter Sewell∗ ∗University of Cambridge yARM Limited zUniversity of Edinburgh xSRI International Abstract—The root causes of many security vulnerabilities vide only coarse-grained memory protection, via the memory include a pernicious combination of two problems, often regarded management unit (MMU). This is hard to change: the mass of as inescapable aspects of computing. First, the protection mech- legacy C/C++ code makes it infeasible to migrate everything anisms provided by the mainstream processor architecture and C/C++ language abstractions, dating back to the 1970s and be- to a type-safe language, or to radically change hardware fore, provide only coarse-grain virtual-memory-based protection. architectures, but introducing fine-grained memory protection Second, mainstream system engineering relies almost exclusively in software, e.g. with bounds-checking, is often too inefficient. on test-and-debug methods, with (at best) prose specifications. Second, mainstream systems are typically developed using These methods have historically sufficed commercially for much test-and-debug engineering methods. While this often suffices of the computer industry, but they fail to prevent large numbers of exploitable bugs, and the security problems that this causes to build systems that are sufficiently functionally correct under are becoming ever more acute. normal use, it fails to build secure systems: it is easy to miss In this paper we show how more rigorous engineering methods a small mistake that manifests itself only in a corner case, but can be applied to the development of a new security-enhanced attackers will actively try to find these, and one small bug can processor architecture, with its accompanying hardware im- compromise the entire system. plementation and software stack. We use formal models of the complete instruction-set architecture (ISA) at the heart of CHERI is an ongoing research project that addresses the the design and engineering process, both in lightweight ways first problem with hardware support for fine-grained memory that support and improve normal engineering practice – as protection and scalable software compartmentalisation, aiming documentation, in emulators used as a test oracle for hardware to provide practically deployable performance and compati- and for running software, and for test generation – and for formal bility [5]–[7]. CHERI achieves this by extending commodity verification. We formalise key intended security properties of the design, and establish that these hold with mechanised proof. This architectures with new security mechanisms, and adapting a is for the same complete ISA models (complete enough to boot conventional software stack to make use of these. operating systems), without idealisation. This paper addresses the second problem: we show how We do this for CHERI, an architecture with hardware capabil- more rigorous engineering methods can be used to improve as- ities that supports fine-grained memory protection and scalable surance and complement traditional methods, using the CHERI secure compartmentalisation, while offering a smooth adoption path for existing software. CHERI is a maturing research project as a whole as a testbench for this. These include architecture, developed since 2010, with work now underway both lightweight methods – formal specification and testing on an Arm industrial prototype to explore its possible adoption methods that provide engineering and assurance benefits for in mass-market commercial processors. The rigorous engineering hardware and software engineering without the challenges of work described here has been an integral part of its development full formal verification – and more heavyweight machine- to date, enabling more rapid and confident experimentation, and boosting confidence in the design. checked proof, establishing very high confidence that the architecture design provides specific security properties. I. INTRODUCTION Despite decades of research, memory safety bugs are still A. The CHERI Context responsible for many security vulnerabilities [1]. Microsoft The CHERI design is based on two principles. The principle estimates that 70% of the vulnerabilities they have patched be- of least privilege [8] says that each part of a program should tween 2006 and 2018 are caused by memory safety issues [2], run only with the permissions it needs to function. For exam- MITRE considers classic buffer overflows as the third most ple, a conventional C/C++ program implicitly uses permission dangerous software error [3], and high-profile memory-safety to its entire memory region for accesses via a pointer, making bugs such as Heartbleed [4] have become common. it vulnerable to buffer overflows, but in CHERI it can be There are two fundamental problems here. First, mainstream limited to the permission to access the pointed-to object. On hardware architectures and C/C++ language abstractions pro- a larger scale, the JavaScript execution engine of a browser does not need access to the encryption keys used in SSL B. The Problems with Traditional Engineering Methods connections, so by restricting its permissions one can ensure that even a compromised JavaScript engine cannot access CHERI-MIPS was initially developed using traditional en- these keys. The principle of intentional use states that when gineering methods: the security properties that the architecture a program performs an action, it should explicitly state which is intended to enforce were described in prose; the architecture permissions it uses to authorise that action. This helps avoid was described in prose and pseudocode; and the hardware the confused deputy problem [9]. For example, an operating implementation of the architecture was validated with hand- system (OS) may need to hold permission to access the entirety written tests. This led to the following problems, often ac- of a user process (e.g. for paging), but when that process makes cepted as inescapable aspects of normal practice. a read() system call, passing a pointer to a user-space buffer, First, the prose and pseudocode architecture description CHERI lets the relevant OS code to use the more restricted was not executable as a test oracle, to check the hardware permission to just that buffer. The CHERI design involves no implementation behaviour against, or as an emulator, to run lookup or search for permissions, which is important both to software above. Hardware validation tests therefore required embody this principle and for performance. manual curation of their intended outcomes, so tests could not be automatically generated, and it was not possible to These principles are realised in CHERI with hardware rerun software tests after changes in the architecture until the capabilities: to access memory, one needs to possess a ca- hardware implementation was updated. pability that authorises that access. A capability augments Second, while the designers had strong intuitions about the the usual virtual address of a language-level pointer with security properties the architecture should provide, their prose bounds that specify the memory region it relates to, and statements were inevitably less precise than they could be, and with permission bits that specify what kind of actions it can omitted crucial details. This led to unnecessary confusion in authorise. To distinguish capabilities from other data, CHERI internal discussions of (for example) the concepts of capability uses tagged memory, one bit for each capability-sized and provenance and monotonicity, central to the design, and made
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