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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 6)

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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 6) UCAM-CL-TR-907 Technical Report ISSN 1476-2986 Number 907 Computer Laboratory Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 6) Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Robert Norton, Stacey Son, Hongyan Xia April 2017 15 JJ Thomson Avenue Cambridge CB3 0FD United Kingdom phone +44 1223 763500 http://www.cl.cam.ac.uk/ c 2017 Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Robert Norton, Stacey Son, Hongyan Xia, SRI International Approved for public release; distribution is unlimited. Sponsored by the Defense Advanced Research Projects Agency (DARPA) and the Air Force Research Laboratory (AFRL), under contracts FA8750-10-C-0237 (“CTSRD”) and FA8750-11-C-0249 (“MRC2”) as part of the DARPA CRASH and DARPA MRC research programs. The views, opinions, and/or findings contained in this report are those of the authors and should not be interpreted as representing the official views or policies, either expressed or implied, of the Department of Defense or the U.S. Government. Additional support was received from St John’s College Cambridge, the Google SOAAP Focused Research Award, the RCUK’s Horizon Digital Economy Research Hub Grant (EP/G065802/1), the EPSRC REMS Programme Grant (EP/K008528/1), the EPSRC Impact Acceleration Account (EP/K503757/1), the Isaac Newton Trust, the UK Higher Education Innovation Fund (HEIF), Thales E-Security, ARM Ltd, and HP Enterprise. Technical reports published by the University of Cambridge Computer Laboratory are freely available via the Internet: http://www.cl.cam.ac.uk/techreports/ ISSN 1476-2986 Abstract This technical report describes CHERI ISAv6, the sixth version of the Capability Hardware Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA)1 being developed by SRI International and the University of Cambridge. This design captures seven years of research, development, experimentation, refinement, formal analysis, and validation through hardware and software implementation. CHERI ISAv6 is a substantial enhancement to prior ISA versions: it introduces support for kernel-mode compartmentalization, jump-based rather than exception-based domain transition, architecture-abstracted and efficient tag restoration, and more efficient generated code. A new chapter addresses potential applications of the CHERI model to the RISC-V and x86-64 ISAs, previously described relative only to the 64-bit MIPS ISA. CHERI ISAv6 better explains our design rationale and research methodology. CHERI is a hybrid capability-system architecture that adds new capability-system primi- tives to a commodity 64-bit RISC ISA enabling software to efficiently implement fine-grained memory protection and scalable software compartmentalization. Design goals have included incremental adoptability within current ISAs and software stacks, low performance overhead for memory protection, significant performance improvements for software compartmentaliza- tion, formal grounding, and programmer-friendly underpinnings. Throughout, we have focused on providing strong and efficient architectural foundations for the principles of least privilege and intentional use in the execution of software at multiple levels of abstraction, preventing and mitigating vulnerabilities. The CHERI system architecture purposefully addresses known performance and robust- ness gaps in commodity ISAs that hinder the adoption of more secure programming models centered around the principle of least privilege. To this end, CHERI blends traditional paged virtual memory with an in-address-space capability model that includes capability registers, capability instructions, and tagged memory. CHERI builds on C-language fat-pointer litera- ture: its capabilities describe fine-grained regions of memory and can be substituted for data or code pointers in generated code, protecting data and also improving control-flow robustness. Strong capability integrity and monotonicity properties allow the CHERI model to express a va- riety of protection properties, from enforcing valid C-language pointer provenance and bounds checking to implementing the isolation and controlled communication structures required for software compartmentalization. CHERI’s hybrid capability-system approach, inspired by the Capsicum security model, al- lows incremental adoption of capability-oriented design: software implementations that are more robust and resilient can be deployed where they are most needed, while leaving less criti- cal software largely unmodified, but nevertheless suitably constrained to be incapable of having adverse effects. Potential deployment scenarios include low-level software Trusted Computing Bases (TCBs) such as separation kernels, hypervisors, and operating-system kernels, as well as userspace TCBs such as language runtimes and web browsers. Likewise, we see early-use scenarios (such as data compression, protocol parsing, and image processing) that relate to particularly high-risk software libraries, which are concentrations of both complex and histori- cally vulnerability-prone code exposed to untrustworthy data sources, while leaving containing applications unchanged. 1We have attempted to avoid confusion among three rather different uses of the word ‘architecture’. The ISA specifies the interface between hardware and software, rather than describing either the (micro-)architecture of a particular hardware prototype, or laying out the total-system hardware-software architecture. 3 Acknowledgments The authors of this report thank other members of the CTSRD and MRC2 teams, our past and current research collaborators at SRI and Cambridge, as well as colleagues at other institutions who have provided invaluable feedback and continuing support throughout this work: Ross J. Anderson Graeme Barnes Hadrien Barral Stuart Biles Matthias Boettcher David Brazdil Ruslan Bukin Brian Campbell Gregory Chadwick James Clarke Serban Constantinescu Chris Dalton Nirav Dave Lawrence Esswood Anthony Fox Paul J. Fox Paul Gotch Richard Grisenthwaite Khilan Gudka Jong Hun Han Andy Hopper Alex Horsman Asif Khan Myron King Chris Kitching Wojciech Koszek Patrick Lincoln Anil Madhavapeddy Ilias Marinos A. Theodore Markettos Tim Marsland Alfredo Mazzinghi Ed Maste Kayvan Memarian Dejan Milojicic Andrew W. Moore Will Morland Alan Mujumdar Prashanth Mundkur Edward Napierala Kyndylan Nienhuis Philip Paeps Lucian Paul-Trifu Alex Richardson Colin Rothwell John Rushby Hassen Saidi Hans Petter Selasky Peter Sewell Muhammad Shahbaz Lee Smith Ian Stark Andrew Turner Richard Uhler Munraj Vadera Jacques Vidrine Philip Withnall Bjoern A. Zeeb The CTSRD team also thanks past and current members of its external oversight group for significant support and contributions: Lee Badger Simon Cooper Rance DeLong Jeremy Epstein Virgil Gligor Li Gong Mike Gordon Steven Hand Andrew Herbert Warren A. Hunt Jr. Doug Maughan Greg Morrisett Brian Randell Kenneth F. Shotting Joe Stoy Tom Van Vleck Samuel M. Weber We would also like to acknowledge the late David Wheeler and Paul Karger, whose conver- sations with the authors about the CAP computer and capability systems contributed to our thinking on CHERI. Finally, we are grateful to Howie Shrobe, MIT professor and past DARPA CRASH and MRC program manager, who has offered both technical insight and support throughout this work. We are also grateful to Robert Laddaga and Stu Wagner, who succeeded Howie in overseeing the CRASH program, to John Launchbury, DARPA I2O office director, Dale Waters, DARPA AEO office director, and to Daniel Adams and Laurisa Goergen, SETAs supporting the CRASH and MRC programs. 4 Contents 1 Introduction 13 1.1 CHERI Design Goals . 14 1.2 The CHERI Protection Model . 16 1.3 The CHERI-MIPS ISA . 17 1.4 CHERI ISA Version History . 20 1.5 Changes in CHERI ISAv6 - 1.20 . 22 1.6 Document Structure . 25 1.7 Publications . 26 2 The CHERI Protection Model 29 2.1 Underlying Principles . 29 2.2 CHERI Capabilities: Strong Protection for Pointers . 30 2.3 Architectural Capabilities . 31 2.3.1 Tags for Pointer Integrity and Provenance . 33 2.3.2 Bounds on Pointers . 33 2.3.3 Permissions on Pointers . 34 2.3.4 Capability Monotonicity via Guarded Manipulation . 34 2.3.5 Sealed Capabilities . 35 2.3.6 Capability Object Types . 35 2.3.7 Sealed Capability Invocation . 36 2.3.8 Capability Flow Control . 36 2.3.9 Capability Compression . 38 2.3.10 Hybridization with Integer Pointers . 38 2.3.11 Hybridization with Virtual Addressing . 38 2.3.12 Hybridization with Architectural Privilege . 39 2.3.13 Failure Modes and Exceptions . 40 2.3.14 Capability Revocation . 40 2.4 Software Protection and Security Using CHERI . 42 2.4.1 C/C++ Language Support . 42 2.4.2 Protecting Non-Pointer Types . 44 2.4.3 Isolation, Controlled Communication, and Compartmentalization . 45 2.4.4 Source-Code and Binary Compatibility . 47 2.4.5 Code Generation and ABIs . 47 2.4.6 Operating-System Support . 48 5 3 Mapping the CHERI Protection Model into Architecture 51 3.1 Design Goals . 51 3.2 A Hybrid Capability-System Architecture . 53 3.3 The CHERI Software Stack . 54 3.4 Architectural Goals . 56 3.5 Capability Model . 57 3.5.1 Capabilities are for Compilers . 57 3.5.2 Capabilities . 58 3.5.3 Capability Registers . 58 3.5.4 Memory Model . 60 3.5.5 Local Capabilities and Revocation . 61 3.5.6 Architectural Privilege . 61 3.5.7 Traps, Interrupts, and Exception Handling . 63 3.5.8 Tagged Memory . 63 3.5.9 Capability Instructions . 64 3.5.10 Object Capabilities . 64 3.5.11 Peripheral Devices . 65 3.6 Deep Versus Surface Design Choices . 66 4 The CHERI-MIPS Instruction-Set Architecture 69 4.1 Architectural Capabilities . 69 4.1.1 Tag Bit . 70 4.1.2 Sealed Bit . 70 4.1.3 Permission Bits . 71 4.1.4 User-Defined Permission Bits . 71 4.1.5 Object Type . 71 4.1.6 Offset . 71 4.1.7 Base . 71 4.1.8 Length . 72 4.2 Capability Permissions . 72 4.3 The Capability Register File . 73 4.3.1 Capability Register Conventions / Application Binary Interface (ABI) .
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