SGI™ Onyx® 3000 Series Graphics System Hardware Owner's Guide
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(12) United States Patent (10) Patent No.: US 8,862,870 B2 Reddy Et Al
USOO886287OB2 (12) United States Patent (10) Patent No.: US 8,862,870 B2 Reddy et al. (45) Date of Patent: Oct. 14, 2014 (54) SYSTEMS AND METHODS FOR USPC .......... 713/152–154, 168, 170; 709/223, 224, MULTI-LEVELTAGGING OF ENCRYPTED 709/225 ITEMIS FOR ADDITIONAL SECURITY AND See application file for complete search history. EFFICIENT ENCRYPTED ITEM (56) References Cited DETERMINATION U.S. PATENT DOCUMENTS (75) Inventors: Anoop Reddy, Santa Clara, CA (US); 5,867,494 A 2/1999 Krishnaswamy et al. Craig Anderson, Santa Clara, CA (US) 5,909,559 A 6, 1999 SO (73) Assignee: Citrix Systems, Inc., Fort Lauderdale, (Continued) FL (US) FOREIGN PATENT DOCUMENTS (*) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 CN 1478348 A 2, 2004 U.S.C. 154(b) by 0 days. EP 1422.907 A2 5, 2004 (Continued) (21) Appl. No.: 13/337.735 OTHER PUBLICATIONS (22) Filed: Dec. 27, 2011 Australian Examination Report on 200728.1083 dated Nov.30, 2010. (65) Prior Publication Data (Continued) US 2012/O17387OA1 Jul. 5, 2012 Primary Examiner — Abu Sholeman (74) Attorney, Agent, or Firm — Foley & Lardner LLP: Related U.S. Application Data Christopher J. McKenna (60) Provisional application No. 61/428,138, filed on Dec. (57) ABSTRACT 29, 2010. The present disclosure is directed towards systems and meth ods for performing multi-level tagging of encrypted items for (51) Int. Cl. additional security and efficient encrypted item determina H04L 9M32 (2006.01) tion. A device intercepts a message from a server to a client, H04L 2L/00 (2006.01) parses the message and identifies a cookie. -
The Quadrics Network (Qsnet): High-Performance Clustering Technology
Proceedings of the 9th IEEE Hot Interconnects (HotI'01), Palo Alto, California, August 2001. The Quadrics Network (QsNet): High-Performance Clustering Technology Fabrizio Petrini, Wu-chun Feng, Adolfy Hoisie, Salvador Coll, and Eitan Frachtenberg Computer & Computational Sciences Division Los Alamos National Laboratory ¡ fabrizio,feng,hoisie,scoll,eitanf ¢ @lanl.gov Abstract tegration into large-scale systems. While GigE resides at the low end of the performance spectrum, it provides a low-cost The Quadrics interconnection network (QsNet) con- solution. GigaNet, GSN, Myrinet, and SCI add programma- tributes two novel innovations to the field of high- bility and performance by providing communication proces- performance interconnects: (1) integration of the virtual- sors on the network interface cards and implementing differ- address spaces of individual nodes into a single, global, ent types of user-level communication protocols. virtual-address space and (2) network fault tolerance via The Quadrics network (QsNet) surpasses the above inter- link-level and end-to-end protocols that can detect faults connects in functionality by including a novel approach to and automatically re-transmit packets. QsNet achieves these integrate the local virtual memory of a node into a globally feats by extending the native operating system in the nodes shared, virtual-memory space; a programmable processor in with a network operating system and specialized hardware the network interface that allows the implementation of intel- support in the network interface. As these and other impor- ligent communication protocols; and an integrated approach tant features of QsNet can be found in the InfiniBand speci- to network fault detection and fault tolerance. Consequently, fication, QsNet can be viewed as a precursor to InfiniBand. -
High Performance Network and Channel-Based Storage
High Performance Network and Channel-Based Storage Randy H. Katz Report No. UCB/CSD 91/650 September 1991 Computer Science Division (EECS) University of California, Berkeley Berkeley, California 94720 (NASA-CR-189965) HIGH PERFORMANCE NETWORK N92-19260 AND CHANNEL-BASED STORAGE (California Univ.) 42 p CSCL 098 Unclas G3/60 0073846 High Performance Network and Channel-Based Storage Randy H. Katz Computer Science Division Department of Electrical Engineering and Computer Sciences University of California Berkeley, California 94720 Abstract: In the traditional mainframe-centered view of a computer system, storage devices are coupled to the system through complex hardware subsystems called I/O channels. With the dramatic shift towards workstation-based com- puting, and its associated client/server model of computation, storage facilities are now found attached to file servers and distributed throughout the network. In this paper, we discuss the underlying technology trends that are leading to high performance network-based storage, namely advances in networks, storage devices, and I/O controller and server architectures. We review several commercial systems and research prototypes that are leading to a new approach to high performance computing based on network-attached storage. Key Words and Phrases: High Performance Computing, Computer Networks, File and Storage Servers, Secondary and Tertiary Storage Device 1. Introduction The traditional mainframe-centered model of computing can be characterized by small numbers of large-scale mainframe computers, with shared storage devices attached via I/O channel hard- ware. Today, we are experiencing a major paradigm shift away from centralized mainframes to a distributed model of computation based on workstations and file servers connected via high per- formance networks. -
HIPPI Developments for CERN Experiments A
VERSION OF: 5-Feb-98 10:15 HIPPI Developments for CERN experiments A. van Praag ,T. Anguelov, R.A. McLaren, H.C. van der Bij, CERN, Geneva, Switzerland. J. Bovier, P. Cristin Creative Electronic Systems, Geneva, Switzerland. M. Haben, P. Jovanovic, I. Kenyon, R. Staley University of Birmingham, Birmingham, U.K. D. Cunningham, G. Watson Hewlett Packard Laboratories, Bristol, U.K. B. Green, J. Strong Royal Hollaway and Bedford New College, U.K. Abstract HIPPI Standard, fast, simple, inexpensive; is this not a contradiction in terms? The High-Performance Parallel We have decided to use the High Performance Parallel Interface (HIPPI) is a new proposed ANSI standard, using a Interface (HIPPI) to implement these links. The HIPPI minimal protocol and providing 100 Mbyte/sec transfers over specification was started in the Los Alamos laboratory in distances up to 25 m. Equipment using this standard is 1989 and is now a proposed ANSI standard (X3T9/88-127, offered by a growing number of computer manufacturers. A X3T9.3/88-23, HIPPI PH) [1,2]. This standard allows commercially available HIPPI chipset allows low cost 100 Mbyte/sec synchronous data transfers between a "Source" implementations. In this article a brief technical introduction and a "Destination". Seen from the lowest level upwards the to the HIPPI will be given, followed by examples of planned HIPPI specification proposes a logical framing hierarchy applications in High Energy Physics experiments including where the smallest unit of data to be transferred, called a the present developments involving CERN: a detector "burst" has a standard size of 256 words of 32 bit or optional emulator, a risc processor based VME connection, a long 64 bit (Fig. -
PC Hardware Contents
PC Hardware Contents 1 Computer hardware 1 1.1 Von Neumann architecture ...................................... 1 1.2 Sales .................................................. 1 1.3 Different systems ........................................... 2 1.3.1 Personal computer ...................................... 2 1.3.2 Mainframe computer ..................................... 3 1.3.3 Departmental computing ................................... 4 1.3.4 Supercomputer ........................................ 4 1.4 See also ................................................ 4 1.5 References ............................................... 4 1.6 External links ............................................. 4 2 Central processing unit 5 2.1 History ................................................. 5 2.1.1 Transistor and integrated circuit CPUs ............................ 6 2.1.2 Microprocessors ....................................... 7 2.2 Operation ............................................... 8 2.2.1 Fetch ............................................. 8 2.2.2 Decode ............................................ 8 2.2.3 Execute ............................................ 9 2.3 Design and implementation ...................................... 9 2.3.1 Control unit .......................................... 9 2.3.2 Arithmetic logic unit ..................................... 9 2.3.3 Integer range ......................................... 10 2.3.4 Clock rate ........................................... 10 2.3.5 Parallelism ......................................... -
Lecture 12: I/O: Metrics, a Little Queuing Theory, and Busses
Lecture 12: I/O: Metrics, A Little Queuing Theory, and Busses Professor David A. Patterson Computer Science 252 Fall 1996 DAP.F96 1 Review: Disk Device Terminology Disk Latency = Queuing Time + Seek Time + Rotation Time + Xfer Time Order of magnitude times for 4K byte transfers: Seek: 12 ms or less Rotate: 4.2 ms @ 7200 rpm (8.3 ms @ 3600 rpm ) Xfer: 1 ms @ 7200 rpm (2 ms @ 3600 rpm) DAP.F96 2 Review: R-DAT Technology 2000 RPM Four Head Recording Helical Recording Scheme Tracks Recorded ±20° w/o guard band Read After Write Verify DAP.F96 3 Review: Automated Cartridge System STC 4400 8 feet 10 feet 6000 x 0.8 GB 3490 tapes = 5 TBytes in 1992 $500,000 O.E.M. Price 6000 x 20 GB D3 tapes = 120 TBytes in 1994 1 Petabyte (1024 TBytes) in 2000 DAP.F96 4 Review: Storage System Issues • Historical Context of Storage I/O • Secondary and Tertiary Storage Devices • Storage I/O Performance Measures • A Little Queuing Theory • Processor Interface Issues • I/O Buses • Redundant Arrarys of Inexpensive Disks (RAID) • ABCs of UNIX File Systems • I/O Benchmarks • Comparing UNIX File System Performance DAP.F96 5 Disk I/O Performance 300 Response Metrics: Time (ms) Response Time Throughput 200 100 0 0% 100% Throughput (% total BW) Queue Proc IOC Device Response time = Queue + Device Service time DAP.F96 6 Response Time vs. Productivity • Interactive environments: Each interaction or transaction has 3 parts: – Entry Time: time for user to enter command – System Response Time: time between user entry & system replies – Think Time: Time from response until user -
Security Hardened Remote Terminal Units for SCADA Networks
University of Louisville ThinkIR: The University of Louisville's Institutional Repository Electronic Theses and Dissertations 5-2008 Security hardened remote terminal units for SCADA networks. Jeff Hieb University of Louisville Follow this and additional works at: https://ir.library.louisville.edu/etd Recommended Citation Hieb, Jeff, "Security hardened remote terminal units for SCADA networks." (2008). Electronic Theses and Dissertations. Paper 615. https://doi.org/10.18297/etd/615 This Master's Thesis is brought to you for free and open access by ThinkIR: The University of Louisville's Institutional Repository. It has been accepted for inclusion in Electronic Theses and Dissertations by an authorized administrator of ThinkIR: The University of Louisville's Institutional Repository. This title appears here courtesy of the author, who has retained all other copyrights. For more information, please contact [email protected]. SECURITY HARDENED REMOTE TERMINAL UNITS FOR SCADA NETWORKS By Jeffrey Lloyd Hieb B.S., Furman University, 1992 B.A., Furman University, 1992 M.S., University of Louisville, 2004 A Dissertation Submitted to the Faculty of the Graduate School of the University of Louisville in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy Department of Computer Science and Computer Engineering J. B. Speed School of Engineering University of Louisville Louisville, Kentucky May 2008 SECURITY HARDENED REMOTE TERMINAL UNITS FOR SCADA NETWORKS By Jeffrey Lloyd Hieb B.S., Furman University, 1992 B.A., Furman University, 1992 M.S., University of Louisville, 2004 A Dissertation Approved on February 26, 2008 By the following Dissertation Committee members Dr. James H. Graham, Dissertation Director Dr. -
ISO/IEC JTC 1/SC 25 N 4Chi008 Date: 2004-06-22
ISO/IEC JTC 1/SC 25 N 4Chi008 Date: 2004-06-22 ISO/IEC JTC 1/SC 25 INTERCONNECTION OF INFORMATION TECHNOLOGY EQUIPMENT Secretariat: Germany (DIN) DOC TYPE: Administrative TITLE: Status of projects of SC25/WG 4, Chitose, Japan, 2004-06-22/24. SOURCE: ISO/IEC JTC 1/SC 25/WG 4 Convener PROJECT: All projects of SC 25/WG 4 STATUS: Agenda ACTION ID: FYI DUE DATE: n/a REQUESTED: For information ACTION MEDIUM: Open DISTRIBUTION: ITTF, JTC 1 Secretariat P-, L-, O-Members of SC 25 No of Pages: 08 (including cover) Page 1 of 8 Status of projects of WG 4, Chitose, Japan, 2004-06-22/24 6 Project 1.25.13.01.XX - Channel Interface Specifications: Fibre Distributed Data Interface (FDDI) 6.1. Project 1.25.13.01.03 - FDDI - Part 1: Physical Layer Protocol (PHY) [ISO 9314-1:1989] no action required 6.2. Project 1.25.13.01.04 - FDDI - Part 2: Media Access Control (MAC) [ISO 9314-2:1989] - - no action required 6.3. Project 1.25.13.01.05 - FDDI - Part 3: Physical Layer Medium Dependent (PMD) [ISO/IEC 9314-3:1990] no action required 6.4. Project 1.25.13.01.06 - FDDI - Part 4: Single-Mode Fibre Physical Layer Medium Dependent (SMF-PMD) [ISO/IEC 9314-4:1999] -- no action required 6.5. Project 1.25.13.01.07 - FDDI - Part 5: Hybrid Ring Control (HRC) [ISO/IEC 9314- 5:1995] no action required 6.6. Project 1.25.13.01.08 - FDDI - Part 6: Station Management (SMT) [ISO/IEC 9314- 6:1998] no action required 6.7. -
Origin™ and Onyx2™ Theory of Operations Manual
Origin™ and Onyx2™ Theory of Operations Manual Document Number 007-3439-002 CONTRIBUTORS Written by Joseph Heinrich Illustrated by Dan Young and Cheri Brown Production by Linda Rae Sande Engineering contributions are listed in the References and Source Material. St Peter’s Basilica image courtesy of ENEL SpA and InfoByte SpA. Disk Thrower image courtesy of Xavier Berenguer, Animatica. © 1997, Silicon Graphics, Inc.— All Rights Reserved The contents of this document may not be copied or duplicated in any form, in whole or in part, without the prior written permission of Silicon Graphics, Inc. RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure of the technical data contained in this document by the Government is subject to restrictions as set forth in subdivision (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS 52.227-7013 and/or in similar or successor clauses in the FAR, or in the DOD or NASA FAR Supplement. Unpublished rights reserved under the Copyright Laws of the United States. Contractor/manufacturer is Silicon Graphics, Inc., 2011 N. Shoreline Blvd., Mountain View, CA 94043-1389. Silicon Graphics, the Silicon Graphics logo, and CHALLENGE are registered trademarks and IRIX, Origin, Origin200, Origin2000, Onyx2, and POWER CHALLENGE are trademarks of Silicon Graphics, Inc. MIPS and R8000 are registered trademarks and R10000 is a trademark of MIPS Technologies, Inc. CrayLink is a trademark of Cray Research, Inc. Origin™ and Onyx2™ Theory of Operations Manual Document Number 007-3439-002 Contents List of Figures vii List of Tables ix About This Guide xi References and Source Material xiii Typographical Conventions xiv Italic xiv Bold Text xiv For More Information xiv Comments and Corrections xiv 1. -
The HIPPI Protocol
The HIPPI Protocol Jim Bell ( [email protected]) Abstract The High-Performance Peripheral Interface (HIPPI) protocol was designed to facilitate high-speed communications between very high-performance computers (such as supercomputers), and thereby to attempt to meet their I/O requirements. This paper describes the HIPPI protocol in some depth, then surveys a few topics of advancement and extension of HIPPI. Table Of Contents z Abstract z Overview of HIPPI { HIPPI-PH (Physical Layer) { HIPPI-FP (Framing Protocol) { HIPPI-SC (Switch Control) { Mapping HIPPI to Other Protcols z HIPPI's Origin z Current Topics in HIPPI { Serial HIPPI { High Speed SONET Extensions { HIPPI Connection Management { Real-world Uses of HIPPI z Annotated Bibliography z Glossary List Of Figures z Suite of HIPPI Protocol Documents Overview of HIPPI HIPPI is a very high-speed data transfer protocol, with the following properties, features, and limitations: z Data rates of 800 or 1600 Mb/s. z Uses a 50- or 100-pair connection. (50-pair for 800 Mb/s data-rate, 100-pair for 1600 Mb/s data- rate.) The 100-pair connection is actually a set of two identical 50-pair cables. z Useful for distances up to 25 meters. (Serial-HIPPI extensions are being proposed for operation up Page 1 of 11 to 10km.) z Transfers 32 bits (for 800 Mb/s data-rate) or 64 bits (for 1600 Mb/s data-rate) in parallel. Packet format allows byte alignment. z Connection-oriented protocol. z Point-to-point connection. z Simplex (i.e., one-way data transfer) operation. z First standard in its class (data-transfer for high-performance computing environments).[1] z Designed for ease of implementation: available options are very limited. -
IT Acronyms at Your Fingertips a Quick References Guide with Over 3,000 Technology Related Acronyms
IT Acronyms at your fingertips A quick references guide with over 3,000 technology related acronyms IT Acronyms at your Fingertips We’ve all experienced it. You’re sitting in a meeting and someone spouts off an acronym. You immediately look around the table and no one reacts. Do they all know what it means? Is it just me? We’re here to help! We’ve compiled a list of over 3,000 IT acronyms for your quick reference and a list of the top 15 acronyms you need to know now. Top 15 acronyms you need to know now. Click the links to get a full definition of the acronym API, Application Programmer Interface MDM, Mobile Device Management AWS, Amazon Web Services PCI DSS, Payment Card Industry Data Security Standard BYOA, Bring Your Own Apps SaaS, Software as a Service BYOC, Bring Your Own Cloud SDN, Software Defined Network BYON, Bring Your Own Network SLA, Service Level Agreement BYOI, Bring Your Own Identity VDI, Virtual Desktop Infrastructure BYOE, Bring Your Own Encryption VM, Virtual Machine IoT, Internet of Things Quick Reference, over 3000 IT acronyms Click the links to get a full definition of the acronym Acronym Meaning 10 GbE 10 gigabit Ethernet 100GbE 100 Gigabit Ethernet 10HD busy period 10-high-day busy period 1170 UNIX 98 121 one-to-one 1xRTT Single-Carrier Radio Transmission Technology 2D barcode two-dimensional barcode Page 1 of 91 IT Acronyms at your Fingertips 3270 Information Display System 3BL triple bottom line 3-D three dimensions or three-dimensional 3G third generation of mobile telephony 3PL third-party logistics 3Vs volume, variety and velocity 40GbE 40 Gigabit Ethernet 4-D printing four-dimensional printing 4G fourth-generation wireless 7W seven wastes 8-VSB 8-level vestigial sideband A.I. -
N95- 17191
7¸¸!<i¸i¸</i¸i := ::: :::::-::: : :: -=:::::= : .::::::::::=; < ...... _.:: _ ,= ........... :::==<:::: :::: :;=::+:+ ::+::_ =:,::::: :: +:::::_.:::::+: =:::<::::=_::<:_::,: <:=:::<::::: : <:::+::::::::::::::;:<:_:::_:::::::::_::_ ................................................_:_i:_i_i_i_i_i_i_i_i_i_i_i_:_:_::_:_:::::_:_:_:;:i:i:_!:_!_:)i:_:_:i:_:_:__ i!)ji;/i N95- 17191: i:_ /: i! < :C • _ , / _J" /< :H • ;" J 5,<! :" !?,:i)i _ A SECOND GENERATION 50 Mbps VLSI LEVEL ZERO PROCESSING SYSTEM PROTOTYPE Jonathan C. Harris, Jeff Shi Nick Speciale, Toby Bennett < <i!!i_!i_ RMS Technologies, Inc. Data Systems Technologies Division Code 520.9 Code 520 !iii_ < Mission Operation and Data Systems Directorate NASA, Goddard Space Flight Center Greenbelt, MD 20771 ABSTRACT • <: • i_ili)<i/ Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division :•i >i:!?:i' (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbps) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbps performance. This paper describes the second generation LZPS prototype based upon VLSI technologies. 1. INTRODUCTION With the new Earth Observing System (EOS) era of satellites, telemetry downlink data rates will CI:: i;!ii:_ increase to 50 Mbps and beyond.