Randy Allen Corporate Vice President, Server and Workstation Division
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GPTPU: Accelerating Applications Using Edge Tensor Processing Units Kuan-Chieh Hsu and Hung-Wei Tseng University of California, Riverside {Khsu037, Htseng}@Ucr.Edu
GPTPU: Accelerating Applications using Edge Tensor Processing Units Kuan-Chieh Hsu and Hung-Wei Tseng University of California, Riverside {khsu037, htseng}@ucr.edu This paper is a pre-print of a paper in the 2021 SC, the Interna- Two decades ago, graphics processing units (GPUs) were just tional Conference for High Performance Computing, Networking, domain-specific accelerators used for shading and rendering. But Storage and Analysis. Please refer to the conference proceedings intensive research into high-performance algorithms, architectures, for the most complete version. systems, and compilers [3–12] and the availability of frameworks like CUDA [13] and OpenCL [14], have revolutionized GPUs and ABSTRACT transformed them into high-performance, general-purpose vector Neural network (NN) accelerators have been integrated into a wide- processors. We expect a similar revolution to take place with NN spectrum of computer systems to accommodate the rapidly growing accelerators—a revolution that will create general-purpose matrix demands for artificial intelligence (AI) and machine learning (ML) processors for a broader spectrum of applications. However, de- applications. NN accelerators share the idea of providing native mocratizing these NN accelerators for non-AI/ML workloads will hardware support for operations on multidimensional tensor data. require the system framework and the programmer to tackle the Therefore, NN accelerators are theoretically tensor processors that following issues: can improve system performance for any problem that uses ten- (1) The microarchitectures and instructions of NN accelerators sors as inputs/outputs. Unfortunately, commercially available NN are optimized for NN workloads, instead of general matrix/tensor accelerators only expose computation capabilities through AI/ML- algebra. -
Amd Filed: February 24, 2009 (Period: December 27, 2008)
FORM 10-K ADVANCED MICRO DEVICES INC - amd Filed: February 24, 2009 (period: December 27, 2008) Annual report which provides a comprehensive overview of the company for the past year Table of Contents 10-K - FORM 10-K PART I ITEM 1. 1 PART I ITEM 1. BUSINESS ITEM 1A. RISK FACTORS ITEM 1B. UNRESOLVED STAFF COMMENTS ITEM 2. PROPERTIES ITEM 3. LEGAL PROCEEDINGS ITEM 4. SUBMISSION OF MATTERS TO A VOTE OF SECURITY HOLDERS PART II ITEM 5. MARKET FOR REGISTRANT S COMMON EQUITY, RELATED STOCKHOLDER MATTERS AND ISSUER PURCHASES OF EQUITY SECURITIES ITEM 6. SELECTED FINANCIAL DATA ITEM 7. MANAGEMENT S DISCUSSION AND ANALYSIS OF FINANCIAL CONDITION AND RESULTS OF OPERATIONS ITEM 7A. QUANTITATIVE AND QUALITATIVE DISCLOSURE ABOUT MARKET RISK ITEM 8. FINANCIAL STATEMENTS AND SUPPLEMENTARY DATA ITEM 9. CHANGES IN AND DISAGREEMENTS WITH ACCOUNTANTS ON ACCOUNTING AND FINANCIAL DISCLOSURE ITEM 9A. CONTROLS AND PROCEDURES ITEM 9B. OTHER INFORMATION PART III ITEM 10. DIRECTORS, EXECUTIVE OFFICERS AND CORPORATE GOVERNANCE ITEM 11. EXECUTIVE COMPENSATION ITEM 12. SECURITY OWNERSHIP OF CERTAIN BENEFICIAL OWNERS AND MANAGEMENT AND RELATED STOCKHOLDER MATTERS ITEM 13. CERTAIN RELATIONSHIPS AND RELATED TRANSACTIONS AND DIRECTOR INDEPENDENCE ITEM 14. PRINCIPAL ACCOUNTANT FEES AND SERVICES PART IV ITEM 15. EXHIBITS, FINANCIAL STATEMENT SCHEDULES SIGNATURES EX-10.5(A) (OUTSIDE DIRECTOR EQUITY COMPENSATION POLICY) EX-10.19 (SEPARATION AGREEMENT AND GENERAL RELEASE) EX-21 (LIST OF AMD SUBSIDIARIES) EX-23.A (CONSENT OF ERNST YOUNG LLP - ADVANCED MICRO DEVICES) EX-23.B -
Quad-Core Catamount and R&D in Multi-Core Lightweight Kernels
Quad-core Catamount and R&D in Multi-core Lightweight Kernels Salishan Conference on High-Speed Computing Gleneden Beach, Oregon April 21-24, 2008 Kevin Pedretti Senior Member of Technical Staff Scalable System Software, Dept. 1423 [email protected] SAND Number: 2008-1725A Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000. Outline • Introduction • Quad-core Catamount LWK results • Open-source LWK • Research directions • Conclusion Going on Four Decades of UNIX Operating System = Collection of software and APIs Users care about environment, not implementation details LWK is about getting details right for scalability LWK Overview Basic Architecture Memory Management … … Policy n 1 n N tio tio Page 3 Page 3 Maker ca ca i l Libc.a Libc.a (PCT) pp ppli Page 2 Page 2 A libmpi.a A libmpi.a Page 1 Page 1 Policy Enforcer/HAL (QK) Page 0 Page 0 Privileged Hardware Physical Application Memory Virtual • POSIX-like environment Memory • Inverted resource management • Very low noise OS noise/jitter • Straight-forward network stack (e.g., no pinning) • Simplicity leads to reliability Nov 2007 Top500 Top 10 System Lightweight Kernel Compute Processors: Timeline 82% run a LWK 1990 – Sandia/UNM OS (SUNMOS), nCube-2 1991 – Linux 0.02 1993 – SUNMOS ported to Intel Paragon (1800 nodes) 1993 – SUNMOS experience used to design Puma First implementation of Portals communication architecture 1994 -
Cray XT and Cray XE Y Y System Overview
Crayyy XT and Cray XE System Overview Customer Documentation and Training Overview Topics • System Overview – Cabinets, Chassis, and Blades – Compute and Service Nodes – Components of a Node Opteron Processor SeaStar ASIC • Portals API Design Gemini ASIC • System Networks • Interconnection Topologies 10/18/2010 Cray Private 2 Cray XT System 10/18/2010 Cray Private 3 System Overview Y Z GigE X 10 GigE GigE SMW Fibre Channels RAID Subsystem Compute node Login node Network node Boot /Syslog/Database nodes 10/18/2010 Cray Private I/O and Metadata nodes 4 Cabinet – The cabinet contains three chassis, a blower for cooling, a power distribution unit (PDU), a control system (CRMS), and the compute and service blades (modules) – All components of the system are air cooled A blower in the bottom of the cabinet cools the blades within the cabinet • Other rack-mounted devices within the cabinet have their own internal fans for cooling – The PDU is located behind the blower in the back of the cabinet 10/18/2010 Cray Private 5 Liquid Cooled Cabinets Heat exchanger Heat exchanger (XT5-HE LC only) (LC cabinets only) 48Vdc flexible Cage 2 buses Cage 2 Cage 1 Cage 1 Cage VRMs Cage 0 Cage 0 backplane assembly Cage ID controller Interconnect 01234567 Heat exchanger network cable Cage inlet (LC cabinets only) connection air temp sensor Airflow Heat exchanger (slot 3 rail) conditioner 48Vdc shelf 3 (XT5-HE LC only) 48Vdc shelf 2 L1 controller 48Vdc shelf 1 Blower speed controller (VFD) Blooewer PDU line filter XDP temperature XDP interface & humidity sensor -
ADVANCED MICRO DEVICES, INC. (Exact Name of Registrant As Specified in Its Charter)
UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 FORM 8-K CURRENT REPORT Pursuant to Section 13 or 15(d) of the Securities Exchange Act of 1934 July 19, 2007 Date of Report (Date of earliest event reported) ADVANCED MICRO DEVICES, INC. (Exact name of registrant as specified in its charter) Delaware 001-07882 94-1692300 (State of Incorporation) (Commission File Number) (IRS Employer Identification Number) One AMD Place P.O. Box 3453 Sunnyvale, California 94088-3453 (Address of principal executive offices) (Zip Code) (408) 749-4000 (Registrant’s telephone number, including area code) N/A (Former Name or Former Address, if Changed Since Last Report) Check the appropriate box below if the Form 8-K filing is intended to simultaneously satisfy the filing obligation of the registrant under any of the following provisions: ¨ Written communications pursuant to Rule 425 under the Securities Act (17 CFR 230.425) ¨ Soliciting material pursuant to Rule 14a-12 under the Exchange Act (17 CFR 240.14a-12) ¨ Pre-commencement communications pursuant to Rule 14d-2(b) under the Exchange Act (17 CFR 240.14d-2(b)) ¨ Pre-commencement communications pursuant to Rule 13e-4(c) under the Exchange Act (17 CFR 240.13e-4(c)) Item 2.02 Results of Operations and Financial Condition. Item 7.01 Regulation FD Disclosure. The information in this Report, including the Exhibit 99.1 attached hereto, is furnished pursuant to Item 2.02 and Item 7.01 of this Form 8-K. Consequently, it is not deemed “filed” for the purposes of Section 18 of the Securities and Exchange Act of 1934, as amended, or otherwise subject to the liabilities of that section. -
Supermicro H8DME-2
Supermicro H8DME-2 Key Features 1. Dual AMD® Opteron™ 2000 Series (Socket F) Support, 1000 MHz HyperTransport Link 2. nVidia MCP55 Pro / NEC uPD720400 Chipset 3. Up to 32GB DDR2 667 SDRAM Up to 32GB DDR2 533 SDRAM Up to 64GB DDR2 400 SDRAM 4. Dual-port Gigabit LAN/Ethernet Controller 5. 6 SATA2 3.0Gb/s HDD Support 6. 2 x8 PCI-e, 2 64-bit 133/100MHz PCI-X, 2 64-bit 100MHz PCI-X 7. ATI ES1000 Graphics 8. SIMLC IPMI 2.0 Support 9. 8 Fan Support with Speed Control Product SKUs Chassis ( Optimized for H8DME-2 ) MBD-H8DME-2- • H8DME-2 (Standard Retail Pack) O • CSE-825TQ-560LPV * • CSE-825TQ-R700LPV * MBD-H8DME-2- • H8DME-2 (Bulk Pack) B 2U Chassis * Please use air-shroud MCP-310-00025- 01 Physical Stats (Air-shrouds sold separately) • CSE-745TQ-800 • Extended ATX Form Factor • CSE-745TQ-R800 • CSE-745TQ-700 • 12" x 13.05" (30.5cm x 33.2cm) • Dimensions CSE-745TQ-R700 Rackmount • CSE-743TQ-R760 Tower / 4U • CSE-743T-R760 Processor/Chipset • CSE-743i-R760 • CSE-743T-650 • Dual 1207-pin Socket F • CSE-743i-650 • Supports up to two AMD Opteron™ 2000 Series (Socket F) processor(s) CPU • • Dual-core Support To ensure system stability, a 420W (minimum) ATX power supply Important [ 4-pin (+12V), 8-pin (+12V) and 24- • 1000MHz HyperTransport Chassis Notes pin are required] System Bus • nVidia MCP55 Pro Chipset • NEC uPD720400 Expansion Slots • 2 x8 PCI-e slots • System Memory 1 SEPC (Supermicro extended Power Connector) slot for 2U active PCI-Express • riser cards with a power extension Sixteen 240-pin DIMM sockets (i.e. -
AMD's Early Processor Lines, up to the Hammer Family (Families K8
AMD’s early processor lines, up to the Hammer Family (Families K8 - K10.5h) Dezső Sima October 2018 (Ver. 1.1) Sima Dezső, 2018 AMD’s early processor lines, up to the Hammer Family (Families K8 - K10.5h) • 1. Introduction to AMD’s processor families • 2. AMD’s 32-bit x86 families • 3. Migration of 32-bit ISAs and microarchitectures to 64-bit • 4. Overview of AMD’s K8 – K10.5 (Hammer-based) families • 5. The K8 (Hammer) family • 6. The K10 Barcelona family • 7. The K10.5 Shanghai family • 8. The K10.5 Istambul family • 9. The K10.5-based Magny-Course/Lisbon family • 10. References 1. Introduction to AMD’s processor families 1. Introduction to AMD’s processor families (1) 1. Introduction to AMD’s processor families AMD’s early x86 processor history [1] AMD’s own processors Second sourced processors 1. Introduction to AMD’s processor families (2) Evolution of AMD’s early processors [2] 1. Introduction to AMD’s processor families (3) Historical remarks 1) Beyond x86 processors AMD also designed and marketed two embedded processor families; • the 2900 family of bipolar, 4-bit slice microprocessors (1975-?) used in a number of processors, such as particular DEC 11 family models, and • the 29000 family (29K family) of CMOS, 32-bit embedded microcontrollers (1987-95). In late 1995 AMD cancelled their 29K family development and transferred the related design team to the firm’s K5 effort, in order to focus on x86 processors [3]. 2) Initially, AMD designed the Am386/486 processors that were clones of Intel’s processors. -
N51tp/Te AMD PUMA Rev 0.6 2008/Nov/05
N51Tp/Te AMD PUMA www.asus.com Rev 0.6 2008/Nov/05 2-Spindle, AMD Puma 15.6” HD LED TFT Panel Specifications Processor & AMD Turion(tm) 64 Mobile Technology Dual Core n Bat. Charging/full/low (Orange) Cache n Lion CPU ZM84/82/80, S1g2 package, n Wireless indicator (Blue) 2M L2 cache, 800MHz, Hyper Transport 3.0 n Bluetooth Indicator (Blue) n Lion CPU RM-72, S1g2 package, n Storage Device Access (Blue) 1M L2 cache, 800MHz, Hyper Transport 3.0 Near Power button n Num Lock (White) AMD Athlon 64 Mobile Technology Dual Core n Cap. Lock (White) n Lion CPU QL-62 S1g2 package, n Ionizer (White) 1M L2 cache, 667MHz, Hyper Transport 3.0 Cap sensor n Mode Switch (Blue) BIOS n AMI BIOS code (Below LEDs dim 3 times when activated.) n 8Mb Flash EPROM n Rewind (Blue) n PMU, Plug & Play n Play/Pause n Boot from USB, LAN,Ai-Flash 3,Ai-Flash 4, Ai-Flash 5 n Stop n Forward Chipset n AMD RS780M + SB700 HT3.0(5200MHz) n Volume up/down n Ionizer Main Memory n 2 x SODIMM Sockets for Expansion Up to 4 GB (BTO n Hybrid Power4Gear Option) n Splendid n Dual Channel DDR2 800 DRAM support n Touchpad disable Display n 15.6” VESA Like LED HD 1366*768; Full-HD Video Camera n Fixed Camera, 1.3M 1920*1080 (N51 BTO) n Fixed Camera, 2.0M n AI Light Sensor n Without Camera ATI M96(Tp) with 1G VRAM, Graphics & Video n Keyboard n Universal Numeric K/B ATI M92(Te) (New package), with 512M VRAM Module n n Vista K/B Start Button n DDR2 VRAM(64Mx16): 1G(Tp); 512M(Te) n DX10.1 Support Ionizer n Sunyou DC5V, 1.8KV n H.264/VC-1 Hardware decoding n HDCP support for HDMI port n One -
Six-Core AMD Opteron™ Processor with AMD
AMD最新テクノロジーアップデート -HPCへの取り組み- 日本AMD株式会社 マーケティング&ビジネス開発本部 エンタープライズプロダクトマーケティング部 部長 山野 洋幸 AMD’s HPC Product Portfolio Energy efficient CPU and discrete GPU processors focused on addressing the most demanding HPC workloads Multi-core x86 Processors • Outstanding Performance • Superior Scalability • Enhanced Power Efficiency Professional Graphics • 3D Accelerators For Visualization • See More and Do More with Your Data ATI Stream Computing • GPU Optimized For Computation • Massive Data-parallel Processing • High Performance Per Watt 2 | AMD HPC Product Portfolio Update @ SC’09 | November 30, 2009 For more information be sure to visit AMD at SC’09 booth #1417 AMD’s HPC Product Portfolio Energy efficient CPU and discrete GPU processors focused on addressing the most demanding HPC workloads Multi-core x86 Processors • Outstanding Performance • Superior Scalability • Enhanced Power Efficiency Professional Graphics • 3D Accelerators For Visualization • See More and Do More with Your Data ATI Stream Computing • GPU Optimized For Computation • Massive Data-parallel Processing • High Performance Per Watt 3 | AMD HPC Product Portfolio Update @ SC’09 | November 30, 2009 For more information be sure to visit AMD at SC’09 booth #1417 Planned Server Platform Roadmap 2006 2007 2008 2009 2010 2011 “Maranello” Socket G34 with AMD SR56x0 and SP5100 Magny-Cours New Architecture Six-Core AMD Opteron™ Processor with AMD way Chipset - Socket F(1207) with AMD SR56x0 and SP5100 Shanghai/Istanbul Platform 2/4 Enterprise Enterprise “Socket F (1207)” Socket F(1207) -
AMD Zen Rohin, Vijay, Brandon Outline
AMD Zen Rohin, Vijay, Brandon Outline 1. History and Overview 2. Datapath Structure 3. Memory Hierarchy 4. Zen 2 Improvements History and Overview AMD History ● IBM production too large, forced Intel to license their designs to 3rd parties ● AMD fills the gap, produces clones for 15ish years - legal battles ensued ● K5 first in-house x86 chip in 1996 ● Added more features like out of order, L2 caches, etc ● Current CPUs are Zen* tomshardware.com/picturestory/71 3-amd-cpu-history.html Zen Brand ● Performance desktop and mobile computing ○ Athlon ○ Ryzen 3, Ryzen 5, Ryzen 7, Ryzen 9 ○ Ryzen Threadripper ● Server ○ EPYC https://en.wikichip.org/wiki/amd/microarchitectures/zen Zen History ● Aimed to replace two of AMD’s older chips ○ Excavator: high performance architecture ○ Puma: low power architecture https://en.wikichip.org/wiki/amd/microarchitectures/zen#Block_Diagram Zen Architecture ● Quad-core ● Fetch 4 instructions/cycle ● Op cache 2k instructions ● 168 physical integer registers ● 72 out of order loads ● Large shared L3 cache ● 2 threads per core https://www.slideshare.net/AMD/amd-epyc-microp rocessor-architecture Datapath Structure Fetch ● Decoupled branch predictor ○ Runs ahead of fetches ○ Successful predictions help latency and memory parallelism ○ Mispredictions incur power penalty ● 3 layer TLB ○ L0: 8 entries ○ L1: 64 entries ○ L2: 512 entries https://www.anandtech.com/show/10591/amd-zen-microarchiture-p art-2-extracting-instructionlevel-parallelism/3 Branch Predictor ● Perceptron: simple neural network ● Table of perceptrons, each a vector of weights ● Branch address used to access perceptron table ● Dot product between weight vector and branch history vector Perceptron Branch Predictor ● ~10% improve prediction rates over gshare predictor - (2, 2) correlating predictor ● Can utilize longer branch histories ○ Hardware requirements scale linearly whereas they scale exponentially for other predictors D. -
AMD Details Next-Generation Platform for Notebook Pcsamd Details Next-Generation Platform for Notebook Pcs 18 May 2007
AMD Details Next-Generation Platform for Notebook PCsAMD Details Next-Generation Platform for Notebook PCs 18 May 2007 At a press conference in Tokyo, Japan, AMD today AMD’s next-generation notebook “Griffin” officially disclosed more details of its next- microprocessor. With “Griffin,” AMD will deliver a generation open platform for notebook computing. number of new capabilities to enhance battery life Codenamed “Puma,” the platform is designed to and overall mobile computing performance. deliver battery life, graphics and video processing enhancements and improved overall system New notebook processing innovations in “Griffin” performance for an enhanced visual experience. include: The “Puma” platform is expected to build on the -- power optimized HyperTransport and memory successful launches of the AMD M690 mobile controllers integrated in the processor silicon that chipset and 65nm process-based AMD Turion 64 operate on a separate power plane as the X2 dual-core mobile technology in April and May processor cores, thereby enabling the cores to go 2007, respectively. into reduced power states; -- dynamic performance scaling offers enhanced The key technologies that comprise “Puma” are battery life with reduced power consumption AMD’s next-generation notebook processor, through separate voltage planes enabling each codenamed “Griffin”, matched with the next- core to operate at independent frequency and generation AMD “RS780” mobile chipset. This voltage; and new platform exemplifies AMD’s commitment to -- power-optimized HyperTransport 3.0 with a more improve platform stability, time to market, than tripling of peak I/O bandwidth, plus new power performance/energy-efficiency and overall features including dynamic scaling of link widths. consumer and commercial customers’ experience via its acquisition and integration of ATI. -
Six-Core AMD Opteron Processor Istanbul Paul G. Howard, Ph.D
Six-Core AMD Opteron Processor Istanbul Paul G. Howard, Ph.D. Chief Scientist, Microway, Inc. Copyright 2009 by Microway, Inc. In April 2009 AMD™ announced the first 6-core Opteron processor, codenamed Istanbul1; delivery began in June 2009, four months ahead of schedule. Istanbul is based on the AMD 64-bit K10 architecture, and is available for 2-, 4-, and 8-socket systems, with clock speeds ranging from 2.0 to 2.8 GHz. Istanbul is the successor to the quad-core Shanghai processor, launched in 2008. It provides up to 30 percent more performance in the same socket and with the same power draw. Here is a summary of the features of the 6-core Istanbul processor: • Six cores mean more performance, and also more performance per watt because the power and thermal envelopes are the same as for 4-core processors • Consistent architecture, scalable to 2, 4, or 8 processor systems • Energy efficient, incorporates AMD-P power management • Virtualization support using AMD-V • Improved bandwidth, through the use of HyperTransport 3.0 and HT Assist. The current state of AMD Opteron processors Istanbul is based on the AMD K10 64-bit architecture and manufactured on a 45 nm SOI process2. Processors in the K10 line to date are shown in the following table. Code Frequency L3 cache Model number Introduction name Cores Sockets (GHz) (MB) Process range3 date Barcelona 4 4 or 8 1.9-2.5 2 65 nm 8346-8360 September 2007 Barcelona 4 2 1.9-2.5 2 65 nm 2344-2360 September 2007 Budapest 4 1 2.1-2.5 2 65 nm 1352-1356 June 2008 Shanghai 4 4 or 8 2.2-3.1 6 45 nm 8374-8393 November 2008 Shanghai 4 2 2.1-3.1 6 45 nm 2372-2393 November 2008 Suzuka 4 1 2.5-2.9 6 45 nm 1381-1389 June 2009 Istanbul 6 4 or 8 2.1-2.8 6 45 nm 8425-8439 June 2009 Istanbul 6 2 2.0-2.8 6 45 nm 2423-2439 June 2009 Budapest uses the same core as Barcelona, and Suzuka uses the same core as Shanghai.