(3-D) Integration Technology
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FP7-ICT-2007-1 ELITE-215030 August 2011 CONFIDENTIAL WP: D2.5 Conclusion Report Extended Large (3-D) Integration TEchnology Seventh Framework Programme FP7-ICT-2007-1 Project Number: FP7-ICT-215030 D2.5: 3-D IC’s Modelling and Simulation: Conclusion Report Version 3.0 [1] FP7-ICT-2007-1 ELITE-215030 August 2011 CONFIDENTIAL WP: D2.5 Conclusion Report [2] FP7-ICT-2007-1 ELITE-215030 August 2011 CONFIDENTIAL WP: D2.5 Conclusion Report Extended Large (3-D) Integration TEchnology Project Name Extended Large (3-D) Integration Technology Project Number ELITE-215030 Document Title 3D IC’s Modelling and Simulation: Conclusion Report Work Package WP2 Dissemination Level CONFIDENTIAL Lead Beneficiary Lancaster University (ULANC) Document Editors Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa (ULANC), Christine Fuchs (LETI), Luca Bortesi and Loris Vendrame (MICRON) Version 3.0 [3] FP7-ICT-2007-1 ELITE-215030 August 2011 CONFIDENTIAL WP: D2.5 Conclusion Report Abstract In this report we discuss the modelling and analysis of 3-D ICs within the scope of ELITE project and their usage in design space exploration of general systems. We present a set of TSV parasitic extraction models for various TSV structures laid out in different substrates, taking into account the physical proximity of neighbouring TSVs. The proposed models can be used in system-level performance design space explorations. The RF and low-frequency behaviour of TSVs has also been modelled and measured from test structures. We then discuss 3-D signalling conventions by exhaustively quantifying the trade offs between standard CMOS drivers and receivers as well as shielding techniques over the TSVs. Then, the methodology to model the thermal behaviour of a die stack is discussed and a stand-alone tool for thermal performance estimation is presented. We follow with the network-level communication analysis where we show how the average distance as a design metric can aid in the partitioning and optimization of large multi-core systems. We then discuss the scalability of 2-D and 3-D networks-on-chip and vertical clocking schemes. Finally we use all of the physical, circuit, and communication-level analyses to create system-level models for performance of computational units. Keywords 3-D Integration, Through-Silicon Via (TSV), Parasitic parameter extraction, Signalling, Thermal Compact Models, Computational efficiency, Flash memory, Integrated Circuit (IC) design. [4] FP7-ICT-2007-1 ELITE-215030 August 2011 CONFIDENTIAL WP: D2.5 Conclusion Report Table of Contents 1. INTRODUCTION .............................................................................................................................................. 7 2. ELECTRICAL MODELLING OF TSVS ........................................................................................................ 8 2.1. INTRODUCTION ......................................................................................................................................... 8 2.2. RELATED WORK ....................................................................................................................................... 8 2.3. 3-D INTEGRATION TECHNOLOGY ....................................................................................................... 9 2.4. PHYSICAL MODELLING OF TSVS ....................................................................................................... 11 2.5. TSV MODELLING IN THE RADIO FREQUENCY RANGE .............................................................. 27 2.6. LOW-FREQUENCY CAPACITANCE MEASUREMENTS ................................................................. 44 2.7. PHYSICAL MODELLING CONCLUSIONS .......................................................................................... 52 3. SIGNALLING CONVENTIONS FOR 3-D ICS ........................................................................................... 54 3.1. INTRODUCTION ....................................................................................................................................... 54 3.2. RELATED WORK ..................................................................................................................................... 54 3.3. TSV PARASITICS AND ELECTRICAL MODEL ................................................................................. 55 3.4. PERFORMANCE COMPARISON: ENERGY, AREA, SI AND BANDWIDTH ................................. 70 3.5. DISCUSSIONS AND CONCLUSIONS..................................................................................................... 72 4. COMPACT THERMAL MODELLING OF 3-D ICS .................................................................................. 73 4.1. INTRODUCTION ....................................................................................................................................... 73 4.2. RELATED WORK ..................................................................................................................................... 74 4.3. THERMAL ANALYSIS OF INTEGRATED CIRCUITS....................................................................... 74 4.4. DISCUSSION AND CONCLUSIONS ....................................................................................................... 82 5. COMMUNICATION PLATFORM ARCHITECTURES............................................................................ 83 5.1. OPTIMAL NETWORK ARCHITECTURES .......................................................................................... 84 5.2. SCALABILITY OF 3-D NOC ARCHITECTURES ................................................................................ 96 5.3. PERFORMANCE ANALYSIS OF MULTI-CLOCK 3-D NOCS ........................................................ 106 5.4. CONCLUSIONS ........................................................................................................................................ 112 [5] FP7-ICT-2007-1 ELITE-215030 August 2011 CONFIDENTIAL WP: D2.5 Conclusion Report 6. SYSTEM-LEVEL MODELLING OF SILICON SYSTEMS .................................................................... 113 6.1. INTRODUCTION ..................................................................................................................................... 113 6.2. RELATED WORK ................................................................................................................................... 113 6.3. MODELLING PERFORMANCE ........................................................................................................... 114 6.4. EFFECTIVE COMPUTATIONAL EFFICIENCY ............................................................................... 116 6.5. SCALING CIRCUITS, DEVICES AND INTERCONNECTS ............................................................. 120 6.6. DESIGN SPACE EXPLORATION ......................................................................................................... 120 6.7. COST .......................................................................................................................................................... 124 6.8. APPLICATIONS OF THE MODEL ....................................................................................................... 125 6.9. CONCLUSIONS ........................................................................................................................................ 131 D2.5 CONCLUSIONS ............................................................................................................................................. 133 REFERENCES ........................................................................................................................................................ 134 [6] FP7-ICT-2007-1 ELITE-215030 August 2011 CONFIDENTIAL WP: D2.5 Conclusion Report 1. Introduction WP2 in the ELITE project addresses all the steps necessary for pre-fabrication estimation of performance, signal integrity, power integrity, thermal behaviour and cost of 3-D ICs. A hierarchical approach has been adopted in this work package, with models at different levels of abstraction proceeding from physical to circuit to network to system level to enable efficient and detailed analyses at various points in the spectrum defined by computational efficiency vs. accuracy. The modelling activity is supported by simulation methodologies for investigating overall performance metrics and are used to carry out detailed design space explorations to provide understanding and insight into the design of 3-D integrated circuits in various application domains. Figure 1 shows the hierarchy of tasks carried out in WP2 and their usage in the design of 3-D ICs. Figure 1 ELITE WP2 Modelling and Simulation Package Task Dependencies The models as well as their usage have previously been reported in various forms to the general public and through internal reports and deliverables to ELITE consortium. The deliverables submitted within WP2 are: D2.1: Extraction and Simulation Methodology D2.2: 3D IC Analysis D2.3: 3D IC Simulation D2.4: 3D Signalling Conventions In order to make this report a complete stand-alone source for system-level performance estimation models and their usage, we reproduce relevant portions of the previously reported works together with updates as per the discussions and comments received from ELITE partners. This report is organized as follows: in Chapter 2, we discuss TSV electrical models for various configurations and geometries in different substrate types. We follow with RF modelling and