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Am29050 Micro RISC Microprocessor with On-Chip Floating-Point Unit Devices

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Am29050 Micro RISC Microprocessor with On-Chip Floating-Point Unit Devices FINAL Advanced Am29050 Micro RISC Microprocessor with On-Chip Floating-Point Unit Devices DISTINCTIVE CHARACTERISTICS 64-entry Memory Management Unit (MMU) with region mapping Full 32-bit, three-bus architecture 1024-byte branch target cache 55 million instructions per second (MIPS) sustained at 40 MHz 4-entry physical address cache On-chip double-precision floating-point Demultiplexed and pipelined address, arithmetic unit instruction, and data buses 80-megaflop peak floating-point execution 192 general-purpose registers at 40 MHz Three-address instruction architecture 40-, 33-, 25-, and 20-MHz operating frequencies On-chip byte-alignment support allows CMOS technology/TTL compatible optional byte/half-word accesses 4-Gbyte virtual address space Pin and bus compatibility with Am29000 and with demand paging Am29005 microprocessors Concurrent instruction and data accesses Binary compatibility with all 29K microprocessors and microcontrollers Burst-mode access support Advanced debugging support SIMPLIFIED BLOCK DIAGRAM AddressAm29050 Data RISC Microprocessor 32 32 32 Instruction ROM Instruction Instruction Memory Data Memory Publication# 15039 Rev. B Amendment /0 Issue Date: December 1994. WWW: 5/4/95 AMD A D V A N C E I N F O R M A T I O N DISTINCTIVE CHARACTERISTICS 1 SIMPLIFIED BLOCK DIAGRAM 1 GENERAL DESCRIPTION 3 RELATED AMD PRODUCTS 3 29K FAMILY DEVELOPMENT SUPPORT PRODUCTS 3 THIRD-PARTY DEVELOPMENT SUPPORT PRODUCTS 3 ORDERING INFORMATION 4 LOGIC SYMBOL 5 KEY FEATURES AND BENEFITS 6 PERFORMANCE OVERVIEW 8 CONNECTION DIAGRAM 12 169-LEAD PGA 12 PGA Pin Designations by Pin Number 13 PGA Pin Designations by Pin Name 14 PIN DESCRIPTIONS 15 ABSOLUTE MAXIMUM RATINGS 19 OPERATING RANGES 19 DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL Operating Ranges 19 CAPACITANCE 19 SWITCHING CHARACTERISTICS over COMMERCIAL Operating Range 21 SWITCHING CHARACTERISTICS over INDUSTRIAL Operating Range 22 SWITCHING WAVEFORMS 25 CAPACITIVE OUTPUT DELAYS 28 SWITCHING TEST CIRCUIT 28 THERMAL CHARACTERISTICS 29 PHYSICAL DIMENSIONS 30 CGX 169 30 2 Am29050 Microprocessor AMD GENERAL DESCRIPTION and imaging applications with fast 3D performance and gives printers the highest performance page description The Am29050 RISC microprocessor is a high-perfor- language (PDL) possible. mance, general-purpose, 32-bit microprocessor imple- mented in CMOS technology. It supports a variety of The Am29050 microprocessor instruction set has been applications by virtue of a flexible architecture and rapid influenced by the results of high-level language, optimiz- execution of simple instructions that are common to a ing compiler research. It is appropriate for a variety of lan- wide range of tasks. guages because it efficiently executes operations that are common to all languages. Consequently, the Am29050 The Am29050 microprocessor meets the demanding microprocessor is an ideal target for high-level languages requirements of floating-point intensive embedded ap- such as C, FORTRAN, Pascal, Ada, and COBOL. plications such as X terminals, signal processing, and digital communications. Because it excels at complex The processor is available in a 169-lead pin grid array math operations required for fast matrix transforma- (PGA) package. The PGA has 141 signal pins, 27 power tions, the Am29050 microprocessor provides graphics and ground pins, and 1 alignment pin. RELATED AMD PRODUCTS 29K Family Devices Part No. Description Am29000 32-bit RISC microprocessor Am29005 Low-cost 32-bit RISC microprocessor with no MMU and no branch target cache Am29030 32-bit RISC microprocessor with 8-Kbyte instruction cache Am29035 32-bit RISC microprocessor with 4-Kbyte instruction cache Am29040 32-bit RISC microprocessor with 8-Kbyte instruction cache and 4-Kbyte data cache Am29200 32-bit RISC microcontroller Am29205 Low-cost 32-bit RISC microcontroller with 16-bit bus interface Am29240 32-bit RISC microcontroller with 4-Kbyte instruction cache and 2-Kbyte data cache Am29243 32-bit RISC data microcontroller with instruction and data caches and DRAM parity Am29245 Low-cost 32-bit RISC microcontroller with 4-Kbyte instruction cache 29K FAMILY DEVELOPMENT SUPPORT PRODUCTS Contact your local AMD representative for information Assembler and utility packages on the complete set of development support tools. The Source- and assembly-level software debuggers following software and hardware development products are available on several hosts: Target-resident development monitors Simulators Optimizing compilers for common high-level Demonstration and evaluation systems languages THIRD-PARTY DEVELOPMENT SUPPORT PRODUCTS The Fusion29K Program of Partnerships for Applica- Modeling/simulation tools tion Solutions provides the user with a vast array of prod- Software development tools ucts designed to meet critical time-to-market needs. Products and solutions available from the AMD Fu- Real-time operating systems (RTOS) sion29K Partners include Application-specific hardware and software Silicon products Board-level products Emulators Manufacturing and prototyping support Hardware and software debuggers Custom support and training Am29050 Microprocessor 3 AMD ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. Valid order numbers are formed by a combination of the elements below. AM29050 –25G C SHIPPING OPTION Blank = Standard Processing B = Burn-in TEMPERATURE RANGE C = Commercial (TC =0°C to +85°C) I = Industrial (TC = –40°C to +125°C *) * TC =TJ = 125°C max PACKAGE TYPE G = 169-Lead Pin Grid Array (CG169) SPEED OPTION –40 = 40 MHz –33 = 33 MHz –25 = 25 MHz –20 = 20 MHz DEVICE NUMBER/DESCRIPTION Am29050 RISC Microprocessor with On-Chip Floating-Point Unit Valid Combinations Comments Valid Combinations Valid Combinations list configurations AM29050–40 With heat sink planned to be supported in volume for AM29050–33 With heat sink GC this device. Consult the local AMD sales AM29050–25 Without heat sink office to confirm availability of specific AM29050–20 Without heat sink valid combinations and to check on newly released combinations. AM29050–33 With heat sink AM29050–25 GI Without heat sink AM29050–20 Without heat sink 4 Am29050 Microprocessor AMD LOGIC SYMBOL BREQ BGRT PEN BINV IRDY R/W IERR SUP/US IBACK LOCK 2 DRDY MPGM1–MPGM0 DERR IREQ DBACK PDA CDA DBREQ 2 WARN DREQT1–DREQT0 4 INTR2–INTR0 MSERR 2 CNTL1–CNTL0 RESET OPT2–OPT0 3 TEST STAT2–STAT0 3 INCLK IREQT 2 TRAP1–TRAP0 PIA 32 I31–I0 IBREQ PWRCLK A31–A0 32 SYSCLK D31–D0 Am29050 Microprocessor 5 AMD KEY FEATURES AND BENEFITS The Am29050 microprocessor extends the 29K Family table that contains the most recently used address of processors with a high-performance, pipelined, on- translations for the processor. TLB entries are modified chip floating-point unit. The floating-point unit performs directly by processor instructions. A TLB entry consists IEEE-compatible, single-precision and double-preci- of 64 bits and appears as two word-length TLB registers sion arithmetic at a peak rate of 80 million floating-point that can be inspected and modified by instructions. operations per second (MFLOPS) at 40 MHz. The Am29050 microprocessor also has features to improve In addition to page-by-page address translation, the the performance of loads and branches, allowing sus- Am29050 microprocessor supports translation for vari- tained integer performance of 55 million instructions per able-sized regions. The region mapping units map virtu- second (MIPS) at 40 MHz. al regions of variable size ranging from 64 Kbyte to 2 Gbyte into regions of physical memory. Each region The Am29050 microprocessor provides a powerful up- mapping unit consists of two protected special-purpose grade to the Am29000 microprocessor. It can be used in registers. Any virtual address not mapped by the region existing Am29000 processor applications without hard- mapping units is translated by the TLB. ware or software modifications, bringing a dramatic in- crease in performance to floating-point-intensive Branch Target Cache applications, particularly graphics and laser-printer ap- The branch target cache on the Am29050 microproces- plications. sor allows fast access to instructions fetched nonse- quentially. This keeps the instruction pipeline full until Added features include a pipelined floating-point arith- the processor can establish a new instruction-prefetch metic unit, region mapping for virtual-to-physical ad- stream from the external instruction memory. A branch dress translation, a monitor mode for debugging instruction can execute in a single cycle if the branch tar- supervisor code, and instruction breakpoints for en- get is in the branch target cache. hanced debugging. Specific performance enhance- ments to the Am29000 microprocessor include a larger The branch target cache is a 1-Kbyte storage array that branch target cache, a physical address cache, an early contains blocks of instructions from recently taken address generator, and instruction forwarding logic. branches. To improve the proportion of successful searches, the branch target cache is organized as a On-Chip Floating-Point Arithmetic Unit two-way set-associative memory. The branch target An on-chip floating-point unit performs single- and cache can be configured under software control to double-precision floating-point operations in accor- cache either two or four instructions for each branch. dance with the IEEE Standard for Binary Floating-Point Each of the two sets in the branch target cache contains Arithmetic (ANSI/IEEE Standard 754-1985).
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