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Chapter Thirteen Chapter Thirteen Fatigue damage in microelectronic packages H. Lu & R. Das Department of Mechanical and Industrial Engineering, Ryerson University, Toronto, Canada Abstract This chapter aims to present some background on electronic-package configuration (structure and material) and packaging mechanics, followed by a brief introduction to a computer vision technique measuring the solder-joint deformation. With a summary of recent research on the solder-joint creep and fatigue, the emphasis of the chapter is placed on presenting ongoing research for a new, experimental physics-based methodology for solder-creep fatigue analysis. The common view is that a reliability study for a package should focus on critical areas in the solder interconnects where fatigue failures are deemed to initiate from. Such a study usually has two important aspects. The first is obtaining high-resolution strain measurements in the identified failure-prone local areas at different stages of a thermal cycle. And the second is analyzing the measured deformation for life prediction based on certain well-established criteria of solder failure. In addition to the practical usage of the new methodology, applications of it are expected to contribute to clarifying issues of controversies in the current, conventional-procedure-based reliability assessment. 1 Introduction Interconnect fatigue due to thermal stress is a common cause of failure for microelectronics and thus a key concern of the packaging reliability. For decades, the design, manufacturing, research and development of the microelectronic packages have been driven by the product renovation and miniaturization. Such a trend is dictated by the continued growth in interconnect density, per package pin-count and footprint, and the enhanced package power consumption as well as the hostile operating conditions. The conventional “build and test” type approaches for design evaluation and reliability assessment can barely meet the challenges, thus necessitating the research for physics-based, innovative, cost- and time-effective methodologies. WIT Transactions on State of the Art in Science and Engineering, Vol 1, © 2005 WIT Press www.witpress.com, ISSN 1755-8336 (on-line) doi:10.2495/1-85312-836-8/13 436 Advances in Fatigue, Fracture and Damage Assessment Solder interconnects in a microelectronic package serve as both the electrical connection and the mechanical bond between the components and the carriers. The surface-mount manufacturing technology requires the bumped solder balls on a package substrate be subjected to the solder-reflow process to form solder joints. During the package’s operation, the power on-and-off cycles and the fluctuation in external environment further subject the package to variations of temperature and other environmental parameters. The thermal fatigue of the solder joints due to cyclic deformation is considered as one of the main root causes of the physical disconnect of the joints. The situation gets worse where the CTE (thermal expansion coefficient) of materials on both sides of the solder joints highly mismatch [1]. A typical ceramic power package, as an example, is composed of a ceramic chip with a CTE around 6 ppm/°C and an epoxy-glass chip carrier (i.e., a printed circuit board) of 16 ppm/°C. For such a package, a temperature rise of 100 oC can induce a solder-joint shear deformation with a magnitude of a few per cent. The ultimate purpose of the reliability study for an electronic package is to predict the “life” span, or the time period for the package to deliver reliable service. In practical terms, the end result of an evaluation is simply a number that represents the thermal cycles to failure for the weakest joint of that package. To realize that, the industry commonly adopts the thermal cycle testing to reach a kind of estimate. The testing is “accelerated” for time efficiency, which means that both the amplitude and frequency of the thermal cycling are enhanced to cause the solder joint to fatigue damage and fracture in a short time period. To correlate the test results with the real package life, however, is a much more complex issue that has been under intensive study in the past. It is noted that while creep fatigue of ordinary metals and alloys usually occurs under elevated temperature [2], solders exhibit time-dependent behaviour even at below the room temperature thanks to their low melting points. The time dependency of solder properties poses challenges to accurately characterize the material parameters as well as to design the accelerated cycle testing and to determine the factor of acceleration for interpreting the test data. Besides, the “acceleration” can create failure modes far different from what actually occurs under service conditions. This situation has been the driving force behind the research for new reliability- assessment methodologies. Ideally, they should be based on testing real packages under real service or processing conditions. Part A: Basics in electronic packaging 2 Soldering in electronic packaging The electronic packaging is “the technology of packaging electronic equipment” [3]. The soldering is a process by which two metals or alloys are joined together with a third metal, usually a solder alloy with lower melting point [4]. The soldering process involves both chemical and physical reactions and results in a metallurgical rather than a mechanical contact with the joining materials. WIT Transactions on State of the Art in Science and Engineering, Vol 1, © 2005 WIT Press www.witpress.com, ISSN 1755-8336 (on-line) Advances in Fatigue, Fracture and Damage Assessment 437 Soldering ensures the electrical contact at a joint only if the joint possesses sufficient mechanical strength. The reliability of the solder joints depends upon the manufacturing process and the operating conditions the package is subjected to. The former affects mainly the joint formation such as the shape, microstructure, voids and other defects, and the latter induces the joint stress and deformation. 3 Level of electronic packaging The electronic packaging is usually divided into several levels, such as the component level (Level 1), module level (Level 2) and chassis level (Level 3) [3,5], etc. The component-level packaging requires technologies for attaching and interconnecting silicon microcircuits to the next-level packaging, and also for protecting the microcircuits from possible attacks from the environment. The structure and material configuration of the component-level package is determined depending upon whether the hermetic (ceramic) or the non-hermetic (plastic) packaging technology is used. In a hermetic package the silicon die is bonded to the cavity of a ceramic package, which is sealed by a lid with the thermal-expansion rate closely matching the package. Fine wires are used to interconnect the metal pads on the silicon die to the leads. As illustrated in Fig. 1 for a leadless chip carrier, the interconnection to the PCB (printed circuit board) is realized via soldering the leads to the metalized area outside the package. For a non-hermetic configuration, the silicon die is bonded to a heat spreader that is typically a part of a leadframe. Interconnection is made either Figure 1: Hermetic and non-hermetic packaging configuration [3]. WIT Transactions on State of the Art in Science and Engineering, Vol 1, © 2005 WIT Press www.witpress.com, ISSN 1755-8336 (on-line) 438 Advances in Fatigue, Fracture and Damage Assessment with thin wires between the die pads and the leads or directly between the leads and pads. Once interconnection is made, the entire assembly is encapsulated in epoxy to provide the protection from the environment. Module-level packaging interconnects components to the next-level packaging. Specifics of the module-level packaging configuration vary depending on whether the through-hole technology or the SMT (surface-mount technology) is used. A through-hole technology module typically uses dual-inline-package (DIP) packaging for interconnecting the microcircuits. The leads on these components are soldered into the holes in a PCB to interconnect with other components and the chassis. Where thermal performance is addressed, a heat sink may be attached to the PCB directly underneath the component. SMT, on the other hand, solders the components directly to the pads on the surface of a PCB. The SMT components are usually smaller in size than the DIP parts and can be mounted on both sides of the module to result in increased packaging density. Since no leads are necessary for interconnecting with the PCB, the components may be mounted on the back surface of the module to increase the usage of real estate. Bonding a heat sink to the PCB can enhance the heat dispersion to improve thermal performance of a SMT module. In some cases additional plated through holes (PTH) are used for better thermal conduction between the component and heat sink. Chassis-level packaging usually includes support rails to which the modules are mounted and a motherboard with connectors, which provides the necessary electrical interconnection to other modules and the main-chassis connectors. The modules may be mounted to the chassis by spring-loaded clips and mechanically actuated clamps and bolts, etc. 4 Electronics-packaging configurations The package architectures developed in the past decades are usually classified into these major configurations [3,5]: • Ball-grid arrays (BGA) • Multi-chip modules (MCM) • Flip-chips • Chip-on-board (COB) • Chip-scale package (CSP) A BGA package, as the schematic in Fig. 2 shows, is characterized by the arrays of solder balls bumped onto the bottom of the package. BGA technology allows controlled height of the solder joints to be realized during the soldering process. Underfill material can be applied to fill between the package and the PCB for improving the thermal performance and mechanical durability of the solder joints. WIT Transactions on State of the Art in Science and Engineering, Vol 1, © 2005 WIT Press www.witpress.com, ISSN 1755-8336 (on-line) Advances in Fatigue, Fracture and Damage Assessment 439 A MCM package may be simply defined as one containing more than one chip.
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