DOCSLIB.ORG

Parallel Algorithms in External Memory

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Parallel Algorithms in External Memory Parallel Algorithms in External Memory By David Alexander Hutchinson A thesis submitted to the Faculty of Graduate Studies and Research in partial fullmentof the requirements for the degree of Do ctor of Philosophy OttawaCarleton Institute for Computer Science Scho ol of Computer Science Carleton University Ottawa Ontario May Includes revisions as of February The original version of this thesis is available from University Microlms International c Copyright David Alexander Hutchinson Abstract External memory EM algorithms are designed for computational problems in which the size of the internal memory of the computer is only a small fraction of the prob lem size The Parallel Disk Mo del PDM of Vitter and Shriver is widely used to discriminate b etween external memory algorithms on the basis of inputoutput IO complexity Parallel algorithms are designed to eciently utilize the computing p ower of multiple pro cessing units interconnected by a communication mechanism Apop ular mo del for developing and analyzing parallel algorithms is the Bulk Synchronous Parallel BSP mo del due to Valiant In this work we develop simulation techniques b oth randomized and deterministic which pro duce ecient EM algorithms from ecient algorithms develop ed under BSP like parallel computing mo dels Our techniques can accommo date one or multiple pro cessors on the EM target machine each with one or more disks and they also adapt to the disk blo cking factor of the target machine We prop ose new more comprehensive mo dels for EM and parallel algorithms which consider the total costs incurred by the algorithm including computation IO and communication The new EMBSP EMBSP and EMCGM mo dels combine the features of the BSP and PDM and thereby answer to a challenge p osed by the ACM Working Group on Storage IO for LargeScale Computing We obtain parallel external memory algorithms for a large number of problems including sorting p ermutation matrix transp ose geometric and GIS problems in cluding D convex hulls D Voronoi diagrams and various graph problems ii Acknowledgements I would like to thank all of the p eople who have help ed me to complete the work describ ed in this thesis Knowing that I cannot thank everyone who has help ed me in my studies and fearing that I would forget someone who has help ed a great deal I have pro crastinated as usual in writing these acknowledgements However the time has come so I hop e that those who I have not listed will forgive me I am sure that I will rememb er all of you tomorrow after the publication deadline has passed I would like to thank m y three advisors Frank Dehne Anil Maheshwari and JorgRudiger Sack for their patience advice and for their condence that I would eventually nish this work In particular I want to thank my initial advisor JorgRudiger Sack for taking a gamble on me for the excellent infrastructure and nancial supp ort he provided and for his critical advice b oth on technical and nontechnical issues I would like to thank Frank Dehne for his help and encouragement in writing pap ers and for his unagging enthusiasm for our results and my prosp ects To Anil Maheshwari I oer my gratitude for the many hours wespent discussing Computer Science and other things over the past several years and for his unfailing willingness to do so on an impromptu basis Without his daytoday help encourage ment and quiet condence in our work I would not have been successful Iwould like to express my appreciation to Wolfgang Dittrich for his collab oration on many nice results and for showing me the power of mathematics in expressing ideas It has been a real pleasure working with him Tomy external examiner Abhiram Ranade and the other memb ers of my exami nation committee Thomas Kunz Ekow Oto o and Ivan Sto jmenovic thanks are due for their hard work in reading this thesis and for the useful suggestions they made I would like to thank my other coauthors Mark Lanthier Doron Nussbaum David Roytenb erg Radu V elicescu Norb ert Zeh and also Patrick Morin Kumanan Yogaratnam for many fruitful discussions and other co op erative work I also would like to thank Lyudmil Alexandrov for many interesting discussions and for his sug gestions for improving the algorithms in Chapter For their encouragement comments and questions which led me to new ideas I would like to acknowledge the help of Lars Arge Tom Cormen and Je Vitter To iii Lars thanks also for a comprehensive BibTeX le on external memory algorithms This was a great help to me Iwould like to thank the p eople of the Scho ol of Computer Science for the excellent working environment during my studies Particular thanks go to Rosemary Carter Barbara Coleman Linda Pfeier Maureen Sherman and Marlene Wilson Thanks also to the technical sta of SCS who kept the machines running and put up with my many suggestions To all of my faculty graduate and undergraduate colleagues who I have worked with as part of the Paradigm Group I oer my appreciation for your contributions to a great working environment Particular thanks go to Mark Lanthier for organizing the coke fund the pizza schedule and the ho ckey games and to Doron Nussbaum and Pat Morin for organizing the pizza talks FinallyI must acknowledge the help and supp ort of a group of p eople that have made the crucial dierence between success and failure for me First I would liketo thank my parents for instilling the desire to stretch for new and wonderful things and for their unconditional supp ort in all of myendeavours Lastly I oer very sp ecial thanks to my wife Gail and our children Lauren Julia Steven and Jessica for their supp ort and encouragement for their cheerfulness and for their love and aection I could not have continued without your help David Hutchinson Ottawa May This research was partially supp orted by Almerco Inc by the Natural Sciences and Engineering Research Council of Canada and by pTeran Computing Inc iv Contents Abstract ii Acknowledgements iii Intro duction Overview Motivation What Makes aGoodEM Algorithm Eectiveness of EM Techniques Fundamental Assumptions for Implementing Ecient IO Al gorithms Basic Data Formats on Multiple Disks Previous EM Research A Brief Survey External Memory Paradigms Batch Filtering Distribution Sweeping Data Structuring Simulation Lower Bounds on IO Complexity wer Bound Sorting Lo Permutation Lower Bound Matrix Transp ose Lower Bound A General Lower Bounding Technique Realistic Parameter Ranges The Role of RAIDs Storage Space Preliminaries Notation and Terminology Asymptotic Notation BSP Mo dels v A Central Issue Communication Bottlenecks Pap ers Contributing to the Thesis Claim to Originalityor Contribution to Knowledge Collab orations Contributions Organization of the Thesis Mo dels Overview Organization of This Chapter EM Mo dels Aggarwal and Vitter Single Disk Mo del The Parallel Disk Mo del PDM Hierarchical Memory Mo dels Parallel Computation Mo dels The Parallel Random Access Memory PRAM Mo del The Bulk Synchronous Parallel BSP Mo del The Extended BSP BSP Parallel Pro cessing Mo del The Coarse Grained Multicomputer CGM Mo del Other Parallel Computing Mo dels Combining PDM and BSPlike Mo dels Ob jective A More Comprehensive Mo del The EMBSP Mo del System Mo del Cost mo del The EMBSP Mo del The EMCGM Mo del Go o dness Criteria for Parallel EM Algorithms Extending the coptimality Criterion AlternativeGoodness Criteria for EMBSP Algorithms EMBSP Algorithms from Simulation Overview of the Metho d Overview and Rationale Randomized Simulation Single Pro cessor Target Machine Multiple Pro cessor Target Machine vi Deterministic Simulation Intro duction Balancing Communication Single Pro cessor Target Machine Multiple Pro cessor Target Machine Summary Deterministic Simulation with Lower Slackness Motivation Overview The Parallel Algorithm LowSlackRouting The Parallel Algorithm NumberBlocks Analysis of LowSlackRouting The EM Algorithm EMLowSlackRouting The EM Algorithm EMNumberBlocks Analysis of EMLowSlackRouting Single Pro cessor Target Machine
Load more

Recommended publications
  • Paralellizing the Data Cube
    PARALELLIZING THE DATA CUBE By Todd Eavis SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY AT DALHOUSIE UNIVERSITY HALIFAX, NOVA SCOTIA JUNE 27, 2003 °c Copyright by Todd Eavis, 2003 DALHOUSIE UNIVERSITY DEPARTMENT OF COMPUTER SCIENCE The undersigned hereby certify that they have read and recommend to the Faculty of Graduate Studies for acceptance a thesis entitled “Paralellizing the Data Cube” by Todd Eavis in partial fulfillment of the requirements for the degree of Doctor of Philosophy. Dated: June 27, 2003 External Examiner: Virendra Bhavsar Research Supervisor: Andrew Rau-Chaplin Examing Committee: Qigang Gao Evangelos Milios ii DALHOUSIE UNIVERSITY Date: June 27, 2003 Author: Todd Eavis Title: Paralellizing the Data Cube Department: Computer Science Degree: Ph.D. Convocation: October Year: 2003 Permission is herewith granted to Dalhousie University to circulate and to have copied for non-commercial purposes, at its discretion, the above title upon the request of individuals or institutions. Signature of Author THE AUTHOR RESERVES OTHER PUBLICATION RIGHTS, AND NEITHER THE THESIS NOR EXTENSIVE EXTRACTS FROM IT MAY BE PRINTED OR OTHERWISE REPRODUCED WITHOUT THE AUTHOR’S WRITTEN PERMISSION. THE AUTHOR ATTESTS THAT PERMISSION HAS BEEN OBTAINED FOR THE USE OF ANY COPYRIGHTED MATERIAL APPEARING IN THIS THESIS (OTHER THAN BRIEF EXCERPTS REQUIRING ONLY PROPER ACKNOWLEDGEMENT IN SCHOLARLY WRITING) AND THAT ALL SUCH USE IS CLEARLY ACKNOWLEDGED. iii To the two women in my life: Amber and Bailey. iv Table of Contents Table of Contents v List of Tables x List of Figures xi Abstract i Acknowledgements ii 1 Introduction 1 1.1 Overview of Primary Research .
    [Show full text]
  • Two-Level Main Memory Co-Design: Multi-Threaded Algorithmic Primitives, Analysis, and Simulation
    Two-Level Main Memory Co-Design: Multi-Threaded Algorithmic Primitives, Analysis, and Simulation Michael A. Bender∗x Jonathan Berryy Simon D. Hammondy K. Scott Hemmerty Samuel McCauley∗ Branden Moorey Benjamin Moseleyz Cynthia A. Phillipsy David Resnicky and Arun Rodriguesy ∗Stony Brook University, Stony Brook, NY 11794-4400 USA fbender,[email protected] ySandia National Laboratories, Albuquerque, NM 87185 USA fjberry, sdhammo, kshemme, bjmoor, caphill, drresni, [email protected] zWashington University in St. Louis, St. Louis, MO 63130 USA [email protected] xTokutek, Inc. www.tokutek.com Abstract—A fundamental challenge for supercomputer memory close to the processor, there can be a higher architecture is that processors cannot be fed data from number of connections between the memory and caches, DRAM as fast as CPUs can consume it. Therefore, many enabling higher bandwidth than current technologies. applications are memory-bandwidth bound. As the number 1 of cores per chip increases, and traditional DDR DRAM While the term scratchpad is overloaded within the speeds stagnate, the problem is only getting worse. A computer architecture field, we use it throughout this variety of non-DDR 3D memory technologies (Wide I/O 2, paper to describe a high-bandwidth, local memory that HBM) offer higher bandwidth and lower power by stacking can be used as a temporary storage location. DRAM chips on the processor or nearby on a silicon The scratchpad cannot replace DRAM entirely. Due to interposer. However, such a packaging scheme cannot contain sufficient memory capacity for a node. It seems the physical constraints of adding the memory directly likely that future systems will require at least two levels of to the chip, the scratchpad cannot be as large as DRAM, main memory: high-bandwidth, low-power memory near although it will be much larger than cache, having the processor and low-bandwidth high-capacity memory gigabytes of storage capacity.
    [Show full text]
  • Minimizing Writes in Parallel External Memory Search
    Proceedings of the Twenty-Third International Joint Conference on Artificial Intelligence Minimizing Writes in Parallel External Memory Search Nathan R. Sturtevant and Matthew J. Rutherford University of Denver Denver, CO, USA fsturtevant, [email protected] Abstract speed in Chinese Checkers, and is 3.5 times faster in Rubik’s Cube. Recent research on external-memory search has shown that disks can be effectively used as sec- WMBFS is motivated by several observations: ondary storage when performing large breadth- first searches. We introduce the Write-Minimizing First, most large-scale BFSs have been performed to ver- Breadth-First Search (WMBFS) algorithm which ify the diameter (the number of unique depths at which states is designed to minimize the number of writes per- can be found) or the width (the maximum number of states at formed in an external-memory BFS. WMBFS is any particular depth) of a state space, after which any com- also designed to store the results of the BFS for puted data is discarded. There are, however, many scenarios later use. We present the results of a BFS on a in which the results of a large BFS can be later used for other single-agent version of Chinese Checkers and the computation. In particular, a breadth-first search is the under- Rubik’s Cube edge cubes, state spaces with about lying technique for building pattern databases (PDBs), which 1 trillion states each. In evaluating against a com- are used as heuristics for search. PDBs require that the depth parable approach, WMBFS reduces the I/O for the of each state in the BFS be stored for later usage.
    [Show full text]
  • The Parallel Persistent Memory Model
    The Parallel Persistent Memory Model Guy E. Blelloch∗ Phillip B. Gibbons∗ Yan Gu∗ Charles McGuffey∗ Julian Shuny ∗Carnegie Mellon University yMIT CSAIL ABSTRACT 1 INTRODUCTION We consider a parallel computational model, the Parallel Persistent In this paper, we consider a parallel computational model, the Par- Memory model, comprised of P processors, each with a fast local allel Persistent Memory (Parallel-PM) model, that consists of P pro- ephemeral memory of limited size, and sharing a large persistent cessors, each with a fast local ephemeral memory of limited size M, memory. The model allows for each processor to fault at any time and sharing a large slower persistent memory. As in the external (with bounded probability), and possibly restart. When a processor memory model [4, 5], each processor runs a standard instruction set faults, all of its state and local ephemeral memory is lost, but the from its ephemeral memory and has instructions for transferring persistent memory remains. This model is motivated by upcoming blocks of size B to and from the persistent memory. The cost of an non-volatile memories that are nearly as fast as existing random algorithm is calculated based on the number of such transfers. A access memory, are accessible at the granularity of cache lines, key difference, however, is that the model allows for individual pro- and have the capability of surviving power outages. It is further cessors to fault at any time. If a processor faults, all of its processor motivated by the observation that in large parallel systems, failure state and local ephemeral memory is lost, but the persistent mem- of processors and their caches is not unusual.
    [Show full text]
  • Implementing Operational Intelligence Using In-Memory Computing
    Implementing Operational Intelligence Using In-Memory Computing William L. Bain ([email protected]) June 29, 2015 Agenda • What is Operational Intelligence? • Example: Tracking Set-Top Boxes • Using an In-Memory Data Grid (IMDG) for Operational Intelligence • Tracking and analyzing live data • Comparison to Spark • Implementing OI Using Data-Parallel Computing in an IMDG • A Detailed OI Example in Financial Services • Code Samples in Java • Implementing MapReduce on an IMDG • Optimizing MapReduce for OI • Integrating Operational and Business Intelligence © ScaleOut Software, Inc. 2 About ScaleOut Software • Develops and markets In-Memory Data Grids, software middleware for: • Scaling application performance and • Providing operational intelligence using • In-memory data storage and computing • Dr. William Bain, Founder & CEO • Career focused on parallel computing – Bell Labs, Intel, Microsoft • 3 prior start-ups, last acquired by Microsoft and product now ships as Network Load Balancing in Windows Server • Ten years in the market; 400+ customers, 10,000+ servers • Sample customers: ScaleOut Software’s Product Portfolio ® • ScaleOut StateServer (SOSS) ScaleOut StateServer In-Memory Data Grid • In-Memory Data Grid for Windows and Linux Grid Grid Grid Grid • Scales application performance Service Service Service Service • Industry-leading performance and ease of use • ScaleOut ComputeServer™ adds • Operational intelligence for “live” data • Comprehensive management tools • ScaleOut hServer® • Full Hadoop Map/Reduce engine (>40X faster*)
    [Show full text]
  • Models for Parallel Computation in Multi-Core, Heterogeneous, and Ultra Wide-Word Architectures
    Models for Parallel Computation in Multi-Core, Heterogeneous, and Ultra Wide-Word Architectures by Alejandro Salinger A thesis presented to the University of Waterloo in fulfillment of the thesis requirement for the degree of Doctor of Philosophy in Computer Science Waterloo, Ontario, Canada, 2013 c Alejandro Salinger 2013 I hereby declare that I am the sole author of this thesis. This is a true copy of the thesis, including any required final revisions, as accepted by my examiners. I understand that my thesis may be made electronically available to the public. iii Abstract Multi-core processors have become the dominant processor architecture with 2, 4, and 8 cores on a chip being widely available and an increasing number of cores predicted for the future. In ad- dition, the decreasing costs and increasing programmability of Graphic Processing Units (GPUs) have made these an accessible source of parallel processing power in general purpose computing. Among the many research challenges that this scenario has raised are the fundamental problems related to theoretical modeling of computation in these architectures. In this thesis we study several aspects of computation in modern parallel architectures, from modeling of computation in multi-cores and heterogeneous platforms, to multi-core cache management strategies, through the proposal of an architecture that exploits bit-parallelism on thousands of bits. Observing that in practice multi-cores have a small number of cores, we propose a model for low-degree parallelism for these architectures. We argue that assuming a small number of processors (logarithmic in a problem's input size) simplifies the design of parallel algorithms.
    [Show full text]
  • High Performance Computing Ð Past, Present and Future
    High Performance Computing – Past, Present and Future Anthony J. G. Hey University of Southampton, Southampton, UK 1 Introduction The New Technology Initiative of the Joint Information Systems Committee in the UK defined High Performance Computing (HPC) in the following terms [1]: “Computing resources which provide more than an order of magnitude more computing power than is normally available on one's desktop.” This is a useful definition of HPC – since it reflects the reality that HPC is a moving target: what is state of the art supercomputing this year will be desktop computing in a few years' time. Before we look towards the future for HPC, it is well worthwhile for us to spend a little time surveying the incredible technological progress in computing over the past 50 years. We will then quickly review some “Grand Challenge” scientific applications, followed by a discussion of the Fortran programming language. Fortran is the paradigmatic scientific programming language and in many respects the evolution of Fortran mirrors developments in computer architecture. After a brief look at the ambitious plans of IBM and Lawrence Livermore Laboratory in the USA to build a true “Grand Challenge” computer by 2004, we conclude with a look at the rather different types of application which are likely to make parallel computers a real commercial success. 2 The Past to the Present Historians of computing often begin by paying tribute to Charles Babbage and his famous Difference Engine – the first complete design for an automatic calculating device. The “Grand Challenge” problem that Babbage was attacking was the calculation of astronomical and nautical tables – a process that was extremely laborious and error-prone for humans.
    [Show full text]
  • Experiments with a Parallel External Memory System*
    Experiments with a Parallel External Memory System? Mohammad R. Nikseresht1, David A. Hutchinson2, and Anil Maheshwari1 1 School of Computer Science, Carleton University 2 Dept. of Systems and Computer Engineering, Carleton University Abstract. The theory of bulk-synchronous parallel computing has pro- duced a large number of attractive algorithms, which are provably op- timal in some sense, but typically require that the aggregate random access memory (RAM) of the processors be sufficient to hold the entire data set of the parallel problem instance. In this work we investigate the performance of parallel algorithms for extremely large problem instances relative to the available RAM. We describe a system, Parallel Exter- nal Memory System (PEMS), which allows existing parallel programs designed for a large number of processors without disks to be adapted easily to smaller, realistic numbers of processors, each with its own disk system. Our experiments with PEMS show that this approach is practi- cal and promising and the run times scale predictable with the number of processors and with the problem size. 1 Introduction In this work we investigate the performance of parallel algorithms for extremely large problem instances relative to the available Random Access Memory (RAM). Using theoretical results of [1, 2], we transform parallel algorithms designed for a large number of processors without disks to smaller, realistic numbers of pro- cessors, each with its own disk system. External Memory (EM) Algorithms: These algorithms are designed so that their run times scale predictably even as the size of their data increases far be- yond the size of internal RAM.
    [Show full text]
  • Fundamentals – Parallel Architectures, Models, and Languages
    HPC – Algorithms and Applications Fundamentals – Parallel Architectures, Models, and Languages Michael Bader TUM – SCCS Winter 2017/2018 Part I Parallel Architectures (sorry, not everywhere the latest ones . ) Michael Bader j HPC – Algorithms and Applications j Fundamentals j Winter 2017/2018 2 Manycore CPU – Intel Xeon Phi Coprocessor • coprocessor = works as an extension card on the PCI bus • ≈ 60 cores, 4 hardware threads per core • simpler architecture for each core, but • wider vector computing unit (8 double-precision floats) • next generation (Knights Landing) available as standalone CPU (since 2017) Michael Bader j HPC – Algorithms and Applications j Fundamentals j Winter 2017/2018 3 Manycore CPU – Intel “Knights Landing” 2nd half ’15 Unveiling Details of Knights Landing 1st commercial systems (Next Generation Intel® Xeon Phi™ Products) 3+ TFLOPS1 In One Package Platform Memory: DDR4 Bandwidth and Parallel Performance & Density Capacity Comparable to Intel® Xeon® Processors Compute: Energy-efficient IA cores2 … . Microarchitecture enhanced for HPC3 . 3X Single Thread Performance vs Knights Corner4 5 . Intel Xeon Processor Binary Compatible . Intel® Silvermont Arch. On-Package Memory: Enhanced for HPC . up to 16GB at launch . 1/3X the Space6 Integrated Fabric . 5X Bandwidth vs DDR47 . 5X Power Efficiency6 Processor Package Jointly Developed with Micron Technology All products, computer systems, dates and figures specified are preliminary based on current expectations, and are subject to change without notice. 1Over 3 Teraflops of peak theoretical double-precision performance is preliminary and based on current expectations of cores, clock frequency and floating point operations per cycle. FLOPS = cores x clock frequency x floating- point operations per second per cycle. 2Modified version of Intel® Silvermont microarchitecture currently found in Intel® AtomTM processors.
    [Show full text]
  • The Efficiency of Mapreduce in Parallel External Memory Arxiv
    The Efficiency of MapReduce in Parallel External Memory Gero Greiner Riko Jacob Institute of Theoretical Computer Science ETH Zurich, Switzerland {greinerg,rjacob}@inf.ethz.ch Abstract Since its introduction in 2004, the MapReduce framework has be- come one of the standard approaches in massive distributed and paral- lel computation. In contrast to its intensive use in practise, theoretical footing is still limited and only little work has been done yet to put MapReduce on a par with the major computational models. Follow- ing pioneer work that relates the MapReduce framework with PRAM and BSP in their macroscopic structure, we focus on the functionality provided by the framework itself, considered in the parallel external memory model (PEM). In this, we present upper and lower bounds on the parallel I/O-complexity that are matching up to constant factors for the shuffle step. The shuffle step is the single communication phase where all information of one MapReduce invocation gets transferred from map workers to reduce workers. Hence, we move the focus to- wards the internal communication step in contrast to previous work. The results we obtain further carry over to the BSP∗ model. On the one hand, this shows how much complexity can be “hidden” for an algo- rithm expressed in MapReduce compared to PEM. On the other hand, arXiv:1112.3765v1 [cs.DC] 16 Dec 2011 our results bound the worst-case performance loss of the MapReduce approach in terms of I/O-efficiency. 1 Introduction The MapReduce framework has been introduced by Dean and Ghemawat [5] to provide a simple parallel model for the design of algorithms on huge data sets.
    [Show full text]
  • The Power of In-Memory Computing: from Supercomputing to Stream Processing
    The Power of In-Memory Computing: From Supercomputing to Stream Processing William Bain, Founder & CEO ScaleOut Software, Inc. October 28, 2020 About the Speaker Dr. William Bain, Founder & CEO of ScaleOut Software: • Email: [email protected] • Ph.D. in Electrical Engineering (Rice University, 1978) • Career focused on parallel computing – Bell Labs, Intel, Microsoft ScaleOut Software develops and markets In-Memory Data Grids, software for: • Scaling application performance with in-memory data storage • Providing operational intelligence on live data with in-memory computing • 15+ years in the market; 450+ customers, 12,000+ servers 2 What Is In-Memory Computing? Generally accepted characteristics: • Comprises both hardware & software techniques. • Hosts data sets in primary memory. • Distributes computing across many servers. • Employs data-parallel computations. Why use IMC? • Can quickly process “live,” fast-changing data. • Can analyze large data sets. • “Scaling out” is more scalable and cost- effective than “scaling up”. 3 In the Beginning Caltech Cosmic Cube (1983) • Possibly the earliest in-memory computing system • Created by professors Geoffrey Fox and Charles Seitz • Targeted at solving scientific problems (high energy physics, astrophysics, chemistry, chip simulation) • 64 “nodes” with Intel 8086/8087 processors & 8MB total memory, hypercube interconnect, 3.2 MFLOPS • “One-tenth the power of the Cray 1 but 100X less expensive” 4 The Era of Commercialization Commercial Parallel Supercomputers • 1984: Industry pioneered
    [Show full text]
  • On the Complexity of List Ranking in the Parallel External Memory Model
    On the Complexity of List Ranking in the Parallel External Memory Model Riko Jacob1, Tobias Lieber1, and Nodari Sitchinava2 1 Institute for Theoretical Computer Science, ETH Z¨urich, Switzerland frjacob,[email protected] 2 Department of Information and Computer Sciences, University of Hawaii, USA [email protected] Abstract. We study the problem of list ranking in the parallel external memory (PEM) model. We observe an interesting dual nature for the hardness of the problem due to limited information exchange among the processors about the structure of the list, on the one hand, and its close relationship to the problem of permuting data, which is known to be hard for the external memory models, on the other hand. By carefully defining the power of the computational model, we prove a permuting lower bound in the PEM model. Furthermore, we present a stronger Ω(log2 N) lower bound for a special variant of the problem and for a specific range of the model parameters, which takes us a step closer toward proving a non-trivial lower bound for the list ranking problem in the bulk-synchronous parallel (BSP) and MapReduce models. Finally, we also present an algorithm that is tight for a larger range of parameters of the model than in prior work. 1 Introduction Analysis of massive graphs representing social networks using distributed pro- gramming models, such as MapReduce and Hadoop, has renewed interests in dis- tributed graph algorithms. In the classical RAM model, depth-first search traver- sal of the graph is the building block for many graph analysis solutions.
    [Show full text]