High Performance Computing Ð Past, Present and Future
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Paralellizing the Data Cube
PARALELLIZING THE DATA CUBE By Todd Eavis SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY AT DALHOUSIE UNIVERSITY HALIFAX, NOVA SCOTIA JUNE 27, 2003 °c Copyright by Todd Eavis, 2003 DALHOUSIE UNIVERSITY DEPARTMENT OF COMPUTER SCIENCE The undersigned hereby certify that they have read and recommend to the Faculty of Graduate Studies for acceptance a thesis entitled “Paralellizing the Data Cube” by Todd Eavis in partial fulfillment of the requirements for the degree of Doctor of Philosophy. Dated: June 27, 2003 External Examiner: Virendra Bhavsar Research Supervisor: Andrew Rau-Chaplin Examing Committee: Qigang Gao Evangelos Milios ii DALHOUSIE UNIVERSITY Date: June 27, 2003 Author: Todd Eavis Title: Paralellizing the Data Cube Department: Computer Science Degree: Ph.D. Convocation: October Year: 2003 Permission is herewith granted to Dalhousie University to circulate and to have copied for non-commercial purposes, at its discretion, the above title upon the request of individuals or institutions. Signature of Author THE AUTHOR RESERVES OTHER PUBLICATION RIGHTS, AND NEITHER THE THESIS NOR EXTENSIVE EXTRACTS FROM IT MAY BE PRINTED OR OTHERWISE REPRODUCED WITHOUT THE AUTHOR’S WRITTEN PERMISSION. THE AUTHOR ATTESTS THAT PERMISSION HAS BEEN OBTAINED FOR THE USE OF ANY COPYRIGHTED MATERIAL APPEARING IN THIS THESIS (OTHER THAN BRIEF EXCERPTS REQUIRING ONLY PROPER ACKNOWLEDGEMENT IN SCHOLARLY WRITING) AND THAT ALL SUCH USE IS CLEARLY ACKNOWLEDGED. iii To the two women in my life: Amber and Bailey. iv Table of Contents Table of Contents v List of Tables x List of Figures xi Abstract i Acknowledgements ii 1 Introduction 1 1.1 Overview of Primary Research . -
Historical Perspective and Further Reading 162.E1
2.21 Historical Perspective and Further Reading 162.e1 2.21 Historical Perspective and Further Reading Th is section surveys the history of in struction set architectures over time, and we give a short history of programming languages and compilers. ISAs include accumulator architectures, general-purpose register architectures, stack architectures, and a brief history of ARMv7 and the x86. We also review the controversial subjects of high-level-language computer architectures and reduced instruction set computer architectures. Th e history of programming languages includes Fortran, Lisp, Algol, C, Cobol, Pascal, Simula, Smalltalk, C+ + , and Java, and the history of compilers includes the key milestones and the pioneers who achieved them. Accumulator Architectures Hardware was precious in the earliest stored-program computers. Consequently, computer pioneers could not aff ord the number of registers found in today’s architectures. In fact, these architectures had a single register for arithmetic instructions. Since all operations would accumulate in one register, it was called the accumulator , and this style of instruction set is given the same name. For example, accumulator Archaic EDSAC in 1949 had a single accumulator. term for register. On-line Th e three-operand format of RISC-V suggests that a single register is at least two use of it as a synonym for registers shy of our needs. Having the accumulator as both a source operand and “register” is a fairly reliable indication that the user the destination of the operation fi lls part of the shortfall, but it still leaves us one has been around quite a operand short. Th at fi nal operand is found in memory. -
April 17-19, 2018 the 2018 Franklin Institute Laureates the 2018 Franklin Institute AWARDS CONVOCATION APRIL 17–19, 2018
april 17-19, 2018 The 2018 Franklin Institute Laureates The 2018 Franklin Institute AWARDS CONVOCATION APRIL 17–19, 2018 Welcome to The Franklin Institute Awards, the a range of disciplines. The week culminates in a grand United States’ oldest comprehensive science and medaling ceremony, befitting the distinction of this technology awards program. Each year, the Institute historic awards program. celebrates extraordinary people who are shaping our In this convocation book, you will find a schedule of world through their groundbreaking achievements these events and biographies of our 2018 laureates. in science, engineering, and business. They stand as We invite you to read about each one and to attend modern-day exemplars of our namesake, Benjamin the events to learn even more. Unless noted otherwise, Franklin, whose impact as a statesman, scientist, all events are free, open to the public, and located in inventor, and humanitarian remains unmatched Philadelphia, Pennsylvania. in American history. Along with our laureates, we celebrate his legacy, which has fueled the Institute’s We hope this year’s remarkable class of laureates mission since its inception in 1824. sparks your curiosity as much as they have ours. We look forward to seeing you during The Franklin From sparking a gene editing revolution to saving Institute Awards Week. a technology giant, from making strides toward a unified theory to discovering the flow in everything, from finding clues to climate change deep in our forests to seeing the future in a terahertz wave, and from enabling us to unplug to connecting us with the III world, this year’s Franklin Institute laureates personify the trailblazing spirit so crucial to our future with its many challenges and opportunities. -
Lynn Conway Professor of Electrical Engineering and Computer Science, Emerita University of Michigan, Ann Arbor, MI 48109-2110 [email protected]
IBM-ACS: Reminiscences and Lessons Learned From a 1960’s Supercomputer Project * Lynn Conway Professor of Electrical Engineering and Computer Science, Emerita University of Michigan, Ann Arbor, MI 48109-2110 [email protected] Abstract. This paper contains reminiscences of my work as a young engineer at IBM- Advanced Computing Systems. I met my colleague Brian Randell during a particularly exciting time there – a time that shaped our later careers in very interesting ways. This paper reflects on those long-ago experiences and the many lessons learned back then. I’m hoping that other ACS veterans will share their memories with us too, and that together we can build ever-clearer images of those heady days. Keywords: IBM, Advanced Computing Systems, supercomputer, computer architecture, system design, project dynamics, design process design, multi-level simulation, superscalar, instruction level parallelism, multiple out-of-order dynamic instruction scheduling, Xerox Palo Alto Research Center, VLSI design. 1 Introduction I was hired by IBM Research right out of graduate school, and soon joined what would become the IBM Advanced Computing Systems project just as it was forming in 1965. In these reflections, I’d like to share glimpses of that amazing project from my perspective as a young impressionable engineer at the time. It was a golden era in computer research, a time when fundamental breakthroughs were being made across a wide front. The well-distilled and highly codified results of that and subsequent work, as contained in today’s modern textbooks, give no clue as to how they came to be. Lost in those texts is all the excitement, the challenge, the confusion, the camaraderie, the chaos and the fun – the feeling of what it was really like to be there – at that frontier, at that time. -
The Computer Scientist As Toolsmith—Studies in Interactive Computer Graphics
Frederick P. Brooks, Jr. Fred Brooks is the first recipient of the ACM Allen Newell Award—an honor to be presented annually to an individual whose career contributions have bridged computer science and other disciplines. Brooks was honored for a breadth of career contributions within computer science and engineering and his interdisciplinary contributions to visualization methods for biochemistry. Here, we present his acceptance lecture delivered at SIGGRAPH 94. The Computer Scientist Toolsmithas II t is a special honor to receive an award computer science. Another view of computer science named for Allen Newell. Allen was one of sees it as a discipline focused on problem-solving sys- the fathers of computer science. He was tems, and in this view computer graphics is very near especially important as a visionary and a the center of the discipline. leader in developing artificial intelligence (AI) as a subdiscipline, and in enunciating A Discipline Misnamed a vision for it. When our discipline was newborn, there was the What a man is is more important than what he usual perplexity as to its proper name. We at Chapel Idoes professionally, however, and it is Allen’s hum- Hill, following, I believe, Allen Newell and Herb ble, honorable, and self-giving character that makes it Simon, settled on “computer science” as our depart- a double honor to be a Newell awardee. I am pro- ment’s name. Now, with the benefit of three decades’ foundly grateful to the awards committee. hindsight, I believe that to have been a mistake. If we Rather than talking about one particular research understand why, we will better understand our craft. -
Two-Level Main Memory Co-Design: Multi-Threaded Algorithmic Primitives, Analysis, and Simulation
Two-Level Main Memory Co-Design: Multi-Threaded Algorithmic Primitives, Analysis, and Simulation Michael A. Bender∗x Jonathan Berryy Simon D. Hammondy K. Scott Hemmerty Samuel McCauley∗ Branden Moorey Benjamin Moseleyz Cynthia A. Phillipsy David Resnicky and Arun Rodriguesy ∗Stony Brook University, Stony Brook, NY 11794-4400 USA fbender,[email protected] ySandia National Laboratories, Albuquerque, NM 87185 USA fjberry, sdhammo, kshemme, bjmoor, caphill, drresni, [email protected] zWashington University in St. Louis, St. Louis, MO 63130 USA [email protected] xTokutek, Inc. www.tokutek.com Abstract—A fundamental challenge for supercomputer memory close to the processor, there can be a higher architecture is that processors cannot be fed data from number of connections between the memory and caches, DRAM as fast as CPUs can consume it. Therefore, many enabling higher bandwidth than current technologies. applications are memory-bandwidth bound. As the number 1 of cores per chip increases, and traditional DDR DRAM While the term scratchpad is overloaded within the speeds stagnate, the problem is only getting worse. A computer architecture field, we use it throughout this variety of non-DDR 3D memory technologies (Wide I/O 2, paper to describe a high-bandwidth, local memory that HBM) offer higher bandwidth and lower power by stacking can be used as a temporary storage location. DRAM chips on the processor or nearby on a silicon The scratchpad cannot replace DRAM entirely. Due to interposer. However, such a packaging scheme cannot contain sufficient memory capacity for a node. It seems the physical constraints of adding the memory directly likely that future systems will require at least two levels of to the chip, the scratchpad cannot be as large as DRAM, main memory: high-bandwidth, low-power memory near although it will be much larger than cache, having the processor and low-bandwidth high-capacity memory gigabytes of storage capacity. -
Minimizing Writes in Parallel External Memory Search
Proceedings of the Twenty-Third International Joint Conference on Artificial Intelligence Minimizing Writes in Parallel External Memory Search Nathan R. Sturtevant and Matthew J. Rutherford University of Denver Denver, CO, USA fsturtevant, [email protected] Abstract speed in Chinese Checkers, and is 3.5 times faster in Rubik’s Cube. Recent research on external-memory search has shown that disks can be effectively used as sec- WMBFS is motivated by several observations: ondary storage when performing large breadth- first searches. We introduce the Write-Minimizing First, most large-scale BFSs have been performed to ver- Breadth-First Search (WMBFS) algorithm which ify the diameter (the number of unique depths at which states is designed to minimize the number of writes per- can be found) or the width (the maximum number of states at formed in an external-memory BFS. WMBFS is any particular depth) of a state space, after which any com- also designed to store the results of the BFS for puted data is discarded. There are, however, many scenarios later use. We present the results of a BFS on a in which the results of a large BFS can be later used for other single-agent version of Chinese Checkers and the computation. In particular, a breadth-first search is the under- Rubik’s Cube edge cubes, state spaces with about lying technique for building pattern databases (PDBs), which 1 trillion states each. In evaluating against a com- are used as heuristics for search. PDBs require that the depth parable approach, WMBFS reduces the I/O for the of each state in the BFS be stored for later usage. -
Introducción a La Ingeniería Electrónica
7-feb-07 MODULO INTRODUCCIÓN A LA INGENIERÍA ELECTRÓNICA MARCOS GONZÁLEZ PIMENTEL UNIVERSIDAD NACIONAL ABIERTA Y A DISTANCIA UNAD BOGOTA 2006 1 ÍNDICE PRIMERA UNIDAD FUNDAMENTACIÓN DE LA INGENIERÍA ELECTRÓNICA CAPÍTULOS 0. INTRODUCCIÓN. CAPÍTULOS 1 CONCEPTUALIZACIÓN 1.1 CIENCIA 1.1.1 Definición 1.1.2 Objetivos 1.1.3 Características básicas de la ciencia . 1.1.4 Ciencia y tecnología 1.1.5 Tipos de Ciencia 1.2 Ingeniería y Tecnología 1.2.1 Definición de Ingeniería 1.2.2 Funciones de la Ingenieria 1.2.3 Ramas de la Ingeniería 1.2.4 Definición de Tecnología 1.3 Ingeniería y Tecnología Electrónica 1.3.1 Definición 1.3.2 Objetivos 1.4 Sistema 1.4.1 Definición 1.4.2 Características y clases de los sistemas CAPITULO 2 ANTECEDENTES 2.1 Historia de la Ingeniería 2.1.1. Historia de la Ingeniería en el mundo 2.1.2. Historia de la ingeniería en Colombia. 2.2 Historia de la electrónica 2.2.1. Historia de la electrónica en el mundo. 2.2.2. Historia de la electrónica en Colombia . CAPITULO 3 ACTUALIDAD 2 3.1 Actualidad de la Ingeniería . 3.1.1 Actualidad de la Ingeniería el mundo . 3.1.2 Actualidad de la Ingeniería en Colombia . 3.2 Actualidad de la electrónica 3.2.1 La Electrónica en el mundo . 3.2.2 La Electrónica en Colombia CAPITULO 4 APLICACIONES 4.1 Industriales. 4.1.1 Definición 4.1.2 Estado del arte. 4.2 Robótica. 4.2.1 Definición 4.2.2 Estado del arte . 4.3 Automatización . -
David Donoho. 50 Years of Data Science. Journal of Computational
Journal of Computational and Graphical Statistics ISSN: 1061-8600 (Print) 1537-2715 (Online) Journal homepage: https://www.tandfonline.com/loi/ucgs20 50 Years of Data Science David Donoho To cite this article: David Donoho (2017) 50 Years of Data Science, Journal of Computational and Graphical Statistics, 26:4, 745-766, DOI: 10.1080/10618600.2017.1384734 To link to this article: https://doi.org/10.1080/10618600.2017.1384734 © 2017 The Author(s). Published with license by Taylor & Francis Group, LLC© David Donoho Published online: 19 Dec 2017. Submit your article to this journal Article views: 46147 View related articles View Crossmark data Citing articles: 104 View citing articles Full Terms & Conditions of access and use can be found at https://www.tandfonline.com/action/journalInformation?journalCode=ucgs20 JOURNAL OF COMPUTATIONAL AND GRAPHICAL STATISTICS , VOL. , NO. , – https://doi.org/./.. Years of Data Science David Donoho Department of Statistics, Stanford University, Standford, CA ABSTRACT ARTICLE HISTORY More than 50 years ago, John Tukey called for a reformation of academic statistics. In “The Future of Data science Received August Analysis,” he pointed to the existence of an as-yet unrecognized , whose subject of interest was Revised August learning from data, or “data analysis.” Ten to 20 years ago, John Chambers, Jeff Wu, Bill Cleveland, and Leo Breiman independently once again urged academic statistics to expand its boundaries beyond the KEYWORDS classical domain of theoretical statistics; Chambers called for more emphasis on data preparation and Cross-study analysis; Data presentation rather than statistical modeling; and Breiman called for emphasis on prediction rather than analysis; Data science; Meta inference. -
Arxiv:2106.11534V1 [Cs.DL] 22 Jun 2021 2 Nanjing University of Science and Technology, Nanjing, China 3 University of Southampton, Southampton, U.K
Noname manuscript No. (will be inserted by the editor) Turing Award elites revisited: patterns of productivity, collaboration, authorship and impact Yinyu Jin1 · Sha Yuan1∗ · Zhou Shao2, 4 · Wendy Hall3 · Jie Tang4 Received: date / Accepted: date Abstract The Turing Award is recognized as the most influential and presti- gious award in the field of computer science(CS). With the rise of the science of science (SciSci), a large amount of bibliographic data has been analyzed in an attempt to understand the hidden mechanism of scientific evolution. These include the analysis of the Nobel Prize, including physics, chemistry, medicine, etc. In this article, we extract and analyze the data of 72 Turing Award lau- reates from the complete bibliographic data, fill the gap in the lack of Turing Award analysis, and discover the development characteristics of computer sci- ence as an independent discipline. First, we show most Turing Award laureates have long-term and high-quality educational backgrounds, and more than 61% of them have a degree in mathematics, which indicates that mathematics has played a significant role in the development of computer science. Secondly, the data shows that not all scholars have high productivity and high h-index; that is, the number of publications and h-index is not the leading indicator for evaluating the Turing Award. Third, the average age of awardees has increased from 40 to around 70 in recent years. This may be because new breakthroughs take longer, and some new technologies need time to prove their influence. Besides, we have also found that in the past ten years, international collabo- ration has experienced explosive growth, showing a new paradigm in the form of collaboration. -
Alan Mathison Turing and the Turing Award Winners
Alan Turing and the Turing Award Winners A Short Journey Through the History of Computer TítuloScience do capítulo Luis Lamb, 22 June 2012 Slides by Luis C. Lamb Alan Mathison Turing A.M. Turing, 1951 Turing by Stephen Kettle, 2007 by Slides by Luis C. Lamb Assumptions • I assume knowlege of Computing as a Science. • I shall not talk about computing before Turing: Leibniz, Babbage, Boole, Gödel... • I shall not detail theorems or algorithms. • I shall apologize for omissions at the end of this presentation. • Comprehensive information about Turing can be found at http://www.mathcomp.leeds.ac.uk/turing2012/ • The full version of this talk is available upon request. Slides by Luis C. Lamb Alan Mathison Turing § Born 23 June 1912: 2 Warrington Crescent, Maida Vale, London W9 Google maps Slides by Luis C. Lamb Alan Mathison Turing: short biography • 1922: Attends Hazlehurst Preparatory School • ’26: Sherborne School Dorset • ’31: King’s College Cambridge, Maths (graduates in ‘34). • ’35: Elected to Fellowship of King’s College Cambridge • ’36: Publishes “On Computable Numbers, with an Application to the Entscheindungsproblem”, Journal of the London Math. Soc. • ’38: PhD Princeton (viva on 21 June) : “Systems of Logic Based on Ordinals”, supervised by Alonzo Church. • Letter to Philipp Hall: “I hope Hitler will not have invaded England before I come back.” • ’39 Joins Bletchley Park: designs the “Bombe”. • ’40: First Bombes are fully operational • ’41: Breaks the German Naval Enigma. • ’42-44: Several contibutions to war effort on codebreaking; secure speech devices; computing. • ’45: Automatic Computing Engine (ACE) Computer. Slides by Luis C. -
The Parallel Persistent Memory Model
The Parallel Persistent Memory Model Guy E. Blelloch∗ Phillip B. Gibbons∗ Yan Gu∗ Charles McGuffey∗ Julian Shuny ∗Carnegie Mellon University yMIT CSAIL ABSTRACT 1 INTRODUCTION We consider a parallel computational model, the Parallel Persistent In this paper, we consider a parallel computational model, the Par- Memory model, comprised of P processors, each with a fast local allel Persistent Memory (Parallel-PM) model, that consists of P pro- ephemeral memory of limited size, and sharing a large persistent cessors, each with a fast local ephemeral memory of limited size M, memory. The model allows for each processor to fault at any time and sharing a large slower persistent memory. As in the external (with bounded probability), and possibly restart. When a processor memory model [4, 5], each processor runs a standard instruction set faults, all of its state and local ephemeral memory is lost, but the from its ephemeral memory and has instructions for transferring persistent memory remains. This model is motivated by upcoming blocks of size B to and from the persistent memory. The cost of an non-volatile memories that are nearly as fast as existing random algorithm is calculated based on the number of such transfers. A access memory, are accessible at the granularity of cache lines, key difference, however, is that the model allows for individual pro- and have the capability of surviving power outages. It is further cessors to fault at any time. If a processor faults, all of its processor motivated by the observation that in large parallel systems, failure state and local ephemeral memory is lost, but the persistent mem- of processors and their caches is not unusual.