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Stability Analysis in Multiple Loop Systems

Prepared by Christophe Basso, Stéphanie Conseil, Nicolas Cyr

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Loop stability analysis usually starts from an open-loop with single loops, the operation becomes more complicated Bode plot of the plant under study, e.g. the power stage of a with converters implementing weighted feedback. This buck or a flyback converter. From this diagram, the designer paper capitalizes on the Ref. [1] work and explores different can extract phase and gain data within the frequency range ways to apply the technique to power converters featuring of interest. His job then consists in identifying a multiple feedback paths. compensator structure which will lead to the selected crossover frequency affected by the right phase margin. The The TL431, a Multiple Loop System final step requires the study of the total loop gain, the power The TL431 alone, can be modeled as a multiple loop plant followed by the compensator, showing that the feedback system. Figure 1 shows a TL431 classically wired poles/zeros placed on the compensator ensure stability once in a type-2 configuration, as described in Ref. [2]. From this the loop is closed. If this operation is rather straightforward schematic, one can identify so-called slow and fast lanes.

Vout Vdd Rled R2 1 k 10 k Rpullup 20 k Fast Slow Lane Lane FB C1 U2B 100 nF C2 U2A 1 nF U1 TL431 R3 10 k

Primary Side Secondary Side

Figure 1. A TL431 Wired in a Classical Configuration, Observing the dc Voltage of a Converter

The TL431 can be seen as a programmable zener also voltage. Therefore, even if you increase C1, it has no effect called a shunt regulator. When the output voltage changes, in rolling off the loop gain since Rled always senses the e.g. because of a load variation, the information is conveyed output voltage. The transfer function of such a system can be to the inverting input of the TL431 via R2/R3 and asks the written in the following form [2]: programmable zener to pump more or less current into the VFB(s) 1 optocoupler LED. It does so by adjusting its cathode + G (s)ǒ1 ) Ǔ (eq. 1) V (s) 1 sR C voltage. By this way, the feedback signal observed on the out 2 1 primary side also changes and instructs the controller to alter where G1(s) represents the mid-band gain brought by the its operating point. If the output voltage variations are too optocoupler CTR, the LED and the pull-up resistors fast, the frequency sensed by R2 exceeds the pole position associated to the capacitor C2. From this expression, we can introduced by C1 and the ac contribution of this path to the actually see the presence of two loops by developing feedback signal becomes null: the TL431 no longer changes Equation1: its operating point and the LED cathode is now fixed. V (s) G (s) FB + ) 1 However, as the LED cathode is fixed, the anode still senses G1(s) (eq. 2) Vout(s) sR2C1 an output voltage variation via Rled. This current variation propagates via the optocoupler and affects the feedback

© Semiconductor Components Industries, LLC, 2008 1 Publication Order Number: April, 2008 - Rev. 0 AND8327/D AND8327/D

The loop gain of such a system could be measured by In this schematic, it is not possible to sweep both inputs breaking the loop at the feedback point. Unfortunately, together as they are separated by the LC filter. Fortunately, depending on the converter configuration, this solution can we can apply the superposition theorem as we are dealing sometimes be difficult to implement. The best is then to with a linear system. At first, we will sweep the slow lane measure the loop gain from the secondary side. In this while keeping the fast lane to a bias level, totally particular example, both the fast and slow lanes share a disconnected from the output voltage. A dc voltage supplied similar entry point. The total loop gain could therefore be by an external source will do. This is what Figure 4 shows. measured as suggested by Figure 2: The precision of the 5 V source is not relevant here as it only serves bias purposes. The ac source actually represents an Vout injection transformer, classically used in loop stability V1 studies. The A and B probes go to a network analyzer which AC = 1 will compute + 20 log ǒBǓ, Rled R2 10 A 1 k 10 k displaying a loop gain equal to Fast Slow G1(s) Lane Lane sR2C1 C1 100 nF U2B L1 Vout

U1 Vsweep TL431 R3 10 k AC = 1 V + + Rled Vext 1 k 5 V Figure 2. When Both Slow and Fast Lanes are R2 Fast B A 10 k Connected Together, the Measurement is Easy to Run Lane Slow C1 + A stimulus source is inserted in series with the output Lane Cout U2B 100 nF voltage and both slow and fast lanes are ac swept. The 220 mF voltage observed on the feedback pin is therefore proportional to both inputs and is representative of what U1 Equations1 and 2 predict. TL431 R3 In Figure 3, we can see the presence of a LC filter, added 10 k to remove unwanted high frequency spikes, typical of a flyback converter. Figure 4. The Fast Lane is ac Disconnected from the Vout Circuit and Only the Slow Lane Receives a Stimulus Rled L1 R2 1 k 10 k Then, once the plot is saved, the configuration needs to be Fast Slow changed to the other input, as suggested by Figure 5. In this Lane Lane circuit, the upper R2 terminal is connected to a dc voltage C1 + whose value must equal the regulated voltage whereas the Cout 100 nF U2B 220 mF fast lane input is now ac swept:

U1 TL431 R3 10 k

Figure 3. The Presence of the LC Filter Splits Both Lanes

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L1 + ö ) ö + (eq. 5) Vout Re(VFB) A1 cos 1 A2 cos 2 X

+ ö ) ö + (eq. 6) Vsweep Im(VFB) A1 sin 1 A2 sin 2 Y AC = 1 V + Vext The rotating vector obtained at the end will be of the 5 V + following form: Rled R2 V + X ) jY (eq. 7) 1 k 10 k FB B A Where we can now extract a module and an argument: Fast Slow Lane Lane ø ø+ Ǹ 2 ) 2 (eq. 8) VFB Y X C1 + Cout *1 Y U2B 100 nF arg V + tan ǒ Ǔ (eq. 9) 220 mF FB X Plotting 20log10 of Equation 8 and the phase returned by U1 Equation9 should give the Bode plot we are looking for. TL431 R3 10 k SPICE Application Before rushing to the laboratory to apply this technique, let's give it a try with a SPICE simulation and check that our Figure 5. The Fast Lane is Now ac Swept as the equations give the correct answers. Figure 6 depicts the Slow Lane is Simply dc Biased TL431 circuit ready to be ac swept, both inputs being connected together. The sweep technique uses an old trick The dc adjustment might be a little difficult given the with L1 and C3 which open the loop in ac but keep it closed open-loop gain brought by the TL431 and the sensitivity on in dc. The closed path in dc helps to automatically adjust the the external bias. The network analyzer still computes voltage on the upper terminal of R2 to obtain a 2.5 V on the feedback output, right in the middle of the available 20log10(B/A) for the fast lane but this time, it plots a loop dynamic. This ensures a circuit properly biased without the gain equal to G1(s). need to tweak anything else. The bias points appearing in Combining Signals Together Figure6 confirms the right values. Once the ac sweep is run Once we have both slow and fast lanes loop plots on the the Bode diagram appears in Figure 7 and confirms the screen, how can we combine them? Can we just sum up the presence of an origin pole, a low frequency zero, a high gain and phase diagrams, respectively expressed in dB and frequency pole and a mid-band gain in between. The phase degrees? Certainly not, it would correspond to cascaded gain boost peaks to 134° at a frequency of 380 Hz where the gain blocks and not paralleled paths. We need to vector sum both reaches 23dB. Now, let us separate the two lanes by output signals and reconstruct the final signal which applying the technique we described earlier. The exploration expresses the combination of both loops. Using Euler of the fast lane requires a simple dc bias on the divider notation, we can express the slow lane signal by a rotating network, again provided by the operational amplifier. vector affected by a module A1 and a phase ϕ1: Figure8 portrays the circuit we have implemented. The modulation signal enters the fast lane through the ac source V + A (cosö ) j sin ö ) (eq. 3) out,slow 1 1 1 Vsweep whereas L1 and C4 prevent any injection in the slow Using a similar notation, we can write the fast lane lane: both loops are fully decoupled from each others. For expression: the slow lane sweep, Figure 9 shows the adopted sketch: the upper LED resistor is simply hooked to a dc source and the + ö ) ö (eq. 4) Vout,fast A2(cos 2 j sin 2) ac stimulus now sweeps the slow lane through the LC To reconstruct and plot the final gain curve combining network. Again, there is no ac link between both inputs. both signals − the signal observed on the feedback pin once all loops are closed − we need to separate the real and imaginary portions of the two lanes and sum them together:

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2.5 V Vdd 5.0 V 4.99 V L1 1 kH + FB 5 10 4 9 - + 4.99 V 2.5 V Rled R2 C3 Rpullup X3 8 1 k 10 k 1 kF AMPSIMP + 20 k V2 1 37 FB 2.49 V 2.5 4.86 V 0 V VFB X1 2.5 V + Optocoupler Vsweep AC = 1 C2 3.78 V 10 n C1 100 nF 6

U1 TL431 R3 10 k

Figure 6. The Type 2 Compensator Based on a TL431 and Adapted for a SPICE Simulation

1 vdbfb 2 ph_vfb

60.0 Loop gain (dB)

40.0

20.0

Plot1 23 dB

0 vdbfb in db(volts)

-20.0 1

150 Phase (°)

130

110 °

Plot2 41

90.0

ph_vfb in degrees 2

70.0

10 100 1k 10k 100k frequency in hertz Figure 7. ac Results of the Type 2 Compensator, Highlighting the Presence of Two Poles and One Zero

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Vsweep AC = 1 5 + X3 AMPSIMP 5.0 V C4 Vdd 5.0 V 4.99 V L1 1 kH + FB 10 5 + 4 2 4.99 V 9 - Rled 1 kF R2 2.5 V Rpullup 8 1 k 10 k + 20 k V2 1 3 FB 2.5 4.87 V 2.49 V VFB 2.5 V X1 Optocoupler

C2 3.79 V 10 n C1 100 nF 6

U1 TL431 R3 10 k

Figure 8. The Fast Lane Sweep Requires a Clear Separation between Both Lanes

Vbias 5 + X3 AMPSIMP 5.0 V Vdd 5.0 V 4.99 V L1 1 kH + FB 5 10 4 9 - + 2 4.99 V 2.5 V Rled R2 C3 Rpullup 8 1 k 10 k 1 kF + 20 k V2 1 37 FB 2.5 4.87 V 2.49 V 0 V VFB X1 2.5 V + Optocoupler Vsweep AC = 1 C2 3.79 V 10 n C1 100 nF 6

U1 TL431 R3 10 k

Figure 9. In the Slow Lane Sweep, the Fast Lane Input Goes to a Fixed dc Bias

SPICE offers the possibility to extract the imaginary and of the figure contains the imaginary portions of both lanes. real parts from an ac simulation. This is what Figure10 The graphical viewer can easily manipulate waveforms and shows where the real curves of both the fast and slow sweeps the sum of both imaginary and real curves already appears have been gathered in the upper portion. The lower section on the picture.

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1 re_fast 2 im_fast 3 re_slow 4 im_slow 5 sum 6 sum

5.00 Re_slow 315 -5.00

Re_fast -15.0 Plot1

-25.0

Re_fast + Re_slow (Y)

sum, re_fast, re_slow in volts -35.0

160

120

Im_slow + Im_fast (X) 80.0 Plot2

40.0

Im_fast sum, im_slow, im_fast in volts sum, im_slow, 0 426 Im_slow 10 100 1k 10k 100k frequency in hertz Figure 10. This Plot Gathers the Real and Imaginary Portions of the Feedback Signal Collected when the Fast and Slow Lanes are Separately ac Swept

Once we reached that point, we can apply Equations8 compared to Figure 7. They are identical gain wise and9 via the graphical viewer internal script. The resulting (Figure11), despite different signs on the phase in Figure12 waveforms are displayed on Figures 11 and 12 then (the tan-1 function is modulo 180°).

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1 p 5 sum 6 sum#a

0 200 5 Y

-10.0 100

-20.0 0 6

Plot1 X sum in volts

-30.0 sum#a in volts -100

-40.0 -200

22 60.0 20log10 YX+

40.0

20.0

Plot3 23 dB

pin unknown 0 p=20*log((sqrt(w5*w5+w6*w6))) -20.0 plot ”p” 1

10 100 1k 10k 100k frequency in hertz Figure 11. Once Mathematical Calculations are Made, the Amplitude Response Reveals the Classical Type 2 Function we are Looking For

1 p 5 sum 6 sum#a

0 200 5 Y

-10.0 100

-20.0 0 6

Plot1 X sum in volts -30.0 sum#a in volts -100

-40.0 -200

1 -50.0 p=atan(w6/w5) plot ”p” -60.0

-70.0

Plot3 41°

pin unknown -80.0 tan*1ǒXǓ Y -90.0

10 100 1k 10k 100k frequency in hertz Figure 12. Calculating the Argument Leads to a Similar Result for the Phase, Showing a Boost of 415

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Combining Data with a Network Analyzer, a Real Case Example To check the validity of our assumptions, we have built a connected to the reference voltage. Figure 13 shows the 65W power supply based on a classical UC3843 controller. adopted schematic: The internal op-amp is disabled via a pull-up resistor

T1 86H-6232 0.18 : 1 : 0.25 HV-bulk R19 R3 R13 C2 10 n MBR20100 L2 2.2 m C4 47 k 47 k 47 k D5 + C11 400 V 100 mF + + C7 + 400 V MUR160 1 nF 220 mF D2 C5a Vout Vref 25 V +- R7 20 k 1.2 mF R17 25 V Gnd IC4 R6 6 k 47 k KBU4K Type = Y1 C13 1 8 C5b CMP Ref R1 1N4937 2.2 nF 1.2 mF 2 FB Vcc 7 IN 330 D8 M1 25 V 3 CS DRV 6 SPP11N60S5 2 x 10 mH 4 Rt GND 5 R16 R8 R14 R12 L1 Schaffner 10 R18 1 k 4.7 k 10 k RN122-1.5/02 U3B U1 47 k UC3843 U3A X2 R10 C10 470 n R5 47 n 56 k + 1 k C6 R23 R24 C3 R6a R6b 220 mF IC2 R9 C12 1 1 1 Meg 1 Meg C16 C15 TL431 10 k 4.7 nF 10 nF 85 - 260 Vac 220 p Gnd Figure 13. The Schematic of the 19 V/3 A Adapter Features a UC3843 with a TL431 on the Secondary Side

The output voltage is regulated by a TL431 wired in a in the first part of this document. The main advantage of this type2 configuration. The fast lane (optocoupler lane) and method lies in the measurement operations confined on the the slow lane (TL431 resistor divider) are separated by an isolated secondary side only. LC filter which is placed to further attenuate the various We will first start by sweeping the slow lane, while the fast high-frequency output spikes inherent to the flyback stages. lane is biased to 19 V (output voltage value) with a dc In order to measure the loop response of our adapter with a voltage source (Figure 14): network analyzer, we are going to use the method described

OUT

Lfilt Cout Cfilt 2.2 m RLoad 2.4 m 100 m Gnd

Gnd Vdd Loop Output

19 V R6 Rpullup 33 Network Analyzer 20 k Source Ch A Ch B Rled 1 k Loop Input Isolator

FB Rupper Czero 66 k

Cpole 47 n 1 n Rlower 10 k

Gnd Figure 14. The Slow Lane is Individually Biased while the Second Loop is ac Swept

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The injection voltage source is implemented with a 20log ǒChBǓ wideband isolation device and a 33 W resistor. Voltage 10 ChA probes are used to measure the loop input and output signals We obtained the Bode plots shown in Figure 15. with respect to ground. The network analyzer directly computes

Slow lane loop response 100 180 slow lane - gain slow lane - phase 80 144

60 108

40 72

20 36 ) ° 0 0 Phase ( Mag (dB) -20 -36

-40 -72

-60 -108

-80 -144

-100 -180 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 Freq (Hz) Figure 15. Slow Lane Loop Response Obtained with the Network Analyzer

p The slow lane loop gain starts with a -1 slope because of + A ń20 ǒö Ǔ x1 10 1 cos 1 (eq. 11) the origin pole formed by (Rupper = R12+R10, Czero = C6). 180 The power stage pole fp is around 20 Hz and corresponds to: and 1 f + ń p p p y + 10A1 20 sinǒö Ǔ (eq. 12) RloadCout 1 1 180 where Rload is the output load resistor and Cout is the sum of The Excel syntax corresponding to these equations are: C and C (Figure 13). After f , the power stage gain 5a 5b p x + POWER(10; A ń20) @ COS(ö @ PI()ń180) (eq. 13) decreases with a -2 slope until it reaches the 8 kHz pole 1 1 1 + ń @ ö @ ń formed by (Rpullup, Cpole) of our type 2 compensator: x2 POWER(10; A1 20) SIN( 1 PI() 180) (eq. 14) + 1 Further to slow lane measurement, we have to run the fpc p 2 RpullupCpole same operation for the fast lane loop. We inject the ac signal Now that we have the slow lane loop plot, we can paste the in the fast lane while the slow lane is disconnected from the network analyzer data into excel. We have a 3-column data output voltage and biased with a dc voltage source. This dc table with the frequency (Hz), magnitude (dB) and phase voltage must be manually adjusted to fix the operating point (degrees). Using Euler notation, we will calculate the real corresponding to the output load used. As the TL431 is very and the imaginary part of the slow lane vector: sensitive to small voltage variations, we can use a resistor between the dc source and the resistor divider to adjust the + ö ) ö + ) (eq. 10) Vout,slow A1(cos 1 j sin 1) x1 jy1 output voltage (See Figure 16). Excel will compute the following formulas:

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OUT Lfilt 2.2 m

Cfilt RLoad Loop Output 100 m Gnd Network Analyzer R6 Ch B Ch A Source 33 Gnd

Isolator Loop Input Vdd DC Voltage Rled R7 Rpullup 1 k ~19 V 20 k 20 k Rupper FB Czero 66 k

47 n Cpole Rlower 1 n 10 k

Gnd

Figure 16. For the fast lane sweep, the slow lane is ac-decoupled from the converter output. Care must be taken to avoid output runaway during this measurement!

Figure 17 details the fast lane loop response. The power + 1 fpc p stage pole fp is around 20 Hz and corresponds to: 2 RpullupCpole + 1 On Figure 13 schematic, Cpole corresponds to C11 and the fp p RloadCout Rpullup resistor is R7. After fp, the power stage gain decreases with a -1 slope until it reaches the 8 kHz pole formed by (Rpullup, Cpole) of our type 2 compensator:

Fast lane loop response 100 180 fast lane - gain 80 144 fast lane - phase

60 108

40 72

20 36 ) °

0 0 Phase ( Mag (dB) -20 -36

-40 -72

-60 -108

-80 -144

-100 -180 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 Freq (Hz) Figure 17. Fast Lane Loop Response Obtained with the Network Analyzer. The Slow Lane is Externally Biased with a dc Power Supply

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Once the network analyzer data has been exported to + ) ) ) + ) (eq. 17) V (x1 x2) j(y1 y2) X jY Excel, we compute the real and the imaginary parts of the FB Finally, we extract the final loop gain and phase by fast lane loop vector: entering Equations 8 and 9 in Excel: A ń20 p x + 10 2 cosǒö Ǔ (eq. 15) + ƞ ) ƞ (eq. 18) 2 2 180 Loopgain 20 * LOG(SQRT(X 2 Y 2); 10)

ń p Loop + DEGREES(ATAN(YńX)) (eq. 19) y + 10A2 20 sinǒö Ǔ (eq. 16) phase 2 2 180 Then we can sum the real and the imaginary contributions Figure 18 shows the reconstructed loop gain and phase plots. to obtain the total loop vector:

Loop gain and phase 60 170 Final Mag (dB) Final Phase 40 120

70 20

20 0

-30

-20 Phase (deg) Magnitude (dB) -80

-40 -130

-60 -180 10 100 1000 10000 100000

Freq (Hz) Figure 18. The Final Bode Plot Combines the Information Obtained from Individual Loop Measurements

Because the arctangent function is defined on a ]-90°; Weighted Feedback on a Forward Converter +90°[ interval, some parts of the resulting curve could Let's now apply a similar methodology to a multi-output exhibit a negative phase rotation caused by the calculation. power supply: in such an application, two different voltage We have corrected these particular points by adding 180° to outputs are regulated using a common TL431, using a their phase calculation result. The reconstructed Bode plot weighted sum configuration (see Figure 19). The resistors shows a clean response and does not differ from classical connecting each output to the TL431 reference pin are loop analysis carried on a current-mode converter. calculated taking into account a relative weight of each output in the feedback.

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Vdd Vout 1

Rled Slow Rpullup Lane 1 Fast Vout 2 Lane R2 U2B R1 Slow C1 Lane 2 C2

U2A U1 R3 TL431

Primary Side Secondary Side

Figure 19. The TL431 Wired in a Two-output Weighted Feedback Configuration

This technique offers a way to improve cross-regulation and Figure 20 represents a simplified two-output version of in a multi-output converter by affecting a weight to certain such a converter. In this 2-switch forward converter, the two outputs whose precision or load constraints are more outputs (5 V and 12 V) are also coupled via their respective important than the others. Of course, the sum of all weight output inductors. Each output contributes to 50% in the must equal 100% at the end. In the ATX world, weighted control loop, which uses a TL431 featuring a type 2 feedback is often encountered in the so-called Silver boxes compensation.

R8 C4 350 V 1 n D5 IRF350 10 1N4148 R3 L4 5 V/ 0.47 m 15 A C1 T6 47 M1 MBR4045 Q1 R11 D7 220 n R2 1 k R7 C21 47 k T4 C7 C20 10 m m 1 m 2200 2200 D1 2N2907 D3 C3 L1 C22 1N5818 MUR460 1 n 220 m D4 MUR460 R10 27 C6 IRF350 L3 D6 MBR40H100 470 p 12 V/ 0.47 m 1N4148 R5 15 A D8 R9 47 M2 27 C8 C19 DRV Q2 R12x C5 R4 1 k 2200 m 1200 m 47 k 470 p

CS R12d 2N2907 Vdd R13 R100 1 k R6 1 k 10 C7d 0.3 R101 180 p 5 k R14 R31 10 1 k 62 k FB ISO1 SFH610A 100 n C9 R12 C4d 25.8 k C10 D9 VCC 1 n R16 4.7 m TL431 10 k

Figure 20. Schematic of the Two-switch Forward Power Supply featuring a Weighted Feedback with TL431

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There are 2 loops we need to measure: one is a combination of the fast and slow lanes observing the +12 V output. The other one is the +5 V loop entering the TL431 via the slow lane. We have mentioned before that measuring the loop at the feedback input of the controller is not practical. As demonstrated in Ref. [3], in order to correctly measure the gain and phase of the feedback loop, the ac stimulus must be injected between a low impedance node (on the power supply output side) and a high impedance node (on the control side). When the injection is done as described previously, i.e. between the output of the power supply and the feedback circuitry, the condition is optimal: the output impedance of the observed point is low, and the input impedance of the feedback path is high. But if we want to open the loop between the optocoupler and the feedback pin of the controller, the conditions are not favorable: the output impedance of the optocoupler is high (this is the pull up resistor in a common-emitter configuration), whereas the input impedance of the FB pin can sometimes be affected by Figure 21. An NPN Buffer Allows Performing the internal dividers or pull-up resistors (it was 5 kW in our Loop Gain Measurement on the Primary Side example). We can anyway find a way to perform this measurement by inserting a buffer between the optocoupler The result is plotted on Figure 22. This loop measurement and the controller as Figure 21 illustrates. Using an NPN done at the feedback pin is clearly not correct: the gain transistor in a common-collector configuration, the output plateaus at low frequencies; and the phase increases again at impedance is made low compared to the input impedance of higher frequencies, so much that the gain margin cannot be the feedback pin. measured. This is clearly not a valid measurement.

NPN buffer - gain Gain (dB) NPN buffer - phase Phase 80 180

60 135

40 90

20 45

0 0

-20 -45

-40 -90

-60 -135

-80 -180 10 100 1000 10000 100000 F (Hz)

Figure 22. Bode Plot Obtained using the NPN Buffer on the Primary Side

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We will now measure one of the two loops independently, Figures23 and 24. Combining the two using the Excel® while biasing the other one with an external dc supply, as we spreadsheet delivers the result of Figure 25. did before. Individual measurement results are shown on

fast + 12 V lanes gain Gain (dB) fast + 12 V lanes phase Phase 80 180

60 135

40 90

20 45

0 0

-20 -45

-40 -90

-60 -135

-80 -180 10 100 1000 10000 100000 F (Hz)

Figure 23. Fast Lane and 12 V Slow Lane Loop Response Obtained with the Network Analyzer

5 V slow lane gain Gain (dB) Phase 5 V slow lane phase 80 180

60 135

40 90

20 45

0 0

-20 -45

-40 -90

-60 -135

-80 -180 10 100 1000 10000 100000 F (Hz)

Figure 24. 5 V Slow Lane Loop Response Obtained with the Network Analyzer

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Combined loops gain Gain (dB) Phase Combined loops phase 80 180

60 135

40 90

20 45

0 0

-20 -45

-40 -90

-60 -135

-80 -180 10 100 1000 10000 100000 F (Hz)

Figure 25. The Final Bode Plot Combines the Information Obtained from Individual Loop Measurements

As expected, the 2-loop measurement is now valid over the validity of the approach, we have gathered Figure25 and the whole frequency range, with a constant slope of −20dB Figure22 on a common graph which appears on Figure26. per decade for the gain at low frequency, and a phase that The gain and the phase curves in the vicinity of the cross over keeps on decreasing after the crossover frequency. To verify frequency are similar.

Combined loops - gain NPN buffer - gain Combined loops - phase Gain (dB) Phase NPN buffer - phase 80 180

60 135

40 90

20 45

0 0

-20 -45

-40 -90

-60 -135

-80 -180 10 100 1000 10000 100000 F (Hz)

Figure 26. Comparing the Combined Bode Plot Obtained from Individual Loop Measurements to the Primary Measurement (with NPN Buffer)

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Conclusion References Measuring the frequency response of a multi-loop 1. D. Venable, “Stability Testing of Multi Loop switch-mode power supply can be a real challenge, Converters”, Venable technical paper #11 especially when all the regulation circuitry is kept on the 2. C. Basso, “Switch Mode Power Supplies: SPICE secondary side. This is often the case with modern current Simulations and Practical Designs”, mode controllers where the feedback input directly controls McGraw-Hill, 2008 the peak current. Hopefully a simple method exists which 3. Middlebrook, R. D., “Measurement of Loop Gain combines individually measured loops with a simple in Feedback Systems, International J. of mathematical manipulation. As demonstrated in this paper, Electronics”, vol. 38, no. 1, pp. 485-512, this method is applicable to a wide range of applications. April1975

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