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ON Semiconductor Is ON Semiconductor Is Now To learn more about onsemi™, please visit our website at www.onsemi.com onsemi and and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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AND8327/D Stability Analysis in Multiple Loop Systems Prepared by Christophe Basso, Stéphanie Conseil, Nicolas Cyr http://onsemi.com Loop stability analysis usually starts from an open-loop with single loops, the operation becomes more complicated Bode plot of the plant under study, e.g. the power stage of a with converters implementing weighted feedback. This buck or a flyback converter. From this diagram, the designer paper capitalizes on the Ref. [1] work and explores different can extract phase and gain data within the frequency range ways to apply the technique to power converters featuring of interest. His job then consists in identifying a multiple feedback paths. compensator structure which will lead to the selected crossover frequency affected by the right phase margin. The The TL431, a Multiple Loop System final step requires the study of the total loop gain, the power The TL431 alone, can be modeled as a multiple loop plant followed by the compensator, showing that the feedback system. Figure 1 shows a TL431 classically wired poles/zeros placed on the compensator ensure stability once in a type-2 configuration, as described in Ref. [2]. From this the loop is closed. If this operation is rather straightforward schematic, one can identify so-called slow and fast lanes. Vout Vdd Rled R2 1 k 10 k Rpullup 20 k Fast Slow Lane Lane FB C1 U2B 100 nF C2 U2A 1 nF U1 TL431 R3 10 k Primary Side Secondary Side Figure 1. A TL431 Wired in a Classical Configuration, Observing the dc Voltage of a Converter The TL431 can be seen as a programmable zener also voltage. Therefore, even if you increase C1, it has no effect called a shunt regulator. When the output voltage changes, in rolling off the loop gain since Rled always senses the e.g. because of a load variation, the information is conveyed output voltage. The transfer function of such a system can be to the inverting input of the TL431 via R2/R3 and asks the written in the following form [2]: programmable zener to pump more or less current into the VFB(s) 1 optocoupler LED. It does so by adjusting its cathode + G (s)ǒ1 ) Ǔ (eq. 1) V (s) 1 sR C voltage. By this way, the feedback signal observed on the out 2 1 primary side also changes and instructs the controller to alter where G1(s) represents the mid-band gain brought by the its operating point. If the output voltage variations are too optocoupler CTR, the LED and the pull-up resistors fast, the frequency sensed by R2 exceeds the pole position associated to the capacitor C2. From this expression, we can introduced by C1 and the ac contribution of this path to the actually see the presence of two loops by developing feedback signal becomes null: the TL431 no longer changes Equation1: its operating point and the LED cathode is now fixed. V (s) G (s) FB + ) 1 However, as the LED cathode is fixed, the anode still senses G1(s) (eq. 2) Vout(s) sR2C1 an output voltage variation via Rled. This current variation propagates via the optocoupler and affects the feedback © Semiconductor Components Industries, LLC, 2008 1 Publication Order Number: April, 2008 - Rev. 0 AND8327/D AND8327/D The loop gain of such a system could be measured by In this schematic, it is not possible to sweep both inputs breaking the loop at the feedback point. Unfortunately, together as they are separated by the LC filter. Fortunately, depending on the converter configuration, this solution can we can apply the superposition theorem as we are dealing sometimes be difficult to implement. The best is then to with a linear system. At first, we will sweep the slow lane measure the loop gain from the secondary side. In this while keeping the fast lane to a bias level, totally particular example, both the fast and slow lanes share a disconnected from the output voltage. A dc voltage supplied similar entry point. The total loop gain could therefore be by an external source will do. This is what Figure 4 shows. measured as suggested by Figure 2: The precision of the 5 V source is not relevant here as it only serves bias purposes. The ac source actually represents an Vout injection transformer, classically used in loop stability V1 studies. The A and B probes go to a network analyzer which AC = 1 will compute + 20 log ǒBǓ, Rled R2 10 A 1 k 10 k displaying a loop gain equal to Fast Slow G1(s) Lane Lane sR2C1 C1 100 nF U2B L1 Vout U1 Vsweep TL431 R3 10 k AC = 1 V + + Rled Vext 1 k 5 V Figure 2. When Both Slow and Fast Lanes are R2 Fast B A 10 k Connected Together, the Measurement is Easy to Run Lane Slow C1 + A stimulus source is inserted in series with the output Lane Cout U2B 100 nF voltage and both slow and fast lanes are ac swept. The 220 mF voltage observed on the feedback pin is therefore proportional to both inputs and is representative of what U1 Equations1 and 2 predict. TL431 R3 In Figure 3, we can see the presence of a LC filter, added 10 k to remove unwanted high frequency spikes, typical of a flyback converter. Figure 4. The Fast Lane is ac Disconnected from the Vout Circuit and Only the Slow Lane Receives a Stimulus Rled L1 R2 1 k 10 k Then, once the plot is saved, the configuration needs to be Fast Slow changed to the other input, as suggested by Figure 5. In this Lane Lane circuit, the upper R2 terminal is connected to a dc voltage C1 + whose value must equal the regulated voltage whereas the Cout 100 nF U2B 220 mF fast lane input is now ac swept: U1 TL431 R3 10 k Figure 3. The Presence of the LC Filter Splits Both Lanes http://onsemi.com 2 AND8327/D L1 + ö ) ö + (eq. 5) Vout Re(VFB) A1 cos 1 A2 cos 2 X + ö ) ö + (eq. 6) Vsweep Im(VFB) A1 sin 1 A2 sin 2 Y AC = 1 V + Vext The rotating vector obtained at the end will be of the 5 V + following form: Rled R2 V + X ) jY (eq. 7) 1 k 10 k FB B A Where we can now extract a module and an argument: Fast Slow Lane Lane ø ø+ Ǹ 2 ) 2 (eq. 8) VFB Y X C1 + Cout *1 Y U2B 100 nF arg V + tan ǒ Ǔ (eq. 9) 220 mF FB X Plotting 20log10 of Equation 8 and the phase returned by U1 Equation9 should give the Bode plot we are looking for. TL431 R3 10 k SPICE Application Before rushing to the laboratory to apply this technique, let's give it a try with a SPICE simulation and check that our Figure 5. The Fast Lane is Now ac Swept as the equations give the correct answers. Figure 6 depicts the Slow Lane is Simply dc Biased TL431 circuit ready to be ac swept, both inputs being connected together.
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