A Single-Chip CMOS Bluetooth V2.1 Radio Soc William W
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2896 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 12, DECEMBER 2008 A Single-Chip CMOS Bluetooth v2.1 Radio SoC William W. Si, Member, IEEE, David Weber, Member, IEEE, Shahram Abdollahi-Alibeik, MeeLan Lee, Richard Chang, Hakan Dogan, Senior Member, IEEE, Haitao Gan, Yashar Rajavi, Susan Luschas, Soner Ozgur, Paul Husted, and Masoud Zargari, Senior Member, IEEE Abstract—A single-chip Bluetooth v2.1-compliant CMOS radio SoC that supports Enhanced Data Rates is implemented in stan- dard 0.13 m CMOS technology. All functions of a Bluetooth radio are integrated in the SoC, including RF, analog and digital parts. The RF transceiver features a polar transmitter, a two-point mod- ulated fractional-N synthesizer, a 500 kHz IF receiver with first order low-pass analog filtering, and a ADC with 74 dB dy- namic range. The total SoC die area is 9.2 mmP with only 3.0 mmP for analog and RF circuits. The basic-rate radio power consump- tion is below 30 mA for both receive and transmit. Index Terms—Bluetooth, polar modulation, polar transmitter, RF receiver, RF transceiver, RF transmitter, system-on-a-chip, two point phase modulation, SoC. Fig. 1. SoC block diagram. I. INTRODUCTION is chosen to minimize overall die area as well as power con- LUETOOTH radio technology has now been adopted in a sumption for both the basic rate and EDR [9]. wide array of applications including audio headsets, cel- B The single-chip Bluetooth SoC block diagram is shown in lular telephones, portable computers, and automotive applica- Fig. 1. All functions of a Bluetooth radio are implemented in tions. Nearly 2 billion Bluetooth products are on the market the SoC, including the RF transceiver, modem, link controller, today [1]. This commercial success has led to continuing im- CPU, RAM, ROM, and a number of other peripheral compo- provements in the Bluetooth standard with higher data trans- nents. The SoC also integrates many auxiliary analog circuits, mission capacity, the latest of which is Bluetooth v2.1 [2].1 A such as linear low-dropout voltage regulators, a phase-locked Bluetooth v2.1 radio is a frequency-hopping system that oper- loop, crystal oscillators, a bandgap, biasing circuits, a low power ates in the 2.4 GHz unlicensed ISM band with 79 subdivided oscillator (LPO) and a thermometer. Only a few components channels of 1 MHz each. Besides the legacy 1 Mbps rate based are left off-chip, notably the crystal and the antenna. All cali- on GFSK modulation, Bluetooth v2.1 includes two higher data bration and support circuitry required for operation is self-con- rates. These two Enhanced Data Rates (EDR) use -DQPSK tained within the SoC. and 8-PSK for 2 Mbps and 3 Mbps links, respectively. The organization of this paper is as follows. Section II de- Numerous fully integrated Bluetooth transceivers and SoCs scribes the circuit implementation of the polar transmitter along have been reported, including several designs that are EDR- with the frequency synthesizer. The 500 kHz IF receiver de- compliant [3]–[8], [12], [13]. Since Bluetooth is primarily used sign is detailed in Section III. Section IV presents measurement for short range communication, the driving force in the market results. is to reduce both power consumption and cost. An integrated, low-cost, CMOS Bluetooth radio SoC will support the contin- II. POLAR TRANSMITTER uing growth of this market. In this paper, a Bluetooth v2.1 com- pliant SoC that integrates all functions of a Bluetooth radio is Fig. 2 shows the architecture of the polar transmitter. A polar presented. The transceiver is comprised of a two-point modu- architecture is chosen for the transmitter primarily because it lated fractional-N synthesizer, a polar transmitter, and a 500 kHz can provide very low power consumption when operating in the IF receiver with minimal analog filtering. The radio architecture legacy GFSK mode as well as requiring less analog area than a traditional quadrature transmit architecture. Transmit mixers are not needed, which saves power and area, and improves lin- Manuscript received April 07, 2008; revised July 21, 2008. Current version earity. In a polar transmitter, the transmit signal is decomposed published December 10, 2008. into amplitude and phase components [10], [18] by the digital The authors are with Atheros Communications, Inc., Santa Clara, CA 95054 modem. The phase modulation is performed in the synthesizer. USA (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/JSSC.2008.2005741 The phase signal is split into high frequency (HF) and low fre- quency (LF) data paths to directly modulate a fractional-N syn- 1Bluetooth v2.1+EDR (Enhanced Data Rate) was officially adopted in August thesizer and create an RF phase modulated signal. The phase 2007. The Bluetooth SIG is exploring the integration of Bluetooth with IEEE 802.11 and ultra wideband. This ‘Alternate MAC/PHY’ proposal is expected to modulated signal is fed directly to an RF power amplifier (PA). be published in mid 2009. For the legacy 1 Mbps GFSK rate with a constant envelope 0018-9200/$25.00 © 2008 IEEE SI et al.: SINGLE-CHIP CMOS BLUETOOTH V2.1 RADIO SoC 2897 Fig. 2. Polar transmitter block diagram. Fig. 4. Description of two-point phase modulation concept. using frequency modulation (FM) in the frequency synthesizer by modulating the feedback division ratio and VCO control voltage. The desired PM data of an 8-PSK signal is converted to FM data by computing its derivative in the digital domain. During a zero-crossing symbol transition, the phase makes a 180 degree change instantaneously as shown in Fig. 3. This step function in the PM data is an impulse function in the FM data, which cannot be perfectly reproduced in a practical polar transmitter due to bandwidth limitations. Simulation analysis determines that a bandwidth of about 12 MHz in the FM path and a maximum frequency deviation of MHz is Fig. 3. 8-DPSK signal polar decomposition. needed in order to meet the EVM and spectrum mask require- ments for 8-PSK modulation at the RF output. As the VCO runs at twice the RF frequency, the maximum frequency deviation RF signal, amplitude modulation is not needed and an efficient at the VCO is MHz. constant-envelope PA is used. For the enhanced rates with a non-constant envelope, amplitude modulation is applied at the A. Two-Point Modulation PA stage using a digital-to-analog converter (DAC). The DAC To address the requirement of 12 MHz bandwidth and uses 9 bits to meet the 26 dB dynamic range requirement for MHz maximum frequency deviation for the FM path, AM, with the additional dynamic range used for power control. a two-point modulation scheme is used in the synthesizer loop The bandwidth of the AM data is about 3 MHz. The PA output [[12]–[16], [19], [20]]. The concept of two-point modulation power is detected using an on-chip peak detector for closed loop is illustrated in Fig. 4. The goal of two-point modulation is to power control. allow the FM path bandwidth to be much wider than the synthe- The inclusion of enhanced data rates (EDR) to the Bluetooth sizer loop bandwidth. In a sigma-delta fractional-N synthesizer, standard makes the choice of polar modulation significantly the most convenient way to modulate the VCO frequency is to more challenging than a design that only supports the legacy apply the modulation signal at the sigma-delta multi-modulus rate. For the basic 1 Mbps rate with no amplitude modulation, divider input. However, the input frequency signal is low pass the total bandwidth of the phase component is approximately filtered by the synthesizer loop bandwidth in order to suppress equal to the 1 MHz channel bandwidth. A conventional sigma-delta quantization noise and reference spurs, thereby fractional-N synthesizer can meet the desired modulation band- constraining the synthesizer loop bandwidth to a value that is width for the basic rate with digital bandwidth enhancement typically a few hundred kHz. This bandwidth is too narrow techniques [11]. However, implementing a polar transmitter for Bluetooth phase modulation, even for the legacy 1 Mbps to support the 3 Mbps rate with 8-PSK modulation poses rate. Various schemes of widening modulation bandwidth have significant challenges for both amplitude and phase modula- been studied [11]–[16]. The two-point modulation approach tion paths. Fig. 3 illustrates the polar decomposition for an has the advantage that the modulation bandwidth is relatively 8-PSK modulated signal. An ideal 8-PSK constellation requires insensitive to PLL loop bandwidth, as well as to process and symbol transitions that include zero crossings. That is, the temperature variations. amplitude of the RF signal will decrease to zero as the symbol A block diagram of the synthesizer with a two-point mod- transition crosses the center of the constellation. Practical polar ulation capability is shown in Fig. 5. The phase signal is de- transmitters have difficulty representing zero amplitude, be- composed into HF and LF paths digitally. Both paths are 11-bit cause of the finite dynamic range of the AM path. System-level wide. The dynamic range of the HF and LF FM paths is deter- simulations show that the Bluetooth spectral mask requirement mined such that quantization noise will not impact the EVM or can be met provided that the AM path has a dynamic range transmit spectral performance. The 11-bit LF data is applied di- of at least 26 dB. A zero crossing is equally challenging for rectly to the divider, which modulates the VCO phase with the phase modulation (PM) path.