A Single-Chip CMOS Bluetooth V2.1 Radio Soc William W

2896 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 12, DECEMBER 2008 A Single-Chip CMOS Bluetooth v2.1 Radio SoC William W. Si, Member, IEEE, David Weber, Member, IEEE, Shahram Abdollahi-Alibeik, MeeLan Lee, Richard Chang, Hakan Dogan, Senior Member, IEEE, Haitao Gan, Yashar Rajavi, Susan Luschas, Soner Ozgur, Paul Husted, and Masoud Zargari, Senior Member, IEEE

Abstract—A single-chip Bluetooth v2.1-compliant CMOS radio SoC that supports Enhanced Data Rates is implemented in standard 0.13 m CMOS technology. All functions of a Bluetooth radio are integrated in the SoC, including RF, analog and digital parts. The RF transceiver features a polar transmitter, a two-point modulated fractional-N synthesizer, a 500 kHz IF receiver with ﬁrst order low-pass analog ﬁltering, and a ADC with 74 dB dynamic range. The total SoC die area is 9.2 mmP with only 3.0 mmP for analog and RF circuits. The basic-rate radio power consumption is below 30 mA for both receive and transmit. Index Terms—Bluetooth, polar modulation, polar transmitter, RF receiver, RF transceiver, RF transmitter, system-on-a-chip, two point phase modulation, SoC.

Fig. 1. SoC block diagram. I. INTRODUCTION

is chosen to minimize overall die area as well as power con- LUETOOTH radio technology has now been adopted in a sumption for both the basic rate and EDR [9]. wide array of applications including audio headsets, cel- B The single-chip Bluetooth SoC block diagram is shown in lular telephones, portable computers, and automotive applica- Fig. 1. All functions of a Bluetooth radio are implemented in tions. Nearly 2 billion Bluetooth products are on the market the SoC, including the RF transceiver, modem, link controller, today [1]. This commercial success has led to continuing im- CPU, RAM, ROM, and a number of other peripheral compo- provements in the Bluetooth standard with higher data trans- nents. The SoC also integrates many auxiliary analog circuits, mission capacity, the latest of which is Bluetooth v2.1 [2].1 A such as linear low-dropout voltage regulators, a phase-locked Bluetooth v2.1 radio is a frequency-hopping system that oper- loop, crystal oscillators, a bandgap, biasing circuits, a low power ates in the 2.4 GHz unlicensed ISM band with 79 subdivided oscillator (LPO) and a thermometer. Only a few components channels of 1 MHz each. Besides the legacy 1 Mbps rate based are left off-chip, notably the crystal and the antenna. All cali- on GFSK modulation, Bluetooth v2.1 includes two higher data bration and support circuitry required for operation is self-con- rates. These two Enhanced Data Rates (EDR) use -DQPSK tained within the SoC. and 8-PSK for 2 Mbps and 3 Mbps links, respectively. The organization of this paper is as follows. Section II de- Numerous fully integrated Bluetooth transceivers and SoCs scribes the circuit implementation of the polar transmitter along have been reported, including several designs that are EDR- with the frequency synthesizer. The 500 kHz IF receiver de- compliant [3]–[8], [12], [13]. Since Bluetooth is primarily used sign is detailed in Section III. Section IV presents measurement for short range communication, the driving force in the market results. is to reduce both power consumption and cost. An integrated, low-cost, CMOS Bluetooth radio SoC will support the contin- II. POLAR TRANSMITTER uing growth of this market. In this paper, a Bluetooth v2.1 compliant SoC that integrates all functions of a Bluetooth radio is Fig. 2 shows the architecture of the polar transmitter. A polar presented. The transceiver is comprised of a two-point modu- architecture is chosen for the transmitter primarily because it lated fractional-N synthesizer, a polar transmitter, and a 500 kHz can provide very low power consumption when operating in the IF receiver with minimal analog filtering. The radio architecture legacy GFSK mode as well as requiring less analog area than a traditional quadrature transmit architecture. Transmit mixers are not needed, which saves power and area, and improves lin- Manuscript received April 07, 2008; revised July 21, 2008. Current version earity. In a polar transmitter, the transmit signal is decomposed published December 10, 2008. into amplitude and phase components [10], [18] by the digital The authors are with Atheros Communications, Inc., Santa Clara, CA 95054 modem. The phase modulation is performed in the synthesizer. USA (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/JSSC.2008.2005741 The phase signal is split into high frequency (HF) and low frequency (LF) data paths to directly modulate a fractional-N syn- 1Bluetooth v2.1+EDR (Enhanced Data Rate) was officially adopted in August thesizer and create an RF phase modulated signal. The phase 2007. The Bluetooth SIG is exploring the integration of Bluetooth with IEEE 802.11 and ultra wideband. This ‘Alternate MAC/PHY’ proposal is expected to modulated signal is fed directly to an RF power amplifier (PA). be published in mid 2009. For the legacy 1 Mbps GFSK rate with a constant envelope

Fig. 2. Polar transmitter block diagram.

Fig. 4. Description of two-point phase modulation concept.

using frequency modulation (FM) in the frequency synthesizer by modulating the feedback division ratio and VCO control voltage. The desired PM data of an 8-PSK signal is converted to FM data by computing its derivative in the digital domain. During a zero-crossing symbol transition, the phase makes a 180 degree change instantaneously as shown in Fig. 3. This step function in the PM data is an impulse function in the FM data, which cannot be perfectly reproduced in a practical polar transmitter due to bandwidth limitations. Simulation analysis determines that a bandwidth of about 12 MHz in the FM path and a maximum frequency deviation of MHz is Fig. 3. 8-DPSK signal polar decomposition. needed in order to meet the EVM and spectrum mask require- ments for 8-PSK modulation at the RF output. As the VCO runs at twice the RF frequency, the maximum frequency deviation RF signal, amplitude modulation is not needed and an efficient at the VCO is MHz. constant-envelope PA is used. For the enhanced rates with a non-constant envelope, amplitude modulation is applied at the A. Two-Point Modulation PA stage using a digital-to-analog converter (DAC). The DAC To address the requirement of 12 MHz bandwidth and uses 9 bits to meet the 26 dB dynamic range requirement for MHz maximum frequency deviation for the FM path, AM, with the additional dynamic range used for power control. a two-point modulation scheme is used in the synthesizer loop The bandwidth of the AM data is about 3 MHz. The PA output [[12]–[16], [19], [20]]. The concept of two-point modulation power is detected using an on-chip peak detector for closed loop is illustrated in Fig. 4. The goal of two-point modulation is to power control. allow the FM path bandwidth to be much wider than the synthe- The inclusion of enhanced data rates (EDR) to the Bluetooth sizer loop bandwidth. In a sigma-delta fractional-N synthesizer, standard makes the choice of polar modulation significantly the most convenient way to modulate the VCO frequency is to more challenging than a design that only supports the legacy apply the modulation signal at the sigma-delta multi-modulus rate. For the basic 1 Mbps rate with no amplitude modulation, divider input. However, the input frequency signal is low pass the total bandwidth of the phase component is approximately filtered by the synthesizer loop bandwidth in order to suppress equal to the 1 MHz channel bandwidth. A conventional sigma-delta quantization noise and reference spurs, thereby fractional-N synthesizer can meet the desired modulation band- constraining the synthesizer loop bandwidth to a value that is width for the basic rate with digital bandwidth enhancement typically a few hundred kHz. This bandwidth is too narrow techniques [11]. However, implementing a polar transmitter for Bluetooth phase modulation, even for the legacy 1 Mbps to support the 3 Mbps rate with 8-PSK modulation poses rate. Various schemes of widening modulation bandwidth have significant challenges for both amplitude and phase modula- been studied [11]–[16]. The two-point modulation approach tion paths. Fig. 3 illustrates the polar decomposition for an has the advantage that the modulation bandwidth is relatively 8-PSK modulated signal. An ideal 8-PSK constellation requires insensitive to PLL loop bandwidth, as well as to process and symbol transitions that include zero crossings. That is, the temperature variations. amplitude of the RF signal will decrease to zero as the symbol A block diagram of the synthesizer with a two-point mod- transition crosses the center of the constellation. Practical polar ulation capability is shown in Fig. 5. The phase signal is de- transmitters have difficulty representing zero amplitude, be- composed into HF and LF paths digitally. Both paths are 11-bit cause of the finite dynamic range of the AM path. System-level wide. The dynamic range of the HF and LF FM paths is deter- simulations show that the Bluetooth spectral mask requirement mined such that quantization noise will not impact the EVM or can be met provided that the AM path has a dynamic range transmit spectral performance. The 11-bit LF data is applied di- of at least 26 dB. A zero crossing is equally challenging for rectly to the divider, which modulates the VCO phase with the phase modulation (PM) path. The PM is implemented a low-pass transfer function. The HF data is applied to the VCO 2898 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 12, DECEMBER 2008

Fig. 5. A two-point frequency modulated synthesizer.

Fig. 6. VCO schematic and VCO frequency modulation gain. using an 11-bit voltage DAC. The HF path phase modulation is thesis during transmit. The power consumption of the synthe- treated the same way as VCO noise by the PLL system, that is, sizer is 11.5 mA from a 1.2 V supply. the portion of the HF signal that falls within the PLL loop bandwidth is attenuated by the PLL. Outside the loop bandwidth, the B. VCO HF signal passes through to the VCO output, unaffected by the Fig. 6 shows details of the 4.8 GHz VCO. It is similar to a tra- PLL. Hence the HF path phase modulation bears a high-pass ditional LC tuned oscillator, but two sets of MOS varactors are transfer function, which ideally compensates the portion of the used in the circuit. MOS varactors M3 and M4 are connected to phase signal filtered out in the LF path. The important point is the synthesizer loop filter and allow the VCO to be locked to the that the LF path is filtered by the loop filter and the HF path center frequency. The LF phase modulation data from the feed- is filtered by the inverse of the same loop filter. When properly back dividers are eventually applied to this varactor input and added together at the VCO output, the desired signal is recon- will modulate the VCO within the loop bandwidth. The second structed in its entirety. This addition occurs independently of the set of MOS varactors M1 and M2 are connected to the HF DAC loop bandwidth, therefore it is insensitive to process and temper- and modulate the VCO outside the loop bandwidth. As a result, ature variation of the loop bandwidth. By properly matching the the combination of these two varactor pairs allows the VCO fre- gain and phase of the HF and LF paths, the combined modula- quency to be modulated with the full FM bandwidth. tion bandwidth at the VCO can far exceed the synthesizer loop One challenge of using a MOS varactor for frequency mod- bandwidth. ulation in an open-loop scheme is that its gain will vary over The local oscillator (LO) frequency is generated by a frac- process and temperature. Also shown in Fig. 6 is measured data tional-N synthesizer with the VCO running near 4.8 GHz. The for a number of chips from a skew lot plotting the variation of choice of a VCO frequency at twice the RF allows I/Q LO the HF gain as a function of process. The X-axis represents the signals near 2.4 GHz to be generated through simple division input code of the 11-bit HF DAC, and the Y-axis represents for the receiver, which reduces I/Q mismatch and minimizes the HF gain in units of Hz/bit. The gain curves are shaped like 2.4 GHz LO leakage into the LNA. A third-order modu- a parabola because the derivative of the C/V characteristic of lator with 4 bit output is used to control the multi-modulus a varactor is greatest near zero bias, which is placed near the feedback divider of the fractional-N synthesizer to create the center of our HF data scale. Because the value of the varactor required 1 MHz channel spacing and for direct frequency syn- capacitance at a given bias can change from chip to chip, cali- SI et al.: SINGLE-CHIP CMOS BLUETOOTH V2.1 RADIO SoC 2899

Fig. 7. Power ampliﬁer schematic.

Fig. 8. Receiver block diagram. bration is needed in order to properly match the HF gain to the and avoid device breakdown. To transmit at 2 dBm, the PA con- LF path. sumes 10.1 mA for the legacy 1 Mbps rate in the switching mode and 20 mA for EDR in the linear mode. C. Power Amplifier III. RECEIVER The power amplifier (PA) schematic is shown in Fig. 7. Am- Fig. 8 illustrates the block diagram of the receiver. The two plitude modulation (when needed) is applied differentially to RF stages including low noise amplifier (LNA) and RF variable the current sources M1 and M2 through a 9-bit current-steering gain amplifier (VGA) provide about 40 dB of gain. Since low DAC. The switching pairs M5-M8 are driven by the phase power consumption is of utmost importance in a Bluetooth de- signal, generated by the synthesizer and a divide-by-2 circuit. vice, these stages use inductive loads. They consume an area of When the amplitude modulation DAC output currents are equal, 0.27 mm , but require only 2 mA of current per stage. Both of the RF output amplitude would be ideally at a minimum. In these RF stages have variable gains for AGC operations. Their practice, device mismatches and capacitive feedthrough causes power consumption scales with the gain setting, and as a result, LO leakage to the RF output that must be calibrated. This will be lower for larger received signals. mixer-type PA topology was chosen for its ability to achieve a Our target sensitivity was dBm for the 1 Mbps rate. The very large AM dynamic range, which was necessary to handle total NF needed to achieve this sensitivity is 12 dB. This NF is the 26 dB dynamic range requirement of the 3 Mbps EDR carefully budgeted among receiver stages so that we can mini- packets. mize the power consumption. For the basic rate with no amplitude modulation, the gate of The RF blocks are followed by a passive quadrature mixer. M1 is connected to VDD so that the source of M5 and M6 is The IF was chosen to be 500 KHz, which places the signal pass- near ground, thereby converting half of the PA to run as an ef- band adjacent to DC. This choice was a compromise between di- ficient switching mode amplifier. The thick-oxide cascode de- rect conversion and a traditional low-IF topology. Unlike a tradi- vices M9-M12 allow PA drain connections to 1.8 V or 3.3 V tional low-IF receiver, where a larger bandpass filter is needed, 2900 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 12, DECEMBER 2008

Fig. 9. LNA and integrated T/R switch schematic. this choice of IF makes it possible to keep the analog filter as In the front-end, an RF switch is integrated on the chip. The a low-pass filter. Also, unlike a direct conversion receiver, the LNA input is shared with the PA output pins through the use of DC offset in this case will not fall in the middle of the signal this on-chip switch, as shown in Fig. 9 [17]. The switch consists band. This removes the signal detection challenge inherent in of AC coupling capacitors, a transformer, and a set of CMOS direct conversion receivers and makes it easier to differentiate switches. During receive mode, the gates of the PA cascode tran- between the beginning of a packet and a small change in DC sistors are grounded, so the incoming signal is channeled to the offset. LNA input gates through the on-chip transformer and the AC Since analog blocks do not lend themselves to technology coupling capacitors. During transmit mode, NMOS switches at scaling as well as digital circuitry, most of the channel selection the LNA input are closed. This protects the LNA input from the and filtering is performed in the digital modem, and the analog PA swing. It also causes the transformer to resonate with the filter is greatly simplified as a result. The first filtering stage is a parasitic capacitance of the PA output and the package pins to nominally first order lowpass filter, which also provides a vari- create a high impedance node that reduces the loss between the able gain of 10–24 dB that can be adjusted for AGC operations. PA and the output pins. A switched capacitor filter follows this stage which creates a Although the RF circuits are differential, the performance tar- notch at 64 MHz. Together, these two stages of the filter provide gets are met even with a single-ended antenna connection. The the needed anti-alias filtering and out-of-band blocker rejection. unused pin can be terminated with an SMT capacitor. Due to The frequency response of the filter was chosen in such a way the integrated nature of the switch, the insertion loss is difficult that no calibration is required. to measure directly, but through simulation the loss is believed The ADC following the filter has a nominal dynamic range to be less than 1 dB. of 74 dB. This dynamic range can comfortably accommodate the signal, close-in blockers and DC offset. The ADC uses a 2-1 IV. MEASUREMENTS third order 64 MHz oversampled architecture. Similar to the RF stages, low power consumption was one of the main criteria The SoC is implemented in standard 0.13 m digital CMOS in the design of all the analog baseband circuits. with a die area of 9.2 mm , of which only 3.0 mm is the analog Two DC offset cancellation DACs are connected to the filter and RF. The basic-rate radio power consumption is 29.7 mA in inputs (not shown in the block diagram). These are only needed receive and 29.4 mA in transmit. if the overall receiver DC offset goes above 140 mV. In practice, Synthesizer phase noise is one of the key performance met- as shown in Section IV, the DC offset is low enough that no rics that can limit transmitter spectral mask compliance and analog correction is needed. This was achieved through careful receiver blocker rejection performance. A typical synthesizer design and layout of the radio. phase noise profile measured at the PA output is plotted in The overall design looks very similar to a direct-conversion Fig. 10. The in-band phase noise is about dBc/Hz which receiver which has the advantage of occupying a relatively small is dominated by reference noise, and at 1 MHz the phase noise area. The entire receive chain draws 15.4 mA from a 1.2 V is about dBc/Hz which is limited by quantization noise. supply. The flattening of the phase noise at higher frequency offsets SI et al.: SINGLE-CHIP CMOS BLUETOOTH V2.1 RADIO SoC 2901

Fig. 12. Measured transmitter output spectrum.

Fig. 10. Measured phase noise at transmitter output.

Fig. 13. Measured receiver performance.

Fig. 11. Measured transmitter 8-DPSK constellation. is an artifact of the measurement as we approach the thermal noise floor of the analyzer. A measured 8-PSK constellation for the transmitter is shown Fig. 14. Measured receiver blocker rejection. in Fig. 11, as measured by a Rhode and Schwartz CBT analyzer. At an average power of 2 dBm, the EVM is shown to have an RMS value less than 5.2% vs. the Bluetooth specification of measured on a test board optimized for analog testing with 13%, and a peak EVM of less than 13.1% vs. the specification of minimal digital activity. The noise figure is measured to be 25%. The Bluetooth standard also requires 99% of the symbols 8–10 dB across channels. The dips that appear periodically in to be below 20% EVM, and in this case 100% of the symbols the noise figure measurement are measurement artifacts which meet this requirement. do not appear in the real system. Fig. 12 shows two measured screenshots of the transmitter The measured blocker rejection performance at 1 Mbps rate output spectrum, both with output power of 2 dBm. The output is shown in Fig. 14. The X-axis represents the frequency offset spectrum at 1 Mbps demonstrates the constant-amplitude GFSK of the blocker relative to the signal frequency, with zero fre- modulation, and the spectrum at 3 Mbps EDR demonstrates the quency offset being a co-channel blocker. The Y-axis represents 8-PSK modulation. In both cases the spectrum meets the re- the magnitude of the desired signal relative to the blocker, with quirements of the Bluetooth standard. 0 dB meaning the signals are received at equal power. For this Fig. 13 shows a measurement of 1 Mbps sensitivity and noise figure, the blocker performance is measured for channels within figure across channels. The sensitivity measurement is per- 7 MHz of the desired signal. As shown in the figure, the radio formed on a system board under a true working environment. meets the Bluetooth requirement with good margin. The measured sensitivity is typically to dBm, which Fig. 15 shows measured DC offset in the RX chain across meets our design target, and exceeds the Bluetooth standard channels and process for ten different chips. In this design, of dBm sensitivity with a large margin. Noise figure is 140 mV of the ADC input range is budgeted to quantize the DC 2902 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 12, DECEMBER 2008

TABLE I SOCPERFORMANCE SUMMARY

the analog domain, since the entire DC offset can be quantized by the ADC and removed digitally. A die micrograph is shown in Fig. 16. The chip was fabricated in a standard digital 0.13 m CMOS process. The RF and analog portion occupies an area of 3 mm , and the total die area is 9.2 mm . The chip is powered from a 3.3 V I/O supply and two separate on-chip voltage regulators provide 1.2 V supplies to the analog and digital blocks. The die is small enough to ﬁt into a 5 5 mm 40 pin QFN package. A summary of measurements is shown in Table I.

Fig. 15. Measured Receiver DC Offset at ADC Input. V. C ONCLUSION A single-chip Bluetooth v2.1 compliant SoC supporting EDR is demonstrated in a 0.13 m standard digital CMOS technology. This SoC uses a two-point polar transmitter architecture to reduce power and area. The fractional-N frequency synthesizer based on a sigma delta modulator achieves a phase noise of dBc/Hz at 1 MHz offset. The whole polar transmitter including the synthesizer but excluding the PA consumes a total of 19.3 mA from 1.2 V supply. The 500 kHz IF receiver architecture minimizes analog ﬁltering. Continuous RX analog power consumption including the synthesizer is 29.7 mA from a 1.2 V supply. The total die area is 9.2 mm , including 3.0 mm for the analog and RF portion. To our knowledge this is the smallest published Bluetooth SoC to date in 0.13 m CMOS.

ACKNOWLEDGMENT Fig. 16. Chip micrograph. A Bluetooth SoC requires a great deal of effort beyond the analog design, which is the focus of this paper. The authors gratefully acknowledge the work of the entire Bluetooth team offset. However, the actual DC offset is well below this budget. at Atheros, especially the CAD, digital design, physical design, As mentioned earlier, no DC offset cancellation is needed in characterization, system integration and bringup groups. SI et al.: SINGLE-CHIP CMOS BLUETOOTH V2.1 RADIO SoC 2903

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He is also involved in the 564–565. architectural development of RF transceivers. 2904 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 12, DECEMBER 2008

MeeLan Lee received the B.S. and M.Eng. degrees Yashar Rajavi was born in Tehran, Iran. He received from the Massachusetts Institute of Technology, the B.S.E.E. degree from the University of Tehran in Cambridge, in 1995 and 1997, respectively, both in 2005, and the M.S.E.E. degree from Stanford Univer- electrical engineering and computer science. sity, Stanford, CA, in 2007. From 1997 to 1999, she was with Chromatic Re- In 2007, he joined Atheros Communications, Santa search, Sunnyvale, CA, working on high-speed dig- Clara, CA, where he is involved with analog/RF IC ital circuits. From 1999 to 2001, she was with Level design. One Communications (now Intel Corporation), San Francisco, CA, designing CMOS RF cordless tele- phone chipsets. Since April 2001, she has been with Atheros Communications, Santa Clara, CA, where she is currently an Analog Design Manager. She is engaged in managing the design of analog, mixed-signal, and RF integrated circuits for wireless communication products. Susan Luschas received the B.S., M.Eng., and Ph.D. degrees in electrical engineering from the Massachusetts Institute of Technology, Cambridge, MA, in 1997, 1998, and 2003, respectively. Richard Chang received the Bachelors and Masters From 2003 to 2005, she was involved in the de- degrees in electrical engineering from MIT in 1998. sign of analog and RF circuits for wireless communi- In 2002, he received the Ph.D. from Stanford Univer- cations at Atheros Communications. She worked on sity, focusing on low-latency, on-chip silicon-based low-power wireless from 2005 to 2008. Since 2005, global interconnects. she has been involved in teaching and advising stu- Following graduation, he worked at MIT Lincoln dents as an adjunct faculty at Santa Clara University. Laboratory, designing 10 GHz silicon-based phased She is currently working at the Bosch Research and array receivers. Since 2004, he has been at Atheros Technology Center on low-power analog circuits. Communications, Santa Clara, CA, where he designs circuits for wireless applications, with a particular in- terest in on-chip integration. Soner Ozgur received the B.S. from the University of Southern California in 1998, and the M.S. and Ph.D. degrees from the Georgia Institute of Tech- Hakan Dogan (SM’00) was born in Malatya, Turkey, nology, Atlanta, GA, in 2000 and 2006, respectively, on June 6, 1976. He received the B.S. degree in elec- all in electrical engineering. trical engineering from University of Southern Cali- He has been with Atheros Communications, Santa fornia (USC), Los Angeles, in 1999, and the M.S. and Clara, CA, since 2006, currently as a Senior Signal Ph.D. degrees in electrical engineering from the Uni- Processing Engineer. His research interests include versity of California at Berkeley in 2001 and 2005, wireless communications, signal processing, detec- respectively. tion/estimation theory and information theory. He is currently with Atheros Communications, Santa Clara, CA, where he is involved with dual-band wireless-LAN transceiver, Bluetooth transceiver and GPS receiver chipset designs. In the summer of 2000, he worked in HP Labs, where he was involved with the design of Paul Husted was born in Buffalo, New York. He clock and data recovery circuits for high-speed serial data links. During the received the B.S. degree from Boston University, two consecutive summers, in 2001 and 2002, he was with Maxim Integrated Boston, MA, in 1998, and the M.S. degree from the Circuits, where he was involved with the design of cable modem tuners and University of California at Berkeley in 1999, all in satellite receivers. electrical engineering. Dr. Dogan is a member of various honor societies. He is the recipient of the Since 1999, he has been with Atheros Communica- Analog Devices Outstanding Student Designer Award and Philip S. Biegler- tions, Santa Clara, CA, currently as a Manager of the Excellence in Electrical Engineering Award from USC. Algorithms and Architecture group. His research interests include wireless communications, signal processing, audio signal processing, and modeling and calibration techniques for integrated analog circuits. Haitao Gan received the B.S.E.E. degree from Ts- inghua University, China, in 1997, the M.S. degree in electrical and computer engineering from the Uni- versity of Massachusetts, Amherst, in 1999, and the Masoud Zargari (S’86–M’97–SM’08) was born in Ph.D. in electrical engineering from Stanford Uni- Tehran, Iran, in 1966. He received the B.S. degree versity, Stanford, CA, in 2006. As part of her Ph.D. in electrical engineering from Tehran University in research, she worked on modeling on-chip passive 1989 and the M.S. and Ph.D. degrees in electrical en- components such as inductors and transformers, and gineering from Stanford University, Stanford, CA, in built and tested LNAs and PAs with on-chip balun. 1993 and 1997 respectively. In May 2006, she joined Atheros Communications, From 1996 to 1998, he was a Member of the Tech- Santa Clara, CA, where she is currently designing nical Staff at Wireless Access Inc., Santa Clara, CA, analog RF and mixed-signal circuits. where he worked on the design and development of wireless systems for two-way messaging networks. In 1998, he joined Atheros Communications as a member of the founding team, where he is currently the Director of Engineering focusing on integrated systems for wireless communications. During 1999 and 2000, he was a Consulting Assistant Professor at Stanford University, where he taught courses in the area of RF and analog integrated circuit design.