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Emips, a Dynamically Extensible Processor Automatic Generation of Interrupt-Aware Hardware Accelerators with the M2V Compiler Abilash Sekar, Alessandro Forin Microsoft Research August 2008 Technical Report MSR-TR-2008-110 Microsoft Research Microsoft Corporation One Microsoft Way Redmond, WA 98052 - 2 - Automatic Generation of Interrupt-Aware Hardware Accelerators with the M2V Compiler Abilash Sekar, Alessandro Forin Microsoft Research Extensible processors take advantage of the fact that a Abstract small amount of code takes the majority of execution time in a typical program. The code that executes most often is The MIPS-to-Verilog (M2V) compiler and the Basic a candidate for hardware acceleration. The code is Block Tools (BBTools) can automatically generate a identified by a special instruction that will initiate the hardware accelerator for selected blocks of machine code accelerator. in an application. The compiler translates blocks of MIPS *.BBW BB Tools Extension machine code into a hardware design captured in Verilog Basic Block File (an "Extension"). The BBTools patch the application *.EXE M2V *.V Compiled (MIPS to Synthesizable binary by inserting the extension instruction that triggers Binary Verilog Verilog the accelerator. The original code is preserved, so that Executable Compiler) execution can fall back to software when necessary. GIANO *.EXE Simulator Patched Binary This work extends the M2V compiler with support for memory load and store instructions, and for interrupts. Figure 1: The eMIPS Tool Chain to automate the We use a transactional model to handle interrupts and/or generation of hardware accelerators. traps due to TLB misses in the Extension. We implemented Selection of the best code to accelerate is an active and tested the interrupt support mechanism using a 64-bit area of research. The eMIPS tool-chain, shown in Figure division basic block, with added instructions for memory 1, restricts the code selection problem to the set of basic loads off the stack pointer. blocks in the application. Using the strict definition in [1], We also added the feature of allowing the BBTools to the basic block is a directed acyclic graph (DAG). A automatically create the best encoding for an extension DAG is a set of machine instructions that do not contain instruction. The tool now evaluates which pair of roots in branches and are branched-to only for the very first the dependency graph leads to the shortest execution instruction. The best candidate blocks are currently cycle time for the Extension. With this addition, the selected by executing the application using the Giano full- process of creating Extensions for the eMIPS processor system simulator [21], in concert with the data obtained can now be fully automated and applied to practical via static analysis of the application binary. The BBTools applications, where loads and stores inside the Extension select the basic blocks to accelerate and patch the binary are of paramount importance. image with the special instructions for the accelerator. The M2V compiler [16] automatically generates the 1 Introduction design for the hardware accelerator, which is then synthesized using the Xilinx tools for the ML40x boards. Extensible processors have a simple RISC pipeline The accelerator can be statically loaded when eMIPS and the ability to augment the Instruction Set Architecture is reset or it can be dynamically loaded when an (ISA) with custom instructions. The ISA can be application is loaded using partial reconfiguration of the augmented statically, at tape-out, or it can be augmented FPGA. By dynamically loading and unloading dynamically when applications are loaded. Extensible accelerators, the area of the programmable hardware can processors differ from other accelerators in their tight be used more efficiently. integration with the basic data path, which leads to In previous versions of eMIPS, the accelerator blocks minimal latencies and therefore greater flexibility. could be specified and given to a hardware designer to Examples of dynamically extensible processors include hand design the accelerator. While this can lead to an eMIPS [6] and Stretch [13]. Tensilica’s Xtensa [14] is an efficient implementation, manual designs do not scale well example of a statically extensible processor. - 3 - as dynamically extensible processors are more widely The third limitation addresses the task of used and the hardware becomes more complex. To automatically choosing an instruction encoding for the effectively utilize dynamically extensible processors, new extension instruction. We observed that the selection different parts of an application can be accelerated using of which registers or constants to encode in the instruction different Extensions, which can be loaded at appropriate can have an effect on the overall execution time. These times. The use of the tool chain along with M2V can values are available early in the execution pipeline. It is expand the use of hardware acceleration and completely therefore important to select those that allow the most automate the process of generating hardware accelerators work to proceed before stalling on a dependency. Our for a variety of basic blocks in an application. algorithm uses two parameters in deciding which two The work described herein addresses three limitations register numbers to encode – fan-out and depth of the root in the tool chain that prevented the M2V tool chain from register read nodes. It selects the pair of registers with the being usable in but a few practical cases. The first maximum combined fan-out and depth. limitation was the lack of support for load and store The remainder of this document is structured as operations, and more generally for variable-cost follows. Section 2 discusses related work. Section 3 gives operations. M2V was previously only able to cope with an overview of the eMIPS hardware platform. Section 4 MIPS instructions that took zero or one cycle. We added discusses the automatic encoding of the extension support for all the instructions that took a fixed number of instruction by the BBTools. Section 5 defines the support cycles, accounting for the cost in the generation of the for memory operations in the M2V compiler. Section 6 schedule. Then we added support for the instructions that discusses the model and implementation for handling have variable costs, prime and foremost loads and stores. interrupts in the Extension. Section 7 explains the M2V We were able to find a way to preserve the overall generated hardware in more detail. Section 8 compares structure of the compiler, while dealing with the variable the synthesis reports obtained for Extensions generated costs. The dependency graph still leads to a state machine with and without the transactional model enabled. Section that controls the overall execution. The transitions are now 9 discusses the experimental results, and Section 10 defined not only by the clock, but also by the signals that concludes the report. Appendix I contains the BBW file indicate completion of the variable-cost operations. for the example basic block. Appendix II contains The second limitation concerns the inability of the synthesis reports for the Extension generated by the M2V M2V compiler to generate logic for handling interrupts compiler. Appendix III contains the Verilog output from within an Extension. External interrupts could only M2V, with the transactional model enabled and interrupt happen before or after the extension instruction, never support. Appendix IV shows an automated visualization inside it. This assumption is invalid in the presence of of the dependency graphs from M2V. TLB misses due to loads and stores. Furthermore, the previous tool required that an Extension never encounter 2 Related Work errors, such as arithmetic overflows or unaligned addresses. For a real-time system, it is important to Work on extensible processors can be divided in respond to interrupts in a timely and predictable manner. several ways. One avenue of exploration is to define the Even in a general-purpose OS it is unacceptable to allow a underlying hardware. Chimaera [7] and GARP [8] are user process to ignore interrupts and lock the machine. To two examples of extensible hardware from the late 1990’s. address the interrupt limitation, we used the concept of Commercial FPGA manufacturers today all provide transactions in dealing with the write-backs to the register examples of soft-cores, microprocessor designs that the file and the stores to memory. The overall execution of the customer can modify and extend for their application [15, Extension is subdivided in sets that execute “atomically”. 3, 13]. M2V uses the eMIPS processor [6] as its Interruptions of any sort are accepted at the transaction underlying hardware platform. eMIPS is the first design boundaries. On interruption, the write-back machine that is secure for general purpose multi-user loads, and the cancels all write-backs from future transactions, completes set of potential applications is therefore more open-ended the write-backs for the current one, and then relinquishes than those found in the typical embedded system alone. control back to the data-path in a limited amount of time. A common approach to generate code for an The restart-address is set to the point in the original basic extensible processor is to modify an existing C compiler. block that corresponds to the current write-back state. It is Tensilica [14] automatically regenerates a full GNU therefore mandatory that extension instructions are simply compilation system given the RTL of the new instruction. inserted in the original image, and that they do not replace Ienne et al. [4] use the SUIF compiler. M2V accepts as the original basic block. input binary machine code rather than source code. There are trade-offs between accelerating from source code in a - 4 - high-level language or from binaries. One of the major the basic block, so that it can identify repeating basic advantages when accelerating from binaries is that any blocks in the binary. application can be accelerated, even applications where the source code is controlled by an outside party and not 3 eMIPS Hardware Overview available to the system developer.
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