Smart Technology Choices I.MX

Smart Technology Choices and Leadership i.MX Applications Processors Shanghai FD SOI Forum

Ronald Martino | Vice President, i.MX Applications Processor Business and Advanced Technology Adoption

SEPT.15.2015

External Use

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, MagniiV, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, QorIQ Qonverge, Qorivva, Ready Play, SafeAssure, the SafeAssure logo, StarCore, Symphony, VortiQa, Vybrid and Xtrinsic are trademarks of Freescale Semiconctor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MXC, Platform in a Package, QUICC Engine, SMARTMOS, Tower, TurboLink and UMEMS are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. ARM, Cortex and TrustZone are trademark(s) or registered trademarks of ARM Ltd or its subsidiaries in the EU and/or elsewhere. All rights reserved. © 2015 Freescale Semiconductor, Inc. Smart World SECURE, CONNECTED, LOW-POWER, SCALABLE

Smart Internet of Things Homes Smart Highways Smart Smart Hospitals Energy

Smart Cities Smart Software Industrial Smart Ease-of-use Connected Homes Cars Open-source Security Connected Device Management World Professional Services Solutions Embedded Processing Connectivity Protocols Multi-Sensing Applications Technology Innovations Video | Image | Graphics | Voice Advanced NVM, RF, Mixed Signal Analog, and Sensors integration Powerful, Secure, Low-Power MCUs & Applications Processors System Miniaturization & Advanced Packaging

TM External Use 1 i.MX Driving Explosive Growth in Smart Vehicles & Smart Devices

2012 eReader Inventory Correction Over 200M i.MX SOCs shipped to date

2010 Over 35M vehicles enabled My Ford Touch Introduction Powered by i.MX with i.MX since 2007

Leader in eReaders and Auto Infotainment MPU

2007 2008 2009 2010 2011 2012 2013 2014 2015 i.MX i.MX Auto

TM External Use 2 i.MX 6 Series: Supreme Scalability and Flexibility Leverage One Design Into Diverse Product Portfolio

Scalable series of NINE ARM-based SoC Families

i.MX 6UltraLite i.MX 6SoloLite i.MX 6SoloX i.MX 6Solo i.MX 6DualLite i.MX 6Dual i.MX 6DualPlus i.MX 6Quad i.MX 6QuadPlus

i.MX i.MX i.MX i.MX i.MX i.MX i.MX i.MX i.MX 6UltraLite 6SoloLite 6SoloX 6Solo Family 6DualLite 6Dual Family 6DualPlus 6Quad Family 6QuadPlus Family Family Family Family Family Family

Pin-to-pin Compatible

Software Compatible

Expanded series for performance, power efficiency and lower BOM

TM External Use 3 Recently Announced i.MX 7D & 7S Advantages

• Advanced Heterogeneous • Unmatched Power Efficiency Architecture − 3x improvement in Power Efficiency − Single and Dual Cortex-A7 vs i.MX 6 Core up to 1GHz − 100 uW/MHz for Cortex-A7

− Cortex-M4 up to 266MHz − 70 uW/MHz for Cortex-M4

. Offload Tasks − One third the power consumed in . Optimize Power the Low Power suspend mode Corte Cortex-A7 Cortex-A7 . Increase Security x-M4 (250uW) vs i.MX 6

Bus Fabric

• Enabling Flexible High • Complete Security Infrastructure Speed Connectivity − Secure Boot − PCI-e v2.1 − Crypto H/W Acceleration − Dual Gbit Ethernet with AVB − Internal and External Tamper − DDR QuadSPI support Detection − eMMC 5.0 − Secure RAM − DPA attack Resistance − Secure JTAG

TM External Use 4 Processing Power Efficiency

2 Core-only

1.6

1.2

0.8

0.4 28nm for MPU & MCU Active ) mW/MHz ( PowerActive

0 2010 2012 2014 2016 2017 2018

ARM® Cortex®-M0+ ARM Cortex-M4 ARM Cortex-A9/Ax

TM External Use 5 i.MX Processor Roadmap Two New i.MX Platforms Based on 28nm FD SOI Technology

i.MX 6QuadPlus

i.MX 6Quad i.MX 6DualPlus i.MX 8 series i.MX 6Dual Advanced Graphics & Performance ARM ® v8-A i.MX 6DualLite i.MX 6Solo i.MX 7 series i.MX 6SoloX Power Efficiency ARM® v7-A i.MX 6SoloLite

i.MX 6UltraLite ARM® v7-A

TM External Use 6 End Nodes TODAY

MCU MPU

Analog Wide-band Sensors High- RF (MEMS) Low- Performance power NVM Core Core

Narrow-band Optics (Camera) RF Analog

Power Management Antennas Batteries (PMIC/PMU)

TM External Use 7 Increasing Integration of Diverse Components

Diversification

Precision RF HV NVM Sensors Biochips Analog

180nm Sense, Acquisition & 130nm Connectivity 90nm Functionality

65nm

40nm Computational & 28nm

Miniaturization Graphics Functionality 14nm . . . Leading-edge Longer-lasting process nodes shrink nodes (45, 32…14FF) (40, 28…??) driven mainly by offer mixed-signal digital SoC integration opportunity

TM External Use 8 End Nodes of TOMORROW

Analog Wide-band Sensors High- RF (MEMS) Performance Low-power NVM Core Core

Optics (Camera) Narrow-band RF Analog

Power Management Antennas Energy Sources (PMIC/PMU)

Complete Integration Scaled and all-in-one small, thin form factor package

TM External Use 9 Moore’s Law “No Exponential is Forever…but Forever can be Delayed”

Recent scaling and performance improvements driven by unprecedented technical innovation on silicon 10 mm

Immersion Cu Metallization Lithography (220nm) (45/40nm) 1 mm

High k / Metal Gate (32/28nm)

100 nm FinFET (22/16/14nm)

10 nm Low-k ILD (130/90nm) Strained Si

(90/65nm) (from TSMC) 1 nm 1970 1980 1990 2000 2010 2020 FD-SOI (28/22nm) (from STMicroelectronics)

TM External Use 10 Freescale Process Development Strategy

• CMOS Platform-Based Technologies: − Leverage foundry standard SmartMOS e-Non technology Power & Volatile Analog Memory − Adapt for targeted applications

Sensors Packaging • Differentiating Technologies: − Focus on

Differentiation High performance/features RF Performance CMOS eNVM SOI −

Feature / Performance / Feature High re-use >80% of the technology

CMOS platform CMOS RF

− Wholly-owned Platform Analog Degree of Partnering intellectual property UHV

TM External Use 11 Smart Technology Choices

1 Which node?

i.MX Which process 2 architecture?

TM External Use 12 28nm – ‘Last Simple Node?’

11 50% INCREASE in COST

Wafer Cost normalized to 0.25um cost 6.0

1.0 .18um .13um 90nm 65nm 40nm 28nm 14/16nm (High-K (FinFET) Metal Gate)

40nm to 28nm will be significant % of worldwide capacity in 2020

TM External Use 13 Cost Vs. Performance

i.MX Die Cost Comparison: 16FF vs 28FD 160% Relative Wafer Price 150% 150% 175% 200% 140% 130% 120% 110%

100% Die Cost 16FF/28FD Cost Die 90% 80% 0.00 25.00 50.00 75.00 100.00 125.00 150.00 Die Size

i.MX Processors • Large range of die size • Pads and overhead not scaling • Larger amount of analog • Future RF integration

TM External Use 14 Freescale History Leveraging SOI

4500 4500 Alpha SER Alpha SER 4000 4000 Neutron SER Neutron SER 3500 3500

3000 3000

2500 2500

2000 2000

1500 1500 Soft Error Rate (FITs/Mb) ErrorRate Soft 1000 (FITs/Mb) ErrorRate Soft 1000

500 500

0 0 130nm (B) 90nm 65nm 130nmSOI 90nmSOI 45nmSOI

• Freescale has developed 20+ processors over 3 generations of SOI technology • Soft Error Rate (SER) is becoming an increasingly significant factor as SoC memory arrays continue to increase in size & density • Bulk technology performs successively worse with each technology node • SOI provides 5 ~ 10x better SER reliability and the gap is widening as geometries shrink • 28 FD SOI benefits extend to 10-100X better immunity

TM External Use 15 SER Comparison

Technology Intrinsic (Technology) SER Product-Level SER

28nm Bulk Si Moderate Design techniques / protection

Protection techniques depend on amount 28nm FD-SOI Low of memory and logic content

Protection techniques depend on amount 14/16nm FinFET Low of memory and logic content

TM External Use 16 Freescale Leveraging SOI for Power Management ICs

NSD Oxide NSD NSD NSD NSD PSD NSD

Substrate Substrate Tie / Ground Plane Substrate Substrate Tie / Ground Plane

Grown Deep Trench Oxide EPI Device1 EPI Device2

SOI Bottom Oxide (BOX) Wafer N Silicon Substrate

• Each component is surrounded on all sides by hard ground plane • Each component or group of components is surrounded by oxide isolation • No parasitic components to substrate.

• System-level voltage expansion and physical area shrink by eliminating substrate injection and device cross-talk concerns in design.

TM External Use 17 FD SOI Advantages

Power-Performance Benefits Low Vdd with Performance 1 Improved Electrostatics Scalable Platform

Analog & RF Characteristics 2 Better Gain, Matching, Noise Gate 1st Integration i.MX Lower Risk Manufacturing 3 Simple Integration / Fast TAT Extends 28nm install base Low complexity planar device

TM External Use 18 28nm FD-SOI Platform

Logic Gate Leakage/Performance Metric

T=25C Vdd=0.8V, 1.1V

Forward Back Bias Back-bias enables large dynamic operating range

Good power-performance at low voltages, temperatures (IOT standby mode) FOMLeakage Reverse Back Bias

Frequency FOM Each point represents simulated average over three X1 library cells from a unique Vt-L combination. Ignores interconnect impact, which is highly implementation dependent

TM External Use 19 Process Technology Implications

28nm & Beyond High-K Metal Gate FD-SOI FinFET

Energy Efficiency

Cost Competitiveness

Ease of Design

Ease of Diversification

Multi-Cores Memory Non-volatile RF Connectivity • Power Management • Secure Java / OS support Memory • Wireless Everywhere • Performance • Connectivity S/W stack • Program Complexity • Security / ARM® TrustZone • Data Collection

TM External Use 20 FD SOI Gaps Addressed by Freescale

Utilizing Full Range of Back-Gate Biasing 1 Extended Bias Range BEOL TDDB Rules Enhanced Voltage Management Expanding Richness 2 of Design Collateral DDK Enhancements i.MX RAM Compiler Enhancements IO Enhancements Enabling Auto Quality 3 and Analog IP Unique Design Rules & Verification Supporting Multiple IP Vendors Auto Aging Use Case

TM External Use 21 Single A53 @ >1.2 GHz

Lower Power & Smaller Area • Leveraging Bias Range • Scalable Performance

Subsystem Attributes 28 FD SOI Alternative 28nm

Instances 550K 1250K

Leakage (Typical / WC) 70 / 175mA 125 / 315mA

Normalized dynamic power 0.75 1.0

Area 1.3 sqmm 1.7 sqmm

TM External Use 22 i.MX 8 Coming Soon…

Leveraging superset design… MIPI_CSI MIPI_CSI Connectivity

• ARM® V8-A 64 bit architecture DDR • 10+ core complex DDR Multimedia − Cortex-A72, Cortex-A53... • Enhanced graphics SCU DB Imagin Audio • Leadership 4k video Digital Logic g

ss_imaging Mixed Signal Logic • Integrated vision Mixed Signal Logic Display Core Complex Display • Low power 4k multi-display Ctrl (A53/A72) Ctrl • Mixed signal Mixed Signal Logic • Rich connectivity • Compelling auto features 28nm Technology Positioning FD SOI for leadership in broad market applications processors

TM External Use 23 Summary

• The evolving smart world requires a broad range of applications processors

• I/O counts, integrated PHYs and interface speeds are increasing

• Integration of functions in a cost effective technology is required for success

• 28 FD SOI offers advantages that allows scaling from small power efficient processors to high performance safety critical processors

• Freescale’s broad i.MX product portfolio and technology adoption strategy enables cost-effective ground-breaking solutions

• Future roadmap for i.MX will leverage 14nm class devices in order to scale power-performance when market demand justifies higher cost and expense of development

TM External Use 24 TM