DOCSLIB.ORG

Winidea 2012 Release Notes

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Winidea 2012 Release Notes _ RELEASE NOTES winIDEA 2012 / 9.12 9.12.1 (18.1.2012) CPU Support Renesas 78k RL78 Family On-Chip-Debug support Full debug feature set for G13 and F12 lines is supported on iC5000 platform. isystem.connect Profiler controller classes CProfilerController2 and CProfilerData2 classes provide access to profiler configuration and recorded data access. For more information see Help/SDK/isystem.connect. iSYSTEM, September 2018 1/169 9.12.2 (31.1.2012) CPU Support MPC 5xxx MPC5676R Cobra Support Full debug and trace feature set for MPC and eTPU cores. Preliminary support for dual eDMA trace. winIDEA Analyzer Bookmarks Any number of bookmarks can be set in the trace and timeline views using the Ctrl+F2 shortcut. The F2 shortcut moves from one bookmark to another. Watch window Expanded watch structure Watch window retains expanded structure of a complex type even if the expression goes out of scope. iSYSTEM, September 2018 2/169 When out of scope, the structure is retained, but Value reflects Note: If the expression is changed or the expression can evaluate to a different type in a changed context, the structure is collapsed. Binary constants Binary constants of the form <digits>b are recognized. e.g. 100b == 4 This format should be used if one intends to modify binary values in the watch window. Other binary display formats cannot be used to modify the value. iSYSTEM, September 2018 3/169 isystem.connect Hot attach/detach capability IConnectDebug::RunControl provides means to hot-attach the target. CExecutionController::hotAttach() and hotDetach() can be used from scripts. Refer to online SDK help for more information. iSYSTEM, September 2018 4/169 9.12.3 (3.2.2012) CPU Support MPC 5xxx MPC5676R Cobra Support Dual eDMA trace support. winIDEA Analyzer Profiler XML Export can generate binary timeline file, which is more compact and faster to generate and parse. XML node indenting is now optional. Indenting can increase file size by up to 15% but yields no benefits for automatic parsers. iSYSTEM, September 2018 5/169 9.12.4 (15.2.2012) CPU Support Incremental FLASH programming When a download is performed into an already programmed device, (optionally) only the FLASH sectors which have been modified, are be programmed. This speeds up download times when only small changes are performed. Incremental FLASH programming is supported on these CPUs: MPC5xxx TriCore XC2000 User configurable Reset duration is provided. This may be required by target specific configuration. TriCore User configurable Reset duration is provided. This may be required by target specific configuration. iSYSTEM, September 2018 6/169 winIDEA Analyzer Session duration limit Profiler session duration can be limited to millisecond range. Multiple IRQ level support Multiple IRQ levels can be configured for OS objects. This allows profiling of nested interrupts. See ProfilerConcepts.pdf for more information. Download in Hot Attach configuration Optionally, winIDEA can upon Debug/Download command, disable Hot Attach and perform regular download. Intialize debugger, load symbols: initialize debugger hardware and loads symbols. This is the default setting. Initialize, attach to CPU, download code: performs regular download, bypassing hot attach configuration. After download the Hot Attach capabilities are restored. iSYSTEM, September 2018 7/169 Location: Debug/Files for Download/Options Watch expressions Full SFR path is supported in watch expressions. This allows display of SFRs with identical names belonging to different CPU modules. Same syntax can be used to access SFR registers via isystem.connect. iSYSTEM, September 2018 8/169 9.12.6 (19.2.2012) CPU Support MPC 5xxx Mass erase before download Program and Data FLASH can be (optionally) erased before download. Location: Hardware.Emulation Options/CPU/Setup/MPC5xxx Default: OFF Bolero3M device unsecure Unsecure with password is implemented. winIDEA Analyzer Context re-activation support Per default the profiler ignores repeated task IDs and considers that the same task/IRQ continues without interruption. iSYSTEM, September 2018 9/169 Optionally, re-activation can be considered as a separate activation of the context. The changed interpretation will be reflected in the statistics for the task. Location: Analyzer/Profiler/Advanced/Ignore context reactivation Default: ON Neutral value for task level objects For Task level objects the neutral value can be specified (like for IRQ objects). Typically the NO_TASK state can be specified as 'neutral' and is indicated with a fatter line in the timeline. iSYSTEM, September 2018 10/169 9.12.7 (24.2.2012) winIDEA Slow Run Execution of the target application can be performed one instruction at a time, which allows acquisition of full program trace. This allows all Analyzer analyses also on CPUs without trace. Location: Debug/Use Slow Run Default: OFF When CPU is running, the status shows the number of executed instructions. The Analyzer will show all executed instructions, the time stamp for every instruction advances by 1 ns. iSYSTEM, September 2018 11/169 Analyzer Min / Max / Average statistics for regular variables and analog AUX For regular variables and analog AUX who can assume arbitrary number of values, these statistics are provided: Minimum value Maximum value Average value Note: average value considers also the durations of a particular value. e.g. if a variable keeps a value of 0 for 9 seconds and a value of 10 for 1 second, the average value will be 1. iSYSTEM, September 2018 12/169 9.12.8 (5.3.2012) CPU Support HCS08 MC9S08MP16R support Full feature set implemented. winIDEA Analyzer Navigation to Min/Max extremes sets markers Marker 1 is set to the beginning of the extreme, and Marker 2 to the end. Caret is also set to the end. isystem.connect Trace control CTraceController is the new class for trace recording and export. CTraceData can be used to read XML or binary trace export files. For further information and examples refer to online SDK documentation. iSYSTEM, September 2018 13/169 9.12.9 (7.3.2012) CPU Support HCS12 MC9S12XHY support Full feature set implemented. TriCore TC1791 support Full feature set implemented. winIDEA Debug Ambiguity resolution dialog now displays also the address of possible symbols. iSYSTEM, September 2018 14/169 9.12.11 (14.3.2012) winIDEA Analyzer Profiler execution in RTOS application Before a Task/IRQ context is known, the code execution can be ignored. The recorded code is attributed to an unknown context which doesn’t exist in the application. If on the other hand the application is profiled from CPU start, the OS is not active yet and the unknown context is a valid state, the option should be disabled. iSYSTEM, September 2018 15/169 9.12.12 (16.3.2012) winIDEA Symbols winIDEA per default saves the symbol table from the previous download session alongside the workspace file. This allows symbol navigation and reconstruction of analyzer recordings immediately when workspace is opened. If saving of symbols is not desired, the option can be switched off. Location: Debug/Options/Symbols/Preserve symbols between winIDEA sessions Default: ON Analyzer Custom defined filters can use bitwise operators Filters can use standard C bitwise operators & | and ^. iSYSTEM, September 2018 16/169 9.12.13 (21.3.2012) CPU Support HCS08 HCS08JM8, HCS08JM16,HCS08JM32, HCS08JM60, full feature set. winIDEA Build Manager For assembler includes winIDEA can optionally (not) search the source file folder. If the Search also source file folder option is set (default), then first the folder of the source file is checked before all listed includes search paths are checked. This is equivalent to C’s: #include “filename” If this option is disabled, the source file folder is not checked and is equivalent to C’s #include <filename> Location: Project/Settings/Includes/Search also source file folder Default: ON Note: always verify that the thus specified algorithm is the same as the assembler implements. iSYSTEM, September 2018 17/169 Analyzer Analyze only events after start point Profiler will per default analyze the entire session, including events which occur before the starting point. To limit the analysis to events after starting point, set this option. iSYSTEM, September 2018 18/169 9.12.14 (27.3.2012) CPU Support S12Z The new Freescale S12Z family of CPUs is supported. eTPU Data profiler is available. Up to 4 data areas can be profiled. winIDEA Disassembly window Disassembly window provides a toolbar, including new navigation functions. Disassemble to disk Go to execution point Go back to previous indicator position List from branch target. This command is available only on direct branches. List from start of the current function. List from end of the current function. Shows the function and offset of the indicator to the start. Browse a function and list from its start. isystem.test R8C Stub support Stubs are supported on R8C IAR and Renesas compilers. iSYSTEM, September 2018 19/169 9.12.15 (28.3.2012) winIDEA isystem.test HC12 Cosmic compiler support for +nowiden option This information cannot be determined from the Elf file and must be explicitly configured in Test/Options… Note: per default the compiler widens the char and float parameters to int and double respectively. iSYSTEM, September 2018 20/169 9.12.18 (4.4.2012) winIDEA Analyzer Bit level data profiling If a data object is composed of several distinct sub-items (bit fields,…), a part of the data object can be extracted by specifying its bit size and bit offset within the parent data object. Several data objects can be defined on top of a parent data entity. Refer to ProfilerConcepts.pdf for more information especially on big endian systems. Data profiling unlimited variables Per default the analyzer will attempt to use one hardware data comparator per data area. On most on-chip trace systems, the number of these comparator is small and insufficient.
Load more

Recommended publications
  • 08-02-2021 Agenda Packet.Pdf
    AGENDA DELANO CITY COUNCIL REGULAR MEETING August 2, 2021 DELANO CITY HALL, 1015 – 11th Avenue 5:30 P.M. IN ACCORDANCE WITH THE GOVERNOR NEWSOM’S EXECUTIVE ORDER #N-08-21, THIS MEETING WILL BE CONDUCTED FULLY VIA TELECONFERENCE, DUE TO THE CURRENT RESTRICTIONS BY SAID ORDER AND CENTERS FOR DISEASES CONTROL AND PREVENTION (CDC) GUIDELINES. THE PUBLIC WILL HAVE ACCESS TO CALL IN, LISTEN TO THE MEETING AND PROVIDE PUBLIC COMMENT. IN ACCORDANCE WITH GOVERNOR NEWSOM’S EXECUTIVE ORDER N-08-21, THERE WILL NOT BE A PHYSICAL LOCATION FROM WHICH THE PUBLIC MAY ATTEND. IN ORDER TO CALL INTO TH E MEETING PLEASE SEE THE DIRECTIONS BELOW. CALL TO ORDER INVOCATION FLAG SALUTE ROLL CALL PRESENTATIONS AND AWARDS Featured Pet – Tabitha PUBLIC COMMENT: The public may address the Council on items which do not appear on the agenda. The Council cannot respond nor take action on items that do not appear on the agenda but may refer the item to staff for further study or for placement on a future agenda. Comments are limited to 3 minutes for each person and 15 minutes on each subject. Please state your name and address for the record. CONSENT AGENDA: The Consent Agenda consists of items that in staff’s opinion are routine and non-controversial. These items are approved in one motion unless a Councilmember or member of the public removes a particular item. 1) Authorization to waive the reading of any ordinance in its entirety and consenting to the reading of such ordinances by title only 2) Warrant Register in the amount of $3,044,398.54 3) Minutes of regular City Council Meeting of July 19, 2021 4) Acceptance and Approval of the City of Delano Quarterly Investment Report 5) Resolution adopting the 2020-2021 Kern Multi-Jurisdiction Hazard Mitigation Plan (MJHMP) 6) Approval of agreement with Youth Educational Sports, Inc.
    [Show full text]
  • Fill Your Boots: Enhanced Embedded Bootloader Exploits Via Fault Injection and Binary Analysis
    IACR Transactions on Cryptographic Hardware and Embedded Systems ISSN 2569-2925, Vol. 2021, No. 1, pp. 56–81. DOI:10.46586/tches.v2021.i1.56-81 Fill your Boots: Enhanced Embedded Bootloader Exploits via Fault Injection and Binary Analysis Jan Van den Herrewegen1, David Oswald1, Flavio D. Garcia1 and Qais Temeiza2 1 School of Computer Science, University of Birmingham, UK, {jxv572,d.f.oswald,f.garcia}@cs.bham.ac.uk 2 Independent Researcher, [email protected] Abstract. The bootloader of an embedded microcontroller is responsible for guarding the device’s internal (flash) memory, enforcing read/write protection mechanisms. Fault injection techniques such as voltage or clock glitching have been proven successful in bypassing such protection for specific microcontrollers, but this often requires expensive equipment and/or exhaustive search of the fault parameters. When multiple glitches are required (e.g., when countermeasures are in place) this search becomes of exponential complexity and thus infeasible. Another challenge which makes embedded bootloaders notoriously hard to analyse is their lack of debugging capabilities. This paper proposes a grey-box approach that leverages binary analysis and advanced software exploitation techniques combined with voltage glitching to develop a powerful attack methodology against embedded bootloaders. We showcase our techniques with three real-world microcontrollers as case studies: 1) we combine static and on-chip dynamic analysis to enable a Return-Oriented Programming exploit on the bootloader of the NXP LPC microcontrollers; 2) we leverage on-chip dynamic analysis on the bootloader of the popular STM8 microcontrollers to constrain the glitch parameter search, achieving the first fully-documented multi-glitch attack on a real-world target; 3) we apply symbolic execution to precisely aim voltage glitches at target instructions based on the execution path in the bootloader of the Renesas 78K0 automotive microcontroller.
    [Show full text]
  • Porting the Arduino Library to the Cypress Psoc in Psoc Creator
    Porting the Arduino Library to the Cypress PSoC in PSoC Creator Matt Durak November 11, 2011 Design Team 1 Abstract Arduino, the open-source electronic platform is a useful tool to hobbyists in building embedded systems. It provides an easy to use library which includes components to work with an Ethernet board, called the Ethernet shield. PSoC is a programmable system-on-chip made by Cypress Semiconductor. It is a very flexible platform which includes an ARM Cortex M3 processor. This application note includes the steps necessary to port parts of the Arduino library to the PSoC in order to use Arduino software and hardware, known as shields, with the PSoC. The note will cover many issues which must be overcome in porting this software. Keywords PSoC, Arduino, C++, C, Library, Software, Porting, PSoC Creator, Ethernet shield Introduction Arduino Library The Arduino is an open-source electronics hardware platform that is designed primarily for students and hobbyists (1). Arduino provides the schematics to build the hardware, as well as kits which can be pre- assembled or just include the parts. This application note will focus on the software for Arduino. Arduino has its own open-source development environment based on Wiring, a platform for programming electronics (2). The software library used by Arduino is written in C++ and is also open-source and freely available (3). This library is composed of a low layer which communicates directly with hardware registers and provides an abstraction for programmers to set whether a pin is an input or an output and to read and write to those pins.
    [Show full text]
  • Schedule 14A Employee Slides Supertex Sunnyvale
    UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 SCHEDULE 14A Proxy Statement Pursuant to Section 14(a) of the Securities Exchange Act of 1934 Filed by the Registrant Filed by a Party other than the Registrant Check the appropriate box: Preliminary Proxy Statement Confidential, for Use of the Commission Only (as permitted by Rule 14a-6(e)(2)) Definitive Proxy Statement Definitive Additional Materials Soliciting Material Pursuant to §240.14a-12 Supertex, Inc. (Name of Registrant as Specified In Its Charter) Microchip Technology Incorporated (Name of Person(s) Filing Proxy Statement, if other than the Registrant) Payment of Filing Fee (Check the appropriate box): No fee required. Fee computed on table below per Exchange Act Rules 14a-6(i)(1) and 0-11. (1) Title of each class of securities to which transaction applies: (2) Aggregate number of securities to which transaction applies: (3) Per unit price or other underlying value of transaction computed pursuant to Exchange Act Rule 0-11 (set forth the amount on which the filing fee is calculated and state how it was determined): (4) Proposed maximum aggregate value of transaction: (5) Total fee paid: Fee paid previously with preliminary materials. Check box if any part of the fee is offset as provided by Exchange Act Rule 0-11(a)(2) and identify the filing for which the offsetting fee was paid previously. Identify the previous filing by registration statement number, or the Form or Schedule and the date of its filing. (1) Amount Previously Paid: (2) Form, Schedule or Registration Statement No.: (3) Filing Party: (4) Date Filed: Filed by Microchip Technology Incorporated Pursuant to Rule 14a-12 of the Securities Exchange Act of 1934 Subject Company: Supertex, Inc.
    [Show full text]
  • Getting Started with Psoc 6 MCU (AN221774)
    AN221774 Getting Started with PSoC 6 MCU Authors: Srinivas Nudurupati, Vaisakh K V Associated Part Family: All PSoC® 6 MCU devices Software Version: ModusToolbox™ 1.0, PSoC Creator™ 4.2 Associated Application Notes and Code Examples: Click here. More code examples? We heard you. To access an ever-growing list of hundreds of PSoC code examples, please visit our code examples web page. You can also explore the PSoC video library here. AN221774 introduces the PSoC 6 MCU, a dual-CPU programmable system-on-chip with Arm® Cortex®-M4 and Cortex-M0+ processors. This application note helps you explore PSoC 6 MCU architecture and development tools, and shows you how to create your first project using ModusToolbox and PSoC Creator. This application note also guides you to more resources available online to accelerate your learning about PSoC 6 MCU. To get started with the PSoC 6 MCU with BLE Connectivity device family, refer to AN210781 – Getting Started with PSoC 6 MCU with BLE Connectivity. Contents 1 Introduction .................................................................. 2 5.6 Part 4: Build the Application .............................. 32 1.1 Prerequisites ....................................................... 3 5.7 Part 5: Program the Device ............................... 33 2 Development Ecosystem ............................................. 4 5.8 Part 6: Test Your Design ................................... 34 2.1 PSoC Resources ................................................ 4 6 My First PSoC 6 MCU Design 2.2 Firmware/Application Development .................... 5 Using PSoC Creator .................................................. 36 2.3 Support for Other IDEs ....................................... 9 6.1 Using These Instructions .................................. 36 2.4 RTOS Support .................................................... 9 6.2 About the Design .............................................. 37 2.5 Debugging......................................................... 11 6.3 Part 1: Create a New Project from Scratch ......
    [Show full text]
  • MIPI Alliance Test and Debug - Nidnt-Port White Paper
    MIPI Alliance Test and Debug - NIDnT-Port White paper Approved Version: 1.0 – 10 January 2007 MIPI Board Approved for Public Distribution NOTE and DISCLAIMER: This is an informative document, not a MIPI Specification. Various rights and obligations which apply solely to MIPI Specifications (as defined in the MIPI Membership Agreement and MIPI Bylaws) including, but not limited to, patent license rights and obligations, do not apply to this document. The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled by any of the authors or developers of this material or MIPI. The material contained herein is provided on an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of negligence. ALSO, THERE IS NO WARRANTY OR CONDITION OF TITLE, QUIET ENJOYMENT, QUIET POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD TO THIS MATERIAL. IN NO EVENT WILL ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR ANY OTHER AGREEMENT RELATING TO THIS MATERIAL, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.
    [Show full text]
  • Freescale In-Circuit Emulator Base User Manual
    Freescale In-Circuit Emulator Base User Manual Rev. 1.1 1/2005 FSICEBASEUM How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses USA/Europe/Locations Not Listed: granted hereunder to design or fabricate any integrated circuits or integrated circuits based on Freescale Semiconductor Literature Distribution Center the information in this document. P.O. Box 5405 Freescale Semiconductor reserves the right to make changes without further notice to any Denver, Colorado 80217 products herein. Freescale Semiconductor makes no warranty, representation or guarantee 1-800-521-6274 or 480-768-2130 regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or Japan: circuit, and specifically disclaims any and all liability, including without limitation Freescale Semiconductor Japan Ltd. consequential or incidental damages. “Typical” parameters that may be provided in Freescale Technical Information Center Semiconductor data sheets and/or specifications can and do vary in different applications and 3-20-1, Minami-Azabu, Minato-ku actual performance may vary over time. All operating parameters, including “Typicals”, must Tokyo 106-8573, Japan be validated for each customer application by customer’s technical experts. Freescale 81-3-3440-3569 Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as Asia/Pacific: components in systems intended for surgical implant into the body, or other applications Freescale Semiconductor Hong Kong Ltd.
    [Show full text]
  • Computer Architectures
    Computer Architectures Motorola 68000, 683xx a ColdFire – CISC CPU Principles Demonstrated Czech Technical University in Prague, Faculty of Electrical Engineering AE0B36APO Computer Architectures Ver.1.10 1 Original Desktop/Workstation 680X0 Feature 68000 'EC000 68010 68020 68030 68040 68060 Data bus 16 8/16 16 8/16/32 8/16/32 32 32 Addr bus 23 23 23 32 32 32 32 Misaligned Addr - - - Yes Yes Yes Yes Virtual memory - - Yes Yes Yes Yes Yes Instruct Cache - - 3 256 256 4096 8192 Data Cache - - - - 256 4096 8192 Memory manager 68451 or 68851 68851 Yes Yes Yes ATC entries - - - - 22 64/64 64/64 FPU interface - - - 68881 or 68882 Internal FPU built-in FPU - - - - - Yes Yes Burst Memory - - - - Yes Yes Yes Bus Cycle type asynchronous both synchronous Data Bus Sizing - - - Yes Yes use 68150 Power (watts) 1.2 0.13-0.26 0.13 1.75 2.6 4-6 3.9-4.9 at frequency of 8.0 8-16 8 16-25 16-50 25-40 50-66 MIPS/kDhryst. 1.2/2.1 2.5/4.3 6.5/11 14/23 35/60 100/300 Transistors 68k 84k 190k 273k 1,170k 2,500k Introduction 1979 1982 1984 1987 1991 1994 AE0B36APO Computer Architectures 2 M68xxx/CPU32/ColdFire – Basic Registers Set 31 16 15 8 7 0 User programming D0 D1 model registers D2 D3 DATA REGISTERS D4 D5 D6 D7 16 15 0 A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 16 15 0 A7 (USP) USER STACK POINTER 0 PC PROGRAM COUNTER 15 8 7 0 0 CCR CONDITION CODE REGISTER 31 16 15 0 A7# (SSP) SUPERVISOR STACK Supervisor/system POINTER 15 8 7 0 programing model (CCR) SR STATUS REGISTER 31 0 basic registers VBR VECTOR BASE REGISTER 31 3 2 0 SFC ALTERNATE FUNCTION DFC CODE REGISTERS AE0B36APO Computer Architectures 3 Status Register – Conditional Code Part USER BYTE SYSTEM BYTE (CONDITION CODE REGISTER) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T1 T0 S 0 0 I2 I1 I0 0 0 0 X N Z V C TRACE INTERRUPT EXTEND ENABLE PRIORITY MASK NEGATIVE SUPERVISOR/USER ZERO STATE OVERFLOW CARRY ● N – negative ..
    [Show full text]
  • UDE Memtool FLASH/OTP Memory Programming Tool UDE Memtool Is a Tool for Programming On-Chip As Well As External FLASH/OTP and EPROM's
    UDE MemTool FLASH/OTP Memory Programming Tool UDE MemTool is a tool for programming on-chip as well as external FLASH/OTP and EPROM's. It integrates seamlessly with the UDE Universal Debug Engine Integrated Development Environment. UDE MemTool comes as add-in for the Universal Debug Engine (UDE) and allows the FLASH/OTP programming during the development cycle inside of UDE. UDE MemTool is aware of the memory map and runs the programming algorithm when required. UDE MemTool can be used with a separate frontend interface as tool. All programming functions are available via standard COM automation interfaces, too. Using these interfaces, the features of UDE MemTool may be integrated into automatic production and testsystems or started via scripts. Additionally, UDE MemTool offers a batch mode and a command line interface for automation purposes. UDE GangProgrammer can program FLASH memory devices simultaneously to save time and optimize the resource usage in a production environment. Functions of UDE MemTool UDE MemTool offers the following functions (depending on the type of memory): Erasing the entire memory module or selected sectors of the memory module Loading Intel Hex and Motorola S-Record files Programming all or selected portions of the file into the memory module Comparing all or selected portions of the file to the current contents of the memory module Read back and save-to-disk of the current memory content Setting and Resetting the Chip/Sector Protection if applicable (on-chip only) UCB (User Configuration Blocks), ABM (Alternate Boot Mode), BMI (Boot Mode Index) header handling for some derivatives. UDE MemTool can handle more than one memory module, and is using on-chip RAM.
    [Show full text]
  • MPC555 Interrupts by John Dunlop, Josef Fuchs, and Steve Mihalik Rev
    Order this document by: MOTOROLA AN2109/D SEMICONDUCTOR APPLICATION NOTE MPC555 Interrupts by John Dunlop, Josef Fuchs, and Steve Mihalik Rev. 0, 26 July 2001 1 Introduction The MPC555 has numerous timers, peripherals and input pins that can generate interrupts. This appli- cation note describes how the interrupts work and how to write software for their initialization and ser- vice routines. Examples illustrate how interrupt handler routines written in assembler, C and even controlled by an operating system can have a dramatic variation in overhead. This overhead is almost entirely caused by the amount of context, (i.e., registers), saved and restored in the routine. Although this application note focuses on interrupts, the discussion of context saving and restoring ap- plies to other exceptions as well as other Motorola PowerPC™ microcontrollers. In addition, later MPC5xx microprocessors include an enhanced interrupt controller which has features to reduce laten- cy. A summary of these features, which are optional to use in these later microcontrollers is listed in Section Appendix B Enhanced Interrupt Controller Summary. 2 Background 2.1 Interrupts versus Exceptions Definitions of “interrupts” and “exceptions” are not always consistent in PowerPC™ literature. The fol- lowing definitions are used for this application note. Exceptions are events that change normal program flow and machine state. Some examples of excep- tions are reset, decrementer passing zero, system call instruction, various bus access errors, and even a software or hardware debugger. When an exception occurs, a short hardware context switch takes place and the processor branches to an address (exception vector) which is unique for each type of ex- ception.
    [Show full text]
  • 8-Bit All Flash 78K0 Microcontrollers 78K0S
    For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [America] [Europe] [Asia & Oceania] NEC Electronics America, Inc. NEC Electronics (Europe) GmbH NEC Electronics (China) Co., Ltd 8-bit All Flash 2880 Scott Blvd. Arcadiastrasse 10 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian Santa Clara, CA 95050-2554, U.S.A. 40472 Düsseldorf, Germany District, Beijing 100083, P.R.China Tel: 408-588-6000 Tel: 0211-65030 Tel: 010-8235-1155 800-366-9782 http://www.eu.necel.com/ http://www.cn.necel.com/ http://www.am.necel.com/ Hanover Office Shanghai Branch Podbielskistrasse 166 B Room 2509-2510, Bank of ChinaTower, 30177 Hannover 200Y incheng Road Central, Tel: 0 511 33 40 2-0 Pudong New Area, Shanghai, P.R.China P.C:200120 Tel:021-5888-5400 Munich Office http://www.cn.necel.com/ Werner-Eckert-Strasse 9 81829 München Shenzhen Branch Tel: 0 89 92 10 03-0 Unit 01, 39/F, Excellence Times Square Building, Stuttgart Office No. 4068 Yi Tian Road, Futian District, Shenzhen, Industriestrasse 3 P.R.China P.C:518048 70565 Stuttgart Tel:0755-8282-9800 Tel: 0 711 99 01 0-0 http://www.cn.necel.com/ United Kingdom Branch NEC Electronics Hong Kong Ltd. Cygnus House, Sunrise Parkway Unit 1601-1613, 16/F., Tower 2, Grand Century Place, Linford Wood, Milton Keynes 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong MK14 6NP, U.K. Tel: 2886-9318 Tel: 01908-691-133 http://www.hk.necel.com/ Succursale Française 9, rue Paul Dautier, B.P.
    [Show full text]
  • Renesas RX62N RDK User's Manual
    Renesas Demonstration Kit (RDK) for RX62N User’s Manual: Hardware RENESAS MCU 32 RX Family / RX600 Series / RX62N Group R20UT2531EU0100 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). i Disclaimer By using this Renesas Demonstration Kit (RDK), the user accepts the following terms. The RDK is not guaranteed to be error free, and the User assumes the entire risk as to the results and performance of the RDK. The RDK is provided by Renesas on an “as is” basis without warranty of any kind whether express or implied, including but not limited to the implied warranties of satisfactory quality, fitness for a particular purpose, title and non-infringement of intellectual property rights with regard to the RDK. Renesas expressly disclaims all such warranties. Renesas or its affiliates shall in no event be liable for any loss of profit, loss of data, loss of contract, loss of business, damage to reputation or goodwill, any economic loss, any reprogramming or recall costs (whether the foregoing losses are direct or indirect) nor shall Renesas or its affiliates be liable for any other direct or indirect special, incidental or consequential damages arising out of or in relation to the use of this RDK, even if Renesas or its affiliates have been advised of the possibility of such damages.
    [Show full text]