Fabrication of Capacitors Based on Silicon Nanowire Arrays Generated by Metal-Assisted Wet Chemical Etching by Wen Zheng

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Fabrication of Capacitors Based on Silicon Nanowire Arrays Generated by Metal-Assisted Wet Chemical Etching By Wen Zheng

B.S. Department of Chemistry, Tsinghua University (2010)

SUBMITTED TO THE DEPARTMENT OF MATERIALS SCIENCE AND ENGINEERING IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY IN MATERIALS SCIENCE AND ENGINEERING AT THE MASSACHUSETTS INSTITUTE OF TECHNOLOGY

June 2016

Signature of Author . Department of Materials Science and Engineering May 20, 2016

Certified by . Carl V. Thompson Stavros Salapatas Professor of Materials Science and Engineering Thesis Supervisor

Accepted by . Donald R. Sadoway Chair, Departmental Committee on Graduate Studies

Fabrication of Capacitors Based on Silicon Nanowire Arrays

Generated by Metal-Assisted Wet Chemical Etching

By Wen Zheng

Submitted to the Department of Materials Science and Engineering at the Massachusetts Institute of Technology on May 20, 2016 in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy

Abstract

Capacitors with high capacitance density (capacitance per footprint area) have potential applications in autonomous microsystems that harvest energy from the environment, as they can store and release energy at high rates. Use of high surface-to-volume ratio structures has been demonstrated as an effective way to increase the electrode area, and therefore to improve the capacitance density, while still keeping the footprint area low. The goal of this thesis was to first develop an understanding of the mechanisms of metal assisted wet chemical etching for fabrication of arrays of silicon nanowires, and then use this understanding to build nanowire array on-chip capacitors in silicon substrates, in order to eliminate additional packaging and enable local and efficient energy delivery. Two types of capacitors were investigated: electrostatic metal-oxide- semiconductor (MOS) capacitors for power management, and supercapacitors for energy storage purposes. For both types of devices, enlarged surface area per footprint was achieved by utilizing the arrays of silicon nanowires. Fundamental studies of the roles of metals in metal-assisted chemical etching (MACE) of silicon were conducted. Lithography techniques were used to generate patterns in metal films which when subjected to MACE resulted in formation of ordered arrays of silicon nanowires. Investigation of various metal catalysts showed that Pt is a more active catalyst than Au, while Cu is not stable in the etchant. Tapered silicon nanowires can be generated by adding a layer of Cu between two Au layers, and etching occurs much faster than when a pure Au catalyst is used.

While carrying out research on the mechanisms of MACE, we developed a new electrochemical method for formation of arrays of silicon nanowires, metal-assisted anodic etching (MAAE). In this process, the etchant consists of HF alone, and does not include an oxidant. In both processes, HF is used as an etchant. However, in MACE, electronic holes are supplied through reduction of an oxidant (e.g. H2O2), while in MAAE, electronic holes are supplied through an external circuit, with anodic contact to either the metal or the silicon. In both contact cases for MAAE, the metal catalyzes the etching process and leads to controlled formation of silicon nanowires, without the need for an oxidant. This discovery, and its analysis, provided new insights into the mechanisms of both MAAE and MACE, and also opened the possibility for use of metal catalyzed electrochemical etching of other materials that cannot survive the HF/oxidant mixture. Processes for fabrication of on-chip capacitors based on silicon nanowires were next developed. We first fabricated on-chip MOS capacitors with nanowire arrays etched using MACE with both single crystal silicon substrates and polycrystalline silicon films. For wires made in both cases, the capacitance density followed a same scaling trend related to their geometries. Epitaxial wafers were used with a post-etch doping process to reduce the series resistance in the devices in order to obtain a better frequency response, as desired for high frequency circuits. To achieve higher capacitance densities for energy storage purposes, we also designed a solid state supercapacitor device based on nanowires etched using MAAE with heavily doped n-type silicon substrates. The silicon nanowires were coated with RuO2 using atomic layer deposition (ALD) to achieve a high capacitance. In this case, charge is stored through the formation of an electrical double layer and through reversible redox reactions. We showed that the capacitance density of these devices roughly scaled with the increased surface area of silicon nanowire arrays. The solid state supercapacitor achieved a capacitance density of 6.5mF/cm2, which is comparable to the best results achieved with other types of on-chip supercapacitors. In contrast with other processes for forming on-chip supercapacitors, the supercapacitors we demonstrated were fabricated using a fully complementary metal-oxide-semiconductor (CMOS) technology compatible process. Moreover, the Si nanowire-based device achieved this high capacitance density without sacrificing power performance compared to the planar device.

Thesis Supervisor: Carl V. Thompson Stavros Salapatas Professor of Materials Science and Engineering 3

Acknowledgement

First of all, I would like to thank my advisor, Professor Carl V. Thompson, for his guidance and support during my time at MIT. He is an advisor who really cares about his students. As a tremendous mentor, he has been extremely encouraging with patience to help me overcome the difficulties. His visions always inspired me to look at things from a new perspective. I would also like to thank my committee members, Professor Caroline Ross and Professor Eugene Fitzgerald, for their kindness and valuable comments on my research. I did most of my work using MTL, NSL and CMSE facilities. I would like to thank all the research staffs, in particular Kurt Broderick at MTL and James Daley at NSL, who have been extremely helpful in offering technical support. I want to thank my colleagues in the Materials for Micro and Nano Systems Group, especially Ahmed Al-Obeidi, Changquan Lai for their useful discussions and valuable collaborations. I also want to thank Robert Mitchell, Hang Yu, Gye Hyun Kim, Thomas Batcho, Jinghui Miao, Lin Xu, Yoon Ah Shin, Hangbo Zhao and other past members of the group. It has been a great honor for me to work with them all. A special thanks to my friends and family, especially to my parents, my mother-in-law and father-in-law for all the sacrifices that they have made on my behalf. Finally, I would like to express my deepest gratitude to my beloved husband, Zhongying Wang. Thank you for believing in me and encouraging me through tough moments. To my beloved daughter Emily Jiayao Wang, who has been a source of endless joy and strength for me. I cannot be more grateful for having your company towards the end of this experience.

Table of Contents

Introduction ...... 24

1.1 Motivation and background ...... 24

1.2 Metal-assisted chemical etching (MACE) ...... 25

1.2.1 Comparison with other fabrication techniques for silicon nanowires ...... 25

1.2.2 Mechanism ...... 30

1.2.3 Factors influencing MACE ...... 34

1.2.4 Applications to semiconductors other than silicon ...... 40

1.3 Literature review on two types of on-chip capacitors ...... 42

1.3.1 Silicon based metal-oxide-semiconductor (MOS) capacitors ...... 42

1.3.2 On-chip supercapacitors ...... 49

Metal-Assisted Anodic Etching (MAAE) ...... 58

2.1 Introduction ...... 58

2.2 Materials and methods ...... 60

2.2.1 Metal film patterned by interference lithography ...... 60

2.2.2 Etching and characterization ...... 62

2.3 Establishing the Schottky barrier heights ...... 63

2.4 MAAE on lightly doped p-type silicon substrate ...... 68

2.5 MAAE on lightly doped n-type silicon substrate ...... 75

2.6 MAAE on heavily doped n-type and p-type silicon substrate ...... 84

2.7 Pt-catalyzed MAAE ...... 89

2.8 Conclusions...... 91

Silicon Nanowire Based MOS Capacitors ...... 96

3.1 Introduction ...... 96

3.2 Silicon nanowires generated by MACE ...... 97

3.3 Conductivity improvement of the silicon nanowires ...... 100

3.3.1 Silicidation ...... 100

3.3.2 Post-MACE doping ...... 107

3.4 Single crystal silicon nanowire based capacitors ...... 112

3.4.1 Fabrication and capacitance measurements on four types of devices ...... 112

3.4.2 Scaling of device performance with nanowire array geometries ...... 116

3.4.3 The effect of nanowire diameter on the capacitor performance ...... 118

3.5 Polycrystalline silicon nanowire based capacitors ...... 122

3.6 Conclusion ...... 125

Silicon Nanowire Based Supercapacitors ...... 128

4.1 Introduction ...... 128

4.2 Materials and experiment ...... 132

4.2.1 Electrode fabrication ...... 132

4.2.2 Solid state supercapacitor fabrication ...... 132

4.2.3 Electrochemical testing ...... 133

4.3 ALD of RuO2 and characterization ...... 134

4.4 Electrochemical test on electrodes in aqueous solution...... 140

4.4.1 Cyclic Voltammetry of 150 ALD cycles electrodes ...... 140

4.4.2 Cyclic Voltammetry of 400 ALD cycles batch electrodes ...... 144

4.4.3 Scalability of specific capacitance based on cyclic voltammetry ...... 147

4.4.4 Charge-discharge test on 400 ALD cycle electrodes ...... 151

4.5 Solid state supercapacitor ...... 153

4.5.1 Cyclic voltammetry of 400 ALD cycles devices ...... 153

4.5.2 Charge-discharge test of 400 ALD cycle devices ...... 156

4.6 Comparison with solid state supercapacitors made using other methods ...... 159

4.7 Conclusions...... 162

Summary and Future Work ...... 164

5.1 Summary ...... 164

5.2 Future work ...... 166

Reference ...... 170

Appendix A Effects of Catalyst Type and Structure in Metal-Assisted Chemical Etching

(MACE) ...... 178

A.1 Comparison between Ag, Au and Pt ...... 178

A.2 Sandwiched catalyst Au/Cu/Au ...... 182

Appendix B Dissolution Valence and Porosity of Silicon in MAAE ...... 186

B.1 Introduction ...... 186

B.2 Dissolution valence ...... 188

B.3 Porosity in silicon nanostructures ...... 191

List of Figures

Figure 1.1 Schematic of silicon wire growth through the Vapor-Liquid-Solid (VLS). (a) Initial

formation of a liquid alloy droplet from a solid Au particle on the substrate. b. Growing

wire with the liquid droplet at the tip [1]...... 26

Figure 1.2 SEM images of nanospheres-on-silicon samples after oxygen plasma treatment and the

silicon etch. Row A represents top views of nanospheres that went through oxygen plasma

etching for various time periods. Row B and row C show top and side views of samples

etched by deep reactive ion etching. The scale bar is 750nm [7]...... 27

Figure 1.3 Si nanowires produced using reactive ion etching: SEM view of (a) and (b) vertical

silicon nanowires with 40nm diameters and 1.5 µm heights, (c) nanowires with 50nm

diameters and etched to a depth of 3µm [8]...... 28

Figure 1.4 Schematics showing the MACE process with Au nanobeams [18]...... 32

Figure 1.5 Silicon energy band diagrams and redox potential of H2O2/H2O on the same scale [19].

...... 32

Figure 1.6 Schematic presentation of three different diffusion models [24]...... 34

Figure 1.7 Schematic of typical morphologies of metal catalysts and the corresponding silicon

structures after MACE [25]...... 35

Figure 1.8 SEM of (a) Silicon nanowires, (b) Silicon nanofins, and (c) Silicon nanowires with

oval cross sections [13]...... 36

Figure 1.9 Etch rates as a function of the molar ratio ρ. Open circles: Ag penetration rate before

porous silicon dissolution in NaOH. Filled squares: etch rate after porous silicon

dissolution in NaOH [16]...... 37

Figure 1.10 (a) Porous silicon nanowires showing the alternating high and low porosity segments

(as variations between high and low contrast along the wire length) caused by etching with

a high and low oxidant concentration, respectively. The scale bar of the close-up view on

the right is 100nm. (b)Diagram of the different morphologies obtained using MACE as a

function of substrate resistivity and concentration of H2O2, for a fixed HF concentration

[26]...... 38

Figure 1.11 SEM images of etching products from silicon substrates with different orientations

(100), (110), (111) and different Au catalyst morphologies: (a)-(c) e-beam deposited

isolated Au nanoparticles, (d)-(f) block-copolymer patterned Au mesh, (g)-(i) interference

lithography patterned Au mesh [15]...... 39

Figure 1.12 Nitrogen adsorption/desorption isotherms of silicon nanowires obtained from wafers

with different resistivities [36]...... 40

Figure 1.13 TEM image of the 18nm diameter Si/Ge nanowire. The inset is the selected area

electron diffraction showing its single crystallinity [37]...... 41

Figure 1.14 SEM images of (a) vertical GaAs nanopillars produced in an etchant of H2SO4 over-

saturated with KMnO4 at 40-45℃, (b) zigzag GaAs nanowires generated from an etchant

of 55.7mM KMnO4 in HF solution at room temperature [40]...... 42

Figure 1.15 The schematic of a MOS capacitor...... 43

Figure 1.16 Energy band diagrams and block charge diagrams for an n-type device under flat band,

accumulation, depletion, and inversion regimes [43]...... 44

Figure 1.17 Normalized capacitance versus gate voltage diagram for a MOS capacitor across three

different regimes measured under high frequency and low frequency alternating current

[44]...... 45

Figure 1.18 (a) A test chip of a DC-DC converter [45]. (b) Pie chart illustrating the percentage of

the capacitor area...... 46

Figure 1.19 (a) SEM image showing the periodic trench structures. (b) SEM image showing the

structure of the MOS capacitor [46]...... 47

Figure 1.20 Cross-sectional images of 32nm deep trench eDRAM cell [48]...... 48

Figure 1.21 SEM of (a) silicon nanowire arrays generated using MACE, (b) cross section of the

MOS capacitor [53]...... 49

Figure 1.22 Schematic of a supercapacitor electrode in the electrolyte...... 50

Figure 1.23 Schematic of the fabrication of a micro-supercapacitor integrated onto a silicon chip

[54]...... 51

Figure 1.24 (a) A photo of the ionogel electrolyte prepared by mixing the ionic liquid 1-butyl-3-

methylimidazolium bis(trifluoromethylsulfonyl)imide with fumed silica nanopowder. (b)

Schematic of the device. (c) Photo of the on-chip device [55]...... 52

Figure 1.25 SEM images of (a) the nanoporous alumina template, (b) ultra-dense silicon nanowire

arrays after growth in the alumina and subsequent removal of the alumina [60]...... 53

Figure 1.26 Plot of specific capacitance versus average wire length calculated from galvanostatic

charge-discharge at 1mA/cm2 in EMIM-TFSI electrolyte [62]...... 54

Figure 1.27 (a) Cross section schematic of the on-chip supercapacitor encapsulated in a solid

Nafion electrolyte, (b) SEM image of electrodes after ALD TiN and RuO2, (c) TEM image

of an individual electrode particle showing the multilayer structure...... 55

Figure 2.1 (a) Set-up for MAAE with contact made through the silicon (back side). (b) Set-up for

MAAE with contact made through the perforated Au film (top side)...... 60

Figure 2.2 (a) Basic configuration of Lloyd’s Mirror; (b) Two beams interfere to form a standing

wave [105]...... 61

Figure 2.3 (a) Schematic diagram showing the injection of electronic holes from an Au coating

into the silicon, and how the holes participate in the etching of silicon. Green arrows

indicate hole current. The color scheme used to represent the different materials here will

be employed throughout the rest of this report. (b) Energy band diagram for the Au/ N-Si

interface. EC, EF and EV refer to the conduction band edge, Fermi level and valence band

edge, respectively. (c) Energy band diagram for the N-Si/ HF interface. (d) Semi-log plot

showing fitted experimental trends (solid lines) and calculated trends (dashed lines) and (e)

linear-linear plot of the experimental data, for the current density (J) vs. the applied voltage

(Va)...... 64

Figure 2.4 Mott-Schottky plot of Au/n-Si. The measurements were conducted at 1 MHz using

Agilent 4980A...... 66

Figure 2.5 Current density-applied voltage, J-Va, plots for electrochemical etching of lightly doped

silicon substrates, etched using Au or Pt...... 67

Figure 2.6 Representative SEM images showing the morphology of the nanowires obtained for

electrochemical etching of p-type silicon substrates. The etch duration in each case was

10min. White solid arrow points to porous silicon, white dashed arrow points to solid

silicon and the white dashed line demarcates the porous/ solid silicon interface. The scale

bar represents 1µm. Note that the entire silicon layer underneath the nanowires shown in

(d) is porous...... 69

Figure 2.7 (a) Energy band diagram at the silicon surface (Y = 0), showing band bending in Si at

X = 0 (where the Au meets the HF). EF here refers to the equilibrium Fermi level. The red

arrow shows holes being repelled by the energy barrier,  (= 0.46eV). (b) Energy band

diagram at the etchant/p-Si interface before (solid lines) and after (dashed lines) the

application of a positive voltage, Va, through the perforated Au film. Holes are initially

repelled from the interface (red arrows) due to an energy barrier, Vbi, but after Va is applied,

they (green arrows) face no barrier...... 70

Figure 2.8 Energy band diagrams at the (a) etchant/p-Si interface and (b) Au/p-Si interface before

(solid lines) and after (dashed lines) the application of a voltage of Va (blue arrow). In this

case, Va < Vbi, the applied voltage at the etchant/p-Si interface is too low to overcome the

energy barrier. As a result, holes injected through the bulk silicon preferentially accumulate

at the Au/p-Si interface and cause etching, as illustrated in (c)...... 73

Figure 2.9 Energy band diagrams at the (a) etchant/p-Si interface and (b) Au/p-Si interface, before

(solid lines) and after (dashed lines) the application of a voltage of Va (blue arrow) through

the silicon substrate (Va = Vbi). Here, the applied voltage has overcome the energy barriers

at the Au/p-Si and etchant/p-Si interfaces, and holes injected through the bulk silicon can

reach both interfaces. As a result, silicon is etched under the Au and porous silicon is also

formed away from the Au, as illustrated in (c). Green arrows indicate the movement of the

holes...... 74

Figure 2.10 (a) J-Va plot for MAAE of n-Si in 4M HF with the anodic contact made through the

perforated Au and through the silicon. (b) – (e) SEM images showing the morphology of

the nanowires obtained for electrochemical etching of n-type silicon substrates. The

etching durations were (b) 10 min, (c) 10 min, (d) 10 min, and (e) 1 min. MAAE was the

only etching mechanism operating, as no porous silicon, an indication of regular anodic

etching, can be observed. The scale bar represents 1µm...... 76

Figure 2.11 (a) Energy band diagram showing that hole injection rate from Au to n-Si (green

arrow) is higher when a positive voltage (blue arrow) is applied to the perforated Au. (b)

Energy band diagram showing how holes transferred from the perforated Au in (a) are

trapped at the etchant/n-Si interface near the Au, causing silicon dissolution. (c) Schematic

diagram showing the injection of holes into n-Si through the Au and how these holes lead

to selective etching at the Au/n-Si interface...... 78

Figure 2.12 (a) Schematic diagram showing the electric field crowding effect. The concentration

of electric field lines is highest at the Au edges where breakdown occurs. (b) Energy band

diagram showing hole generation by impact ionization breakdown when a sufficiently large

positive voltage is applied to the n-Si substrate...... 79

Figure 2.13 (a) J-Va log-log plots for continuous-Au/n-Si and perforated-Au/n-Si interfaces. The

best fit line is also shown for each trend. (b) Plot of ln (1-J0/J) vs ln (|Va|). (c) Calculated

and experimental J-Va plots for electrochemical etching of n-Si when the anodic contact

was made through the silicon substrate. The HF concentration was varied from 1M to 4M

in the experiments...... 81

Figure 2.14 Current density–applied voltage, J-Va, plots for electrochemical etching of heavily

doped silicon substrates...... 84

Figure 2.15 Representative SEM images at different magnifications showing the morphologies of

the nanostructures obtained for (a) p+ and (b) n+ Si substrates with the anodic contact made

through the perforated Au. The current densities and durations of etching were (a)

12.5mA/cm2, 10min and (b) 8mA/cm2, 10min. White arrows indicate porous silicon

regions. The scale bars in (ai) and (bi) represent 1 µm, and those in (aii) and (bii) represent

500 nm. White arrows point to porous silicon, while the white dashed arrow points to solid

silicon. The dashed white line indicates the porous/ solid silicon interface. In (b) all of the

area shown under the wires is porous...... 85

Figure 2.16 Representative SEM images at different magnifications showing the morphologies of

the nanostructures obtained for (a) p+ and (b) n+ silicon substrates with the anodic contact

made through the silicon substrate. The current densities and durations of etching were (a)

23mA/cm2, 5min (bi) 23mA/cm2, 5min and (bii) 28mA/cm2, 5min. Yellow arrows point to

a thin layer of anti-reflection coating on the silicon nanowires that was not fully dissolved

by the solvent NMP. The scale bars in (ai) and (bi) represent 1 µm while those in (aii) and

(bii) represent 500 nm...... 86

Figure 2.17 (a) Energy band diagram illustrating the process of surface generation of electron-

hole pairs in n+-Si by means of a tunnelling transition stage. Because this surface generation

occurs at the etchant/n+-Si interface, the majority of the holes are concentrated at the

surface of the silicon in contact with the HF, where they are consumed in porous silicon

formation, as illustrated in (b). As a result, little or no nanowire formation is observed. 88

Figure 2.18 SEM images showing the morphology of nanowires obtained by electrochemical

etching of N-type silicon substrates (with Pt on the front surface) with the anodic contact

made through the silicon substrate. Etching parameters are given for each image...... 90

Figure 2.19 Current density-applied voltage, J-Va, plots for electrochemical etching of heavily

doped Si substrates with Pt...... 91

Figure 3.1 Transmission electron micrograph of a silicon nanowire MACE-etched from the

epitaxial wafer...... 98

Figure 3.2 (a) Silicon nanowire arrays from etching lightly doped p-type substrate for 7min; (b)

nanowire arrays from etching a heavily doped substrate with a lightly doped epitaxial layer

for 7min; (c) nanowires arrays from etching of intrinsic polycrystalline layers on lightly

doped substrates for 5min; (d) as-deposited polycrystalline silicon film...... 99

Figure 3.3 Schematic representation of silicide formation on silicon nanowires...... 100

Figure 3.4 (a) Silicon nanowires generated using MACE, (b) after e-beam evaporation of Ni, (c)

annealed at 450℃ for 2hours, and (d) after removal of excess Ni...... 102

Figure 3.5 (a) Silicon nanowires generated using MACE, (b) after sputtering deposition of Ni, (c)

annealed at 450℃ for 2hours, and (d) after removal of excess Ni...... 103

Figure 3.6 (a) XRD peaks from silicided wires, (b) TEM image, and (c) and (d) the selected area

electron diffraction of nanowires after silicidation and excess Ni removal...... 104

Figure 3.7 (a) Silicon nanowires generated using MACE, (b) after sputter deposition of Ni after

back sputtering, and (c) and (d) annealed at 450℃ for 2hours...... 105

Figure 3.8 (a) Silicon nanowires coated with ALD Pt, (b) nanowires after annealing, (c) cross

sectional TEM images of silicide nanowires after annealing, (d) HRTEM mage near the

edge of a nanowire and (e) HRTEM image close to the center of a nanowire...... 106

Figure 3.9 Schematic representation of post-MACE doping...... 107

Figure 3.10 SEM images of (a) as generated n-type silicon nanowires, (b) nanowires after doping

and before oxide removal, (c) silicon nanowires after the deglaze process, (d) TEM image

of a doped nanowire after the deglaze, (e) phosphorous mapping on the nanowire in (d), (f)

elemental mapping of Si, P, O across the nanowire. The inset in (f) shows the mapping

path on the nanowire...... 109

Figure 3.11 SEM images of (a) as generated p-type silicon nanowires, nanowires (b) after doping

and (c) after the deglaze process...... 110

Figure 3.12 Boron concentration vs. distance into Si...... 111

Figure 3.13 Process flow for silicon nanowire based capacitor fabrication...... 113

Figure 3.14 CV curves of four types of 100 µm *100 µm devices: (a) (double sweep) at various

AC frequencies for a Type I capacitor; (b) (single sweep) at various AC frequencies for a

Type II capacitor; (c) at various AC frequencies for a Type III capacitor; (d) at various AC

frequencies for a Type IV capacitor...... 115

Figure 3.15 Dependence of capacitance density on (a) the period of the nanowire array; (b) the

nanowire length...... 118

Figure 3.16 Four stages that a device goes through if the nanowires can be fully depleted...... 119

Figure 3.17 Mott-Schottky plots for 100um*100um Type I and II devices measured at 1 kHz.

...... 121

Figure 3.18 CV curves at various AC frequencies for (a) a 100µm*100 µm polycrystalline planar

capacitor; (b) a 100 µm *100 µm polycrystalline 550nm nanowire based capacitor. (c) a

100 µm *100 µm polycrystalline 660nm nanowire based capacitor. (d) Capacitance

densities measured at 1kHz of these three types of devices versus the wire length...... 124

Figure 4.1 Specific power versus specific energy for various energy storage devices [130]. ... 128

Figure 4.2 Schematic of a symmetrical solid state supercapacitor...... 131

Figure 4.3 Electrochemical cell set up for three electrode test in aqueous electrolyte...... 134

Figure 4.4 SEM images of silicon nanowire arrays before ALD that are (a) 1.8μm tall and (b)

6.4μm tall...... 135

Figure 4.5 TEM images of (a) a SiNW1-150cyc sample and (b) a SiNW2-400cyc sample. Higher

magnification TEM images of the (c) top, (d) middle, and (e) bottom of a SiNW2-400cyc

nanowire. (f) A HRTEM image of a nanoparticle on a SiNW2-400cyc nanowire...... 136

Figure 4.6 EDX result for the 6.4µm nanowires after 400 ALD cycles. (a) TEM image of a

collection of nanowires, and (c), (d), and (e) elemental mapping of silicon, oxygen and

ruthenium, respectively. (b) Summary of the quantitative results on the percentage of these

elements...... 137

Figure 4.7 XRD of various samples with and without the ALD process...... 138

Figure 4.8 XPS spectra and deconvolution analysis (Ru 3d) showing the presence of ruthenium

oxide...... 139

Figure 4.9 Cyclic Voltammetry curves for heavily doped n-type samples coated using 150 ALD

cycles: (a) planar Si w/o RuOx; (b) planar Si-150cyc RuOx; (c) SiNW1-150cyc RuOx; (d)

SiNW2-150cyc RuOx...... 141

Figure 4.10 EIS of bare planar Si and various samples coated using 150 ALD cycles. The inset

focuses on the high frequency region...... 142

Figure 4.11 A schematic diagram of charge transfer in silicon nanowire electrodes coated with

RuOx using 150 ALD cycles. The orange particles are the RuOx...... 143

Figure 4.12 Cyclic Voltammetry curves for a bare heavily doped n-type silicon nanowire sample.

...... 144

Figure 4.13 Cyclic Voltammetry curves for various types of heavily doped n-type samples: (a)

planar Si-400cyc RuOx; (b) SiNW1-400cyc RuOx; (c) SiNW2-400cyc RuOx...... 145

Figure 4.14 EIS of bare planar Si and various samples coated with RuOx using 400 ALD cycles.

The inset focuses on the high frequency region...... 146

Figure 4.15 A schematic diagram of charge transfer in silicon nanowire based electrodes coated

with RuOx using 400 ALD cycles. The orange particles are the RuOx...... 147

Figure 4.16 Specific capacitance versus scan rate for various types of heavily doped n-type

samples...... 148

Figure 4.17 Charge-discharge curves at various current densities for various types of heavily

doped n-type samples: (a) planar Si without RuOx; (b) planar Si-400cyc RuOx; (c) SiNW1-

400cyc RuOx; (d) SiNW2-400cyc RuOx. The legends show the current densities with units

of mA/cm2...... 152

Figure 4.18 Specific capacitance at various charge-discharge current densities for various types

of heavily doped n-type samples: (a) planar Si without RuOx; (b) planar Si-400cyc RuOx;

Figure 4.19 Cyclic voltammetry of symmetrical solid state devices made with various electrodes,

(a) planar Si w/o RuOx, (b) planar Si-400cyc RuOx; (c) SiNW1-400cyc RuOx; (d) SiNW2-

400cyc RuOx...... 154

Figure 4.20 Specific capacitance of symmetrical solid state devices made with various electrodes,

including planar Si w/o RuOx, planar Si-400cyc RuOx, SiNW1-400cyc RuOx and SiNW2-

400cyc RuOx at various scan rates...... 155

Figure 4.21 Galvanostatic charge and discharge curves for symmetrical devices with various

electrodes over a range of discharge rates, (a) planar Si w/o RuOx, (b) planar Si-400cyc

RuOx; (c) SiNW1-400cyc RuOx; (d) SiNW2-400cyc RuOx. The units of the legends are

mA/cm2...... 156

Figure 4.22 Specific capacitance calculated from charge and discharge curves for symmetrical

devices with various electrodes over a range of discharge rates, including planar Si w/o

RuOx, planar Si-400cyc RuOx, SiNW1-400cyc RuOx, and SiNW2-400cyc RuOx...... 157

Figure 4.23 The specific capacitance versus charge-discharge cycle number for the solid state

supercapacitor device based on SiNW2-400cyc RuOx electrodes at a discharge current

density of 0.4mA/cm2...... 158

Figure 4.24 A comparison chart of solid state capacitors including our nanowire based MOS

capacitors; state-of-the art micro trench capacitors as reported in Ref. 1 [47], Ref. 2

[51],and Ref. 3 [52]; carbon-based solid state on-chip supercapacitors from reference 4

[135], 5 [55], and 6 [131], RuO2 based solid state on-chip supercapacitor from reference 7

[79], reference 8 [142], reference 9 [75] and our solid state on-chip supercapacitors based

on Si-RuOx composite electrodes...... 160

Figure 4.25 (a) A comparison chart of specific capacitance normalized by the thickness of RuOx

deposited in Si CMOS compatible thin film deposition techniques for a variety of solid

state on-chip supercapacitors including this work, ALD RuOx [79] and sputter deposited

RuOx [142]. (b) Areal Ragone plot of four types of solid state devices discussed in this

chapter...... 162

Figure 5.1 A schematic of a nanowire solid state supercapacitor on a single chip...... 168

List of Tables

Table 2.1 Schottky barrier heights and breakdown voltage VBR (n-Si, silicon contact) determined

from experimental J-Va trends obtained for Au and Pt. 68

Table 2.2 Overview of the nanostructure morphologies observed for each type of wafer and

contact location. 92

Table 3.1 Descriptions of the four MOS single-crystalline capacitors. 113

Table 3.2 Critical nanowire diameters for different doping concentrations. 120

Table 4.1 Scalability of specific capacitance with the nanowire array geometry. 150

Table 4.2 Effects of ALD cycle number on electrode performance in cyclic voltammetry. 151

Introduction

1.1 Motivation and background

Capacitors are indispensable elements for power management circuitry, energy autonomous systems (EASs) and integrated circuits (ICs) in general. They can serve multiple purposes in these applications including temporary charge storage, power regulation, and signal noise reduction. Making capacitors directly on-chip reduces the need for packaging of multiple chips as well as provides local energy delivery and power regulation. The objective of this thesis is to develop high performance on-chip capacitors. Toward this goal, we aim to develop and use metal assisted wet chemical etching techniques to generate silicon nanowires for fabrication of high performance electrostatic and super capacitors.

The thesis consists of five chapters. In this chapter, we present a review of various techniques used to generate silicon nanowire arrays, as well as metal-oxide-semiconductor (MOS) capacitors and supercapacitors. We also discuss characteristics of metal-assisted chemical etching

(MACE), which is the primary technique used for nanostructuring of silicon in the research described in this thesis. In Chapter 2, we report on a mechanistic study of wet etching of silicon plus development of a new related technique for nanostructuring of silicon called metal-assisted anodic etching (MAAE). Different types of wafers and experimental setups were investigated in the MAAE space and electronic energy band diagrams were constructed for each condition to understand carrier generation and transport mechanisms. In Chapter 3, we describe the process developed for making silicon nanowire based MOS capacitors from both single crystal and polycrystalline substrates. The scalability of device performance with respect to the geometry of silicon nanowire arrays is also discussed. In Chapter 4, we report on the process flow used to

24 fabricate micro-supercapacitors using silicon nanowires coated with RuO2. Atomic layer deposition (ALD) was the technique used for deposition of RuO2 on the silicon nanowires generated using MAAE. In addition, full solid-state supercapacitors with solid electrolytes were fabricated using a CMOS compatible process. The superior performances of these devices are demonstrated and characterized in detail. Finally, Chapter 5 provides a summary of the key results and conclusions as well as suggestions for future work.

1.2 Metal-assisted chemical etching (MACE)

1.2.1 Comparison with other fabrication techniques for silicon nanowires

Various techniques have been investigated for generation of silicon nanowires. We present here a review of three prominent approaches including vapor-liquid-solid (VLS) growth, reactive ion etching (RIE), and MACE. The comparison between these three techniques shows that MACE is capable of overcoming most limitations of the other two methods.

(a) Vapor-liquid-solid (VLS) growth

The vapor-liquid-solid (VLS) method for wire growth was first described by Wagner and

Ellis [1]. Fig. 1.1 shows a schematic illustration of the VLS growth method for silicon nanowires.

During the growth, silicon gas precursors, including SiH4, SiHCl3 or other high order silanes are collected at the metal catalyst, which helps to lower the dissociation energy of the gas molecule.

The most commonly used metal catalyst is gold. According to the phase diagram, the Au-Si alloy becomes liquid above the eutectic point of 363℃ when enough silicon is present. Under a constant precursor gas flow rate, more and more silicon atoms are collected into the Au-Si liquid alloy.

When the metal alloy becomes supersaturated, Si will precipitate at the interface between the

25 particle and the substrate, leading to the growth of solid silicon wires. Since the first report of the

VLS method decades ago, great efforts have been made to refine this process to better control the properties of silicon nanowires [2-5]. The advantage of the VLS method is the versatility of the substrate material. However, it is limited by poor control of nanowire orientations. The growth direction for VLS growth, and hence the axis of the wires, is generally along either <111> or <110> direction [6]. In addition, metal contamination in silicon nanowires at high growth temperatures also raises concerns about CMOS compatibility of this process.

Figure 1.1 Schematic of silicon wire growth through the Vapor-Liquid-Solid (VLS). (a) Initial formation of a liquid alloy droplet from a solid Au particle on the substrate. b. Growing wire with the liquid droplet at the tip [1].

(b) Reactive ion etching (RIE)

As an alternative to the VLS method, nanowires can be fabricated through dry etching, which involves two distinct steps in the form of pattern generation and pattern transfer. Fig. 1.2

26 shows an example using nanospheres as etch masks to generate vertically standing silicon nanowires using deep reactive ion etching [7]. These researchers used a sequence of three steps to tune the structure of the silicon nanowires. First, monodisperse polystyrene nanospheres were spin- coated on a clean silicon wafer to generate an ordered layer of nanospheres. Then reactive ion etching with an oxygen plasma was used to tailor the size of the nanospheres. Finally, the nanospheres acted as hard masks for the deep reactive ion etching of silicon to generate nanowire arrays. In addition to nanospheres, other patterning techniques such as photolithography can be used to generate the hard mask for dry etch. This method also has limitations. For example, nanowires generated through anisotropic dry etching generally have very rough surfaces, as can be seen in Fig. 1.2. The periodic gratings on the nanowire sidewalls will destroy the nanowire when the latter’s diameter shrinks to a level comparable to surface roughness.

Figure 1.2 SEM images of nanospheres-on-silicon samples after oxygen plasma treatment and the silicon etch. Row A represents top views of nanospheres that went through oxygen plasma etching for various time periods. Row B and row C show top and side views of samples etched by deep reactive ion etching. The scale bar is 750nm [7].

Chou’s group demonstrated fabrication of silicon nanowires with diameters as small as

40nm by optimizing the etch cycle time and gas flows [8], as shown in Fig. 1.3a and b. However, a surface roughness of 10nm was observed, which was a quarter of the nanowire diameter. They also demonstrated nanowire arrays with wire diameters of 50nm and etching depth of 3µm, achieving aspect ratios around 60:1 (Fig. 1.3c). In those high aspect ratio structures, the uniformity became an issue in addition to the surface roughness. Etching stopped halfway in some regimes, leading to a piece of silicon remaining between the nanowires. Therefore, dry etching is still limited in generating high aspect ratio nanowires with very small diameters and smooth surfaces.

Moreover, it is a time consuming and expensive process, as generally only one wafer at a time can be etched, and the etching tool is complex.

Figure 1.3 Si nanowires produced using reactive ion etching: SEM view of (a) and (b) vertical silicon nanowires with 40nm diameters and 1.5 µm heights, (c) nanowires with 50nm diameters and etched to a depth of 3µm [8].

Another approach that has recently attracted more attention is MACE, which is a wet chemical etching approach. This is the main approach we used to generate silicon nanowires in this thesis research, therefore we present a detailed review of MACE in the following sections.

In this process, a noble metal is used to catalyze etching of silicon only at the metal-silicon interface in an etchant solution composed of HF and an oxidant. From a historical point of view,

MACE was first discovered by Dimova-Malinovska et al., when they deposited a layer of Al on silicon [9] and then placed the samples into a typical stain etching solution for silicon composed of HF, HNO3 and H2O. In the absence of Al, there was a time delay of 30-800s between the insertion of the sample in the etchant and the onset of etching [10, 11]. However, with Al the etching happened almost immediately. Li and Bohn then furthered these studies by exploring the use of noble metals in similar experiments [12]. They deposited Au, Pt and Au/Pd nanoparticles on silicon substrates and immersed the samples in an etchant composed of HF and H2O2. It was observed that the metal nanoparticles could successfully catalyze the etching of silicon.

MACE is unique and promising due to the following advantages:

 MACE is a room temperature process that is CMOS compatible, which means it can be readily

incorporated into standard chip manufacturing processes. Unlike the VLS technique, which

requires high growth temperature, MACE occurs at room temperature in an etchant with

chemicals commonly used in the semiconductor industry. Though MACE also requires the

presence of noble metals, the low processing temperature will reduce the likelihood of any

serious metal contamination. Also, metals that react with silicon, rather than diffusing into

silicon to create recombination centers can be used (e.g. Pt).

 MACE can be combined with thin film patterning techniques to generate silicon nanowire

arrays. In addition, ordered and aligned silicon nanowires can be achieved with this method.

This is in contrast with the VLS technique, for which the wires are generally not well aligned,

and are never aligned with their axes normal to the surface of a (100) Si wafer. MACE is a

process that can provide a good control over the feature size, length, orientation, cross sectional 29

shape [13], and doping of the nanowire arrays. Silicon nanowires with diameters as small as

20nm and aspect ratios as high as 220 were successfully achieved using MACE [14]. The

length can be simply determined by controlling the etch time. The orientation of the nanowires

can be altered by choosing the appropriate wafer or adjusting other experimental conditions

[15]. The effects of these factors will be discussed in more detail in section 1.2.3.

 MACE is an economical method as it allows for mass production of silicon nanostructures on

multiple wafers at the same time through parallel processing. For dry etching, which is the

most commonly used technique in today’s semiconductor industry, wafers can only be

processed one at a time, which makes it time consuming and expensive. The capitol cost of dry

etching equipment is also intrinsically high, as vacuums are required, and gas chemistries and

plasma conditions must be very well controlled. In contrast, a wet chemical etching can be

carried out in baths in ambient conditions.

1.2.2 Mechanism

A variety of oxidants can be used in MACE, such as AgNO3, H2O2, Na2S2O8, KMnO4, and

O2. However, because the mechanism and kinetics for each oxidant can be quite different from the others, for the sake of simplicity, we will only focus on the use of H2O2 with HF, as this is the etch chemistry used in all the research to be discussed. It is widely accepted that the reactions occur preferentially near the noble metal with the following cathode and anode reactions [16, 17]:

n Cathode: H O nH  nH O  nh , (1.1) 2 2 2 2

4  n Anode: Si6 HF  nh  H2 SiF 6  nH  H 2 , (1.2) 2

nn4  Overall reaction: Si6 HF  H2 O 2  H 2 SiF 6  nH 2 O  H 2  . (1.3) 22

The metal acts as a catalyst in the process and thus it does not appear in the reaction equations above. During MACE, the noble metals such as Au, Ag or Pt catalyze the reduction of

H2O2, resulting in the generation of electronic holes. The electronic holes are then transferred to the silicon at the metal-silicon interface, causing the oxidation and dissolution of silicon atoms underneath the metal. Depending on the etchant solution composition and the amount of hydrogen produced, n in the equations above can vary from 2 to 4 [16].

For etching to continue, MACE requires a force to keep the metal and silicon in proximity.

In 2013, Lai et al. designed a novel experiment to study this mechanical force [18], as shown in

Fig. 1.4. They patterned nanoscale Au beams that were mechanically constrained at two ends.

After placing the sample into the etchant, the non-constrained area started etching and the MACE process stopped when the elastic bending force of the Au beam matched that of the adhesion strength between the metal and the silicon. The shape of the beam was then characterized using atomic-force microscopy (AFM) and used to compute the adhesion strength between the metal beam and the silicon. It was concluded that van der Waals forces were the dominant mechanical forces that held the catalyst and silicon together during MACE.

Figure 1.4 Schematics showing the MACE process with Au nanobeams [18].

One of the key steps in MACE is the electronic hole generation and transport. Fig. 1.5 shows an energy band diagram of silicon and the redox potential for H2O2/H2O constructed for consideration of MACE [19]. As can be seen from the energy band diagram, the holes can be readily injected from the oxidant to the silicon. It is widely accepted that the metal accelerates this process by extracting holes from the oxidant and injecting them into the silicon.

Figure 1.5 Silicon energy band diagrams and redox potential of H2O2/H2O on the same scale [19].

There have also been reports that suggest different charge transport pathways. Tsang et al. developed the one-step etching of n-type silicon in HF and AgNO3 etchant without using an elemental metal catalyst. They built a quasi-quantitative energy band diagram for silicon- electrolyte interfaces and concluded that it is more likely that electrons are the dominant carriers in the etching of n-type silicon with various doping levels [20]. Kolasinski analyzed the energy band diagram at the metal-silicon interfaces for different metals on silicon substrates with both doping types. He then proposed that the electronic holes did not diffuse from the metal to silicon but instead, the charges were concentrated on the metal catalyst and led to an electric field that induced the etching of silicon [21].

Given that controversy remains over whether electrons or holes are the dominant charge carriers in MACE, it is clear that further basic studies are needed. For this reason, we have carried out deeper investigations into the energy band diagrams for silicon wet etching systems that will be discussed in more detail in Chapter 2.

Finally, the diffusion process of the reactants and reaction products has also been studied.

Initially, most researchers accepted that the reagents and products only diffuse along the metal- silicon interface [22, 23]. However, Geyer et al carried out a series of experiments to confirm the diffusion pathways in MACE [24]. They tested three different models, as shown in Fig. 1.6, with a perforated metal film. For a thin metal film that probably had small cracks, model I suggested that the reagents and products diffused through the pores in the film, which was found to be true.

However, this cannot be the only pathway for diffusion as a repeated test with a thick film also yielded etching. This observation supports the hypothesis of model II. In this model, the oxidation of silicon occurred at the metal-silicon interface to form a porous silicon layer. The etchant then diffused through the porous layer to facilitate the dissolution. Meanwhile, for metal strips that had 33 the same lateral size but different thicknesses, the etching rates were found to be roughly the same.

This phenomenon was inconsistent with model III. If silicon atoms diffused through the metal film to the metal-etchant interface as described in this model, the etching rate should decrease with increasing film thickness. In summary, model II was confirmed as the main diffusion pathway in

MACE, while model I can exist at the same time in very thin metal films.

Figure 1.6 Schematic presentation of three different diffusion models [24].

1.2.3 Factors influencing MACE

In addition to fundamental studies of MACE mechanisms, efforts have also been made to control the MACE process and engineer different types of nanostructures. Numerous experiments have been carried out to identify factors governing the outcomes from MACE, in order to generate desired structures with better process control.

(a) Metal morphology and type

Metal functions as a catalyst in MACE; therefore, only the silicon underneath the metal will be etched. Holes in a metal film will lead to wires where holes are placed, while patches of metal will form holes in the silicon with the shapes of the patches. Fig. 1.7 shows a schematic representation of different silicon nanostructures resulting from different metal morphologies [25].

Figure 1.7 Schematic of typical morphologies of metal catalysts and the corresponding silicon structures after MACE [25].

Choi et al. showed that various silicon nanostructures can be synthesized by a combination of interference lithography and MACE [13]. The patterns in the metal film were easily modified by changing the interference lithography conditions, which were then transferred to silicon. For example, silicon nanostructures with different cross-sectional shapes were generated including silicon nanowires, silicon nanofins, and silicon nanowires with oval cross sections, as shown in

Fig. 1.8. They also demonstrated that the size and spacing of the nanowires in the arrays could be controlled independently.

Figure 1.8 SEM of (a) Silicon nanowires, (b) Silicon nanofins, and (c) Silicon nanowires with oval cross sections [13].

Chang et al. demonstrated that even for a fixed wafer orientation, modifications of the catalyst morphology can be used to change the orientation of the silicon nanowires generated from

MACE [15]. This will be discussed in further detail when reviewing the effects of substrate type on MACE. In addition to the morphology, different types of metals also behave differently in

MACE, which will be discussed in Appendix A.

(b) Etchant solution composition

Chartier et al. plotted the etching rate of MACE with respect to the etchant composition, as shown in Fig. 1.9 [16]. By investigating SEM images of samples etched in different solutions, they observed four different morphological regimes identified as polishing, craters, simultaneous formation of microporous/porous silicon, and porous silicon.

Figure 1.9 Etch rates as a function of the molar ratio ρ. Open circles: Ag penetration rate before porous silicon dissolution in NaOH. Filled squares: etch rate after porous silicon dissolution in NaOH [16].

Chiappini et al. also carried out experiments with both Ag and Au nanoparticles [26]. By fixing the concentration of the HF, they found that the etching rates for both Ag and Au nanoparticles were comparable and showed a positive correlation with the H2O2 concentration.

They also discovered that in the regime where nanowires were formed, the etchant composition affected the morphology of the nanowires. Silicon nanowires tended to be more porous with increasing concentration of the oxidant, as shown in Fig. 1.10. Later research further confirmed this with patterned catalysts [17, 27]. Since then, many researchers have channeled their efforts into investigating and controlling the porosity levels in silicon nanowires generated using MACE

[27-30]. 37

Figure 1.10 (a) Porous silicon nanowires showing the alternating high and low porosity segments (as variations between high and low contrast along the wire length) caused by etching with a high and low oxidant concentration, respectively. The scale bar of the close-up view on the right is 100nm. (b)Diagram of the different morphologies obtained using MACE as a function of substrate resistivity and concentration of H2O2, for a fixed HF concentration [26].

In the early studies, experimental observations appeared to confirm the hypothesis that

MACE only results in vertical etching, regardless of the orientation of the substrate [22, 31].

However, etching in directions different from the substrate orientation was discovered later [32-

34]. In 2010, Chang et al. designed a systematic experiment to study the effect of the silicon substrate orientation on the crystallographic orientation of silicon nanowires [15] (Fig. 1.11). They found that for isolated Au nanoparticles (Fig. 1.11a-c) and Au mesh with small hole spacings (Fig.

1.11d-e), etching occurred in the crystallographically preferred <100> direction. However, when the Au mesh had a larger hole spacing (Fig. 1.11g-i), the etching was confined to the vertical direction no matter which substrate was used.

Figure 1.11 SEM images of etching products from silicon substrates with different orientations (100), (110), (111) and different Au catalyst morphologies: (a)-(c) e-beam deposited isolated Au nanoparticles, (d)-(f) block-copolymer patterned Au mesh, (g)-(i) interference lithography patterned Au mesh [15].

In addition to substrate orientations, doping levels were also widely studied, as shown previously in Fig. 1.10b. Backes et al. also studied MACE on p-type silicon and found that the porosity level increased with the doping, while the etching rate decreased with an increasing doping level [35]. Duan’s group also reported larger porosity in n-type silicon wafers with a higher doping concentration. According to the nitrogen adsorption/desorption isotherms shown in Fig.

1.12, the mean BET surface areas were 370, 240, 40, 30 m2g-1 for silicon nanowires etched on silicon substrates from high to low doping levels [36]. Therefore, the porosity in silicon nanowires will increase with increasing doping concentration, regardless of the dopant type (n-type or p-type).

Figure 1.12 Nitrogen adsorption/desorption isotherms of silicon nanowires obtained from wafers with different resistivities [36].

Some have also reported possible approaches to control the porosity of silicon nanowires.

For example, Balasundaram et al. succeeded in generating a non-porous highly doped silicon nanowire with an aspect ratio around 10:1 with an etchant of a high HF to H2O2 ratio (volumetric ratio of 30:1) [30]. A low temperature of 0ºC (ice bath) was necessary in their process to reduce the porosity, which was at the expense of a six to seven times lower etch rate compared to a room temperature process using the same etchant solution. While this is an interesting result, it is limited in practical use, and more research into the origin and control of porosity is needed.

1.2.4 Applications to semiconductors other than silicon

For many years, MACE was only found to work with silicon. However, researchers started to explore the possibility of extending this method to other semiconductors with proper modifications.

Geyer et al. successfully fabricated sub-20nm Si/Ge superlattice nanowires using Ag catalyzed MACE [37, 38]. Fig. 1.13 shows the representative TEM images of the Si/Ge nanostructures generated from MACE. As can be seen in Fig. 1.13, there is a sharp transition between Si and Si/Ge layers. In addition, the superlattice in the Si/Ge layer is also visible [37].

However, there has been no report so far on fabricating pure Ge nanowires with MACE.

Figure 1.13 TEM image of the 18nm diameter Si/Ge nanowire. The inset is the selected area electron diffraction showing its single crystallinity [37].

In addition to group IV semiconductors, III-V semiconductors are candidate materials for photovoltaic applications. Asoh et al. first developed a MACE process to form ordered InP microbump arrays in an etchant solution of H2SO4 and H2O2 under UV illumination [39]. In 2011,

Li’s group developed a MACE process to fabricate periodic GaAs nanostructures on n-type (100)

GaAs wafers without the use of UV irradiation [40]. This was possible through the use of KMnO4

41 oxidant in acidic solutions (H2SO4 or HF). Though high aspect ratio nanostructures were successfully achieved, it was found that the nanostructure geometries were highly sensitive to the etchant composition. Fig. 1.14 shows two different GaAs morphologies of nanostructures generated under different conditions.

Figure 1.14 SEM images of (a) vertical GaAs nanopillars produced in an etchant of H2SO4 over-saturated with KMnO4 at 40-45℃, (b) zigzag GaAs nanowires generated from an etchant of 55.7mM KMnO4 in HF solution at room temperature [40].

1.3 Literature review on two types of on-chip capacitors

1.3.1 Silicon based metal-oxide-semiconductor (MOS) capacitors

Electrostatic MOS capacitors are key components in power management circuitry. They are used for regulating the power distribution and reducing signal noise. A typical MOS capacitor is an ideal CMOS compatible on-chip capacitor, as shown in Fig. 1.15. Silicon serves as one electrode and the gate metal serves as the other electrode, and they are separated by a dielectric material. Another metal layer forms an ohmic contact on the back of silicon substrate. The dielectric is usually an oxide film, such as silicon dioxide and hafnium oxide that can be as thin as

42 a few nanometers [41, 42]. If the silicon wafer is p-type, the device will be referred as n-type MOS capacitor as the inversion layer is mainly n-type.

Figure 1.15 The schematic of a MOS capacitor.

For an MOS capacitor, an external bias applied to the metal gate will cause energy band bending at the silicon and oxide interface. To better understand the device physics, different gate voltages are studied. Different band bending states corresponding to the applied voltage will lead to three operational regimes: accumulation, depletion and inversion. Fig. 1.16 shows the energy band diagrams and block charge diagrams for an n-type device under flat band, accumulation, depletion, and inversion conditions [43]. The flat band state represents the condition when there is no energy band bending on the semiconductor side. Under this condition, there is no charge accumulation in either the semiconductor or the metal. The gate voltage applied to the device for flat band state is called flat band voltage, VFB. For the device shown in Fig. 1.15, when the gate voltage is smaller than VFB, the majority carriers of the semiconductor, in this case the electronic holes, will accumulate at the semiconductor surface. When the gate voltage increases above VFB, the holes are depleted at the interface. Therefore, a negative charge appears due to the acceptor ions remaining in the semiconductor lattice, and the device enters the depletion regime. When the gate voltage further increases beyond the value at which the semiconductor reaches its maximum

43 depletion width, inversion occurs. In the inversion regime, the minority carries of the semiconductor body, which are electrons in this device, will aggregate at the silicon and metal interface.

Figure 1.16 Energy band diagrams and block charge diagrams for an n-type device under flat band, accumulation, depletion, and inversion regimes [43].

Because the charge state is different under different conditions, the capacitance is also different and is a function of the applied external bias. The MOS capacitor performance is typically characterized using the capacitance-voltage method, in which the device is tested by sweeping a

DC voltage superposed with an alternating current across a potential window. Fig. 1.17 shows a representative capacitance-voltage curve for a p-type MOS capacitor [44]. It is observed that the capacitance does not only depend on the gate voltage, but also depends on the frequency of the alternating current. In the accumulation regime, the device works as a simple parallel plate capacitor and shows the highest capacitance. In the depletion regime, the capacitance is the overall value calculated from the oxide capacitance and the semiconductor capacitance in series. The inversion capacitance, however, depends on the measurement frequency as shown below. For a

44 low frequency, there is enough time for the holes to be generated and swept near the interface, leading to the same capacitance as in accumulation regime. At a high frequency, though, the carriers are unable to keep up. Therefore, the capacitance remains at its minimum value corresponding to the maximum depletion state of the device.

Figure 1.17 Normalized capacitance versus gate voltage diagram for a MOS capacitor across three different regimes measured under high frequency and low frequency alternating current [44].

The maximum capacitance can be calculated from Eq. (1.4). In this equation, εox is the dielectric constant of the oxide, εo is the vacuum permittivity, tox is the oxide thickness and A is the total surface area of the electrode.

ox 0 CAtotal  . (1.4) tox

Even though enormous efforts have been made to optimize the dielectric oxide for better performance, these capacitors still occupy a lot of the chip area even for the high capacitance

45 achieved under the accumulation condition. For example, the capacitors occupy almost 80% of the total die area of a switched capacitor DC-DC converter test chip, as shown in Fig. 1.18 [45].

Therefore, the capacitance density has to improve to further shrink the chip size. Here, the capacitance density means the capacitance per chip area, which is proportional to the ratio of effective electrode area to the chip area, as shown in Eq. (1.5). A’ represents the chip area in the equation.

 A C ox 0 . (1.5) tAox '

Figure 1.18 (a) A test chip of a DC-DC converter [45]. (b) Pie chart illustrating the percentage of the capacitor area.

An effective way to increase the capacitance density is introducing 3D electrodes to increase the A/A’ ratio in Eq. (1.5). There has been some impressive work done in this field, mainly by using silicon nanostructures or microstructures as the semiconductor electrode of MOS capacitor. Lehmann et al. first employed silicon trenches generated from moderately doped n-type silicon created using the anodization method [46]. The trenches had a pitch of 3.5μm, diameter of

2μm and depth of 165 μm, leading to an increase of the surface area by 85, as shown in Fig. 1.19a.

They then doped the silicon trenches to increase the conductivity and deposited dielectric and the top gate of poly-silicon, as shown in Fig. 1.19b. The capacitor showed a specific capacitance up to 4μF V/mm3.

Figure 1.19 (a) SEM image showing the periodic trench structures. (b) SEM image showing the structure of the MOS capacitor [46].

Since then, silicon trench structures have been widely exploited as the electrode to make high performance MOS capacitors in both industry and academia. IBM developed trench capacitors with a capacitance density of 120nF/mm2 that was implemented in their 90nm & 65nm technology nodes [47], in which silicon trenches with aspect ratios around 35:1 and SiON dielectric were used. In their 32nm technology nodes, deep trenches with similar aspect ratios were used, while a capacitance enhancement of 20% at the same node leakage was achieved by using a high-k dielectric (HfO2) [48]. Fig. 1.20 shows cross-sectional images of 32nm deep trench eDRAM cell, where two deep trench capacitors are shown on the left image.

Figure 1.20 Cross-sectional images of 32nm deep trench eDRAM cell [48].

Roozeboom et al. have successfully fabricated high density and low loss MOS capacitors based on trenches etched using both wet and dry etching [49]. They demonstrated that the capacitance scaled with the increase of the surface area, regardless of the technique used to produce the structures. They further improved the capacitance density by optimizing the electrode structure and the dielectric material [50-52]. A capacitance density as high as 230nF/mm2 was reported for trench MOS capacitors and 440nF/mm2 was achieved with trench metal-insulator-metal (MIM) capacitors.

In addition to silicon trench structures, Chang et al. have reported the use of vertically standing silicon nanowire arrays as an alternative for MOS capacitors [53]. They achieved a capacitance density as high as 4.2μF/cm2, which was nearly a nine-fold increase over a planar device fabricated under the same conditions. Fig. 1.21 shows SEM images of the silicon nanowire arrays and the as-fabricated full MOS capacitor device.

Figure 1.21 SEM of (a) silicon nanowire arrays generated using MACE, (b) cross section of the MOS capacitor [53].

1.3.2 On-chip supercapacitors

As described in the previous section, an MOS capacitor’s performance can be significantly improved by using three dimensional structures. Therefore, utilizing Si nanowires based MOS capacitors can reduce the size of power management circuitry in EASs and other ICs. However, the maximum aspect ratio that can be realized experimentally still limits the device capacitance density, which makes them insufficient for energy storage purposes. Supercapacitors, on the other hand, generally have a much higher capacitance compared to electrostatic capacitors. In supercapacitors, the charge will be stored and separated between the electrode and the electrolyte interfaces, as shown in Fig. 1.22. This interface can be treated as a capacitor with a Helmholtz double-layer distance as small as a few angstroms, which is the cause of high capacitance.

Figure 1.22 Schematic of a supercapacitor electrode in the electrolyte.

There are two types of supercapacitors. One is called electrical double-layer supercapacitor

(EDLS) or electrostatic supercapacitors, and the other is called faradaic supercapacitor or pseudocapacitors. For EDLS, there is no electrochemical reaction during charge and discharge cycles. For faradaic supercapacitors, in addition to the physical charge accumulation at the electrode surface, specific ions (green absorbed specific cations in Fig. 1.22) can penetrate through the double layer and reach the electrode material. In this case, the electrochemical redox reactions between the electrode material and absorbed ions also contribute to the overall capacitance.

Traditional supercapacitors consist of two current collectors, two electrodes, a liquid electrolyte and a separator. Therefore, they are mostly made as an individual sealed device.

However, to be able to directly integrate supercapacitors with other micro-electrochemical systems and general ICs, they need to be fabricated on-chip, in micro-scale and encapsulated in a solid electrolyte. An increasing amount of recent research has been focused on those directions to develop on-chip micro-supercapacitors.

Carbon based materials are popular electrode materials to make electrical double-layer micro-supercapacitors due to their light weight, high surface to volume ratio and excellent electrochemical activity. In 2010, Gogotsi’s group developed a process to make micro- supercapacitors from monolithic carbide-derived carbon (CDC) films [54]. The generated carbon film was porous, leading to a high double layer capacitance from the high surface area. The cell showed a volumetric capacity as high as 180 F/cm3 in tetraethylammonium tetrafluoroborate

(TEABF4). They also proposed the use of CDC films in combination with standard thin film deposition and patterning techniques to make on-chip micro-supercapacitors, as shown in Fig. 1.23.

However, they did not demonstrate the full device experimentally. Moreover, a temperature between 500℃ to 1000℃ was required to convert the carbide to carbon films, which would limit the usefulness of this process in integration with CMOS technology.

Figure 1.23 Schematic of the fabrication of a micro-supercapacitor integrated onto a silicon chip [54].

In 2013, Kaner’s group was able to demonstrate a scalable fabrication of graphene based on-chip micro-supercapacitors [55]. They first coated Si/SiO2 substrates with a thin film graphene oxide. The photo-thermal effect of graphene oxide was then used to convert graphene oxide to graphene with the absorption of high-intensity photons. They used a patterning technique named

LightScribe to generate graphene patterns as electrodes for the supercapacitor. An ionogel electrolyte, as shown in Fig. 1.24a, was used to make the device with the schematic shown in Fig.

1.24b and the real picture in Fig. 1.24c. The device exhibited a high capacitance on the order of a few F/cm3.

Figure 1.24 (a) A photo of the ionogel electrolyte prepared by mixing the ionic liquid 1-butyl-3- methylimidazolium bis(trifluoromethylsulfonyl)imide with fumed silica nanopowder. (b) Schematic of the device. (c) Photo of the on-chip device [55].

Though carbon based materials have been extensively investigated as electrodes for supercapacitors, they also have some disadvantages. Requiring high temperature treatment or involving processes that are not CMOS compatible are the major issues. Therefore, alternative materials have also been investigated.

It was not until recently that silicon has also been studied as a potential electrode material for electric double layer supercapacitors. Thissandier et al. have carried out a series of experiments to test the electrochemical performance of silicon nanostructures in an ionic liquid electrolyte [56-

61]. They were able to grow silicon nanowires using a nanoporous alumina template and obtained more ordered structures compared to the growth without the template, as shown in Fig. 1.25. By using an ionic liquid electrolyte, they were able to achieve a specific capacitance as high as

34.6μF/cm2 [60]. However, there has been no report so far on using silicon directly as an electrode for on-chip solid state micro-supercapacitors.

Figure 1.25 SEM images of (a) the nanoporous alumina template, (b) ultra-dense silicon nanowire arrays after growth in the alumina and subsequent removal of the alumina [60].

As discussed previously, with silicon itself as the electrode, an ionic liquid electrolyte was required to achieve ideal capacitive behaviors. Even with this electrolyte and high aspect ratio silicon nanostructures, the electrodes only showed a low capacitance density on the order of tens of μF/cm2. Therefore, modification of silicon nanostructure surfaces has gained significant tractions in literature recently. For example, Alper et al. demonstrated encapsulating silicon nanowires with ultrathin graphitic carbon sheath, as electrochemical double layer capacitor electrodes [62]. They first synthesized porous silicon nanowires from heavily doped silicon substrates through MACE. Carbonization was achieved by exposing the samples to CH4 at 900ºC, which led to a carbon layer thickness between 1 and 3 nm. The electrode performance was tested 53 in an organic liquid electrolyte. They demonstrated that the capacitance density scaled with the lengths of the wires, and achieved a capacitance density as high as 325mF/cm2 (Fig. 1.26).

However, this approach is limited by the high temperature requirement for the carbonization step.

Figure 1.26 Plot of specific capacitance versus average wire length calculated from galvanostatic charge- discharge at 1mA/cm2 in EMIM-TFSI electrolyte [62].

In addition to the electric double layer supercapacitors, pseudocapacitive materials have also been investigated to modify the silicon surface. Among various transition metal oxides for pseudocapacitor applications, ruthenium oxide stands out due to its high gravimetric capacity that is nearly 1000Fg-1 [63], good conductivity of 37µΩ∙cm [64], and good cyclability. Hydrous ruthenium oxide was widely investigated for supercapacitor applications decades ago [65-67].

However, the high cost of the material has limited its applications for bulk supercapacitors. In recent years, ruthenium oxide retrieved the attention due to their promising applications in micro- supercapacitors, as only a small amount is needed. Ruthenium oxide synthesized by wet

54 approaches was generally combined with materials that have high surface area including graphene

[68, 69], carbon nanotubes [70, 71], carbon nanofibers [72], carbon nanowalls [73], porous gold

[74], virus templated surface [75] or 3D silicon microstructures [76], in order to achieve an areal specific capacitance as high as a few F/cm2. However, the solution synthesis of ruthenium oxide generally yielded a poor control over the film morphology. More importantly, it is not a desirable step for the existing micro device fabrication process.

In recent years, atomic layer deposition (ALD) of RuO2 has been developed [77, 78]. A full solid state on-chip micro-supercapacitor was demonstrated by Gnerlich et al. based on ALD RuO2

[79]. Fig. 1.27a showed a schematic of the on-chip supercapacitor device with a solid Nafion electrolyte. However, it is clear from Fig. 1.27b that the electrode pillars are not well aligned as shown in the schematic, due to the extremely irregular nature of the viruses. The electrodes were made by electroless Ni coated virus, followed by ALD coating of TiN and RuO2, as shown in Fig.

1.27c. The fabricated device achieved a specific capacitance of 0.6mF/cm2. Though a full functional on-chip solid state supercapacitor has been demonstrated, this device is limited for its relatively low specific capacitance and involvement of a virus template.

Figure 1.27 (a) Cross section schematic of the on-chip supercapacitor encapsulated in a solid Nafion electrolyte, (b) SEM image of electrodes after ALD TiN and RuO2, (c) TEM image of an individual electrode particle showing the multilayer structure.

In the chapters to follow, our research on two types of on-chip capacitors, based on the use of silicon nanowire arrays, will be discussed. One is an electrostatic MOS capacitor; the other is a solid state micro-supercapacitor based on ALD RuO2 coated silicon nanowires.

Metal-Assisted Anodic Etching (MAAE)

2.1 Introduction

Metal-assisted chemical etching (MACE) has been the focus of much recent research, due to its flexibility in producing features such as high aspect ratio nanowires [14, 80], nanopores [81], tilted nanowires [82], and spirals [83] in a simple and inexpensive wet etching process. Silicon nanostructures made using MACE have been incorporated into a wide range of devices, including devices for energy storage [84-86], sensing [87, 88], and advanced electronics [89, 90]. Two different silicon nanowire morphologies are generally observed when MACE is used, highly porous nanowires that are photoluminescent and non-porous nanowires. In general, highly doped silicon wafers tend to form nanowires that are more porous than those formed in low to moderately doped silicon substrates, regardless of the oxidant type and concentration used [26, 91, 92].

An alternative method of forming photoluminescent porous silicon for optoelectronic devices, without nanowire formation, is to anodically etch silicon in an electrochemical cell [93,

94]. Unlike MACE, anodic etching does not involve the use of an oxidant, but consists of an HF solution alone. Anodic etching also does not require a metal to act as a catalyst. In anodic etching, an electrical potential is applied to the silicon using an external power supply, which drives electronic holes to the etchant/silicon interface so that silicon dissolution occurs. Holes are majority carriers in p-type silicon, so they are readily available to cause etching under anodic bias.

However, holes are minority carriers in n-type silicon, and thus, do not substantially contribute to silicon dissolution under an anodic bias. Previous research has shown that porous silicon cannot be formed from n-type silicon, unless illumination or a high reverse bias are used to increase the hole concentration through electron-hole generation or breakdown [95].

A few studies have combined MACE and anodic etching to produce silicon nanowires. In these experiments, an external electrical bias is added to the traditional MACE process without eliminating the oxidant in etchant solutions. This external bias can provide an additional hole supply, leading to accelerated etching [96, 97], or can be used to reduce lateral etching away from the metal coated area in conventional MACE [98].

Nanowire and nanopore formation have also been shown to be possible by substituting the oxidant in MACE with an external bias [99-101]. However, these studies were relatively limited in scope and in some cases, the contribution of the external bias to the etching of the silicon was not clear due to the use of Ag and Cu nanoparticles [99, 100], which are known to dissolve in HF solution and etch silicon when they re-precipitate, even in the absence of H2O2 [102]. In addition, application of a bias to the metal in a conventional anodic etching configuration was not investigated in these studies.

Although MACE and anodic etching have both been widely used in research, the details of their etching mechanisms are not well understood [25, 103]. Indeed, researchers have acknowledged that a comprehensive study combining the electronic and chemical aspects of

MACE is required to fully understand the etching mechanism [25, 99].

For this reason, we have carried out experiments on Metal-Assisted Anodic Etching

(MAAE) of silicon, using the two experimental configurations shown in Fig. 2.1. Silicon substrates were coated with perforated Au films and subjected to anodic etching in a HF solution. Au is stable in HF and does not dissolve and re-deposit during the etching processes [18, 104]. Also, besides anodic contact to the silicon substrate (Fig. 2.1a), the use of a continuous, perforated film allows application of an anodic bias to the noble metal (Fig. 2.1b). This allows comparison and contrasting of the effects of hole generation at Au/Si interfaces and electrolyte/Si interfaces, and allows

59 separate investigation of the effects that electronic and chemical processes have on the nanostructures formed in MAAE. This, in turn, provides insights into the mechanisms of MACE and conventional anodic etching.

Figure 2.1 (a) Set-up for MAAE with contact made through the silicon (back side). (b) Set-up for MAAE with contact made through the perforated Au film (top side).

2.2 Materials and methods

2.2.1 Metal film patterned by interference lithography

In order to obtain an ordered array of silicon nanowire arrays, the metal has to be patterned as an orderly perforated film. Such structures can be generated with various patterning techniques including nanosphere lithography, block copolymer lithography, anodic aluminum oxide (AAO) 60 mask based lithography and interference lithography (IL). In this thesis, we will use interference lithography to pattern the film. IL is a quick and economical approach to generating a periodic pattern. It is also a maskless process and generally takes only a few minutes for each exposure. A

Lloyd’s mirror interferometer will be used in this work. A mirror is used to reflect part of the light from a broad beam to create interference [105], as shown in Fig. 2.2. The system has a 325nm He-

Cd laser source, and can create features with a period as small as 165nm. The pattern period on the photoresist is calculated with the following equation:

λ p = . (2.1) 2sinθ

In this equation, λ is the laser wavelength and θ is the half angle of the two interference beams.

Figure 2.2 (a) Basic configuration of Lloyd’s Mirror; (b) Two beams interfere to form a standing wave [105].

To minimize undesired interference caused by reflections at the photoresist/substrate interface and achieve sharp features, a tri-layer stack was used. The substrates were first coated with a trilayer consisting of 220nm BARLi anti-reflection coating (ARC) (AZ Electronic

Materials), 20nm-thick SiO2, and 200nm-thick PFI-88 photoresist layer (Sumitomo Chemical Co.).

The substrates were exposed twice at perpendicular angles using Lloyd’s mirror interference lithography to generate an ordered array of photoresist pillars. The patterns were then developed in CD 26 solution and transferred to the ARC layer by reactive ion etching. After an e-beam deposition of 20nm-thick Au films, heated N-methyl-2-pyrrolidone (NMP) was used to remove the ARC posts.

Four types of (100) silicon wafers as described were studied including p-type (boron-doped,

10-20 Ω·cm and 0.005-0.01 Ω·cm), lightly doped n-type (phosphorous-doped, 10-30 Ω·cm) and heavily doped n-type (arsenic-doped, ≤0.005 Ω·cm) were studied. The Au film was deposited and patterned with the process described above. The ohmic contacts for lightly doped p-type and n- type silicon substrates were made using a thick layer (>100 nm) of Au and Al, respectively.

2.2.2 Etching and characterization

The samples were cut into 1×1.5cm2 strips. A direct current (DC) power supply (Agilent

E3612A) was used to apply a bias during MAAE, and the I-V characteristics of the process were acquired. The etchant was composed of HF (49%, VWR) and de-ionized (DI) water. Unless indicated otherwise, the concentration of HF used was 4M and the total volume of the etchant was kept at 70mL. Experimental configuration in which the contact was made through the silicon is shown in Fig. 2.1a. A platinum mesh is used as a counter electrode. The sample was sealed between a Teflon cell and a copper plate, with the Au-coated side of the wafer exposed to the etchant solution. The exposed area of the sample was 0.7cm2. The copper plate was connected to the positive end of the power source, and the Pt counter electrode was connected to the negative end to complete the circuit.

The experimental configuration for contact through the perforated Au films is shown in

Fig. 2.1b. The silicon sample was suspended in the solution with an area immersed in the solution of approximately 0.7cm2. An Au wire was fixed in place using a clip and was used to contact the patterned Au film, so that the electric current could only go through the Au on the top surface of the silicon. After etching, the samples were removed from the etchant solution and rinsed with deionized water multiple times before being dried using a nitrogen gun.

2.3 Establishing the Schottky barrier heights

Based on the analysis of previous reports [16, 18, 25], MACE of silicon in HF takes place when electronic holes (h+) are injected into the silicon near the metal-silicon interface (Fig. 2.3a).

Because most of the injected holes lie near the Au/Si interface for metal assisted chemical etching, the fastest dissolution of silicon takes place under the metal. If a perforated Au film is used, the un-etched silicon protrudes through the holes in the film, leading to the formation of silicon nanowires.

In the process of metal assisted dissolution of silicon described above, it should be noted that charge transfer takes place through two interfaces, the Au/Si interface and the etchant/Si interface. Therefore, the details of the electronic band structures of these two interfaces are required to quantitatively understand the etching process. Figs. 2.3b and 2.3c show examples of the general energy band diagrams for these two interfaces. It can be seen that they are basically

Schottky junctions [106, 107]. Note that the axis for Y = 0 is arbitrarily fixed with respect to the

Au/Si and etchant/Si interfaces, while X = 0 is fixed with respect to the Au/HF interface. This convention will be used throughout the rest of the paper.

Figure 2.3 (a) Schematic diagram showing the injection of electronic holes from an Au coating into the silicon, and how the holes participate in the etching of silicon. Green arrows indicate hole current. The color scheme used to represent the different materials here will be employed throughout the rest of this report.

(b) Energy band diagram for the Au/ N-Si interface. EC, EF and EV refer to the conduction band edge, Fermi level and valence band edge, respectively. (c) Energy band diagram for the N-Si/ HF interface. (d) Semi- log plot showing fitted experimental trends (solid lines) and calculated trends (dashed lines) and (e) linear- linear plot of the experimental data, for the current density (J) vs. the applied voltage (Va).

In order to determine the Schottky barrier heights for each junction, we made use of the experimental J-Va (current density vs applied voltage) trends obtained for various experimental configurations and samples, shown in Fig. 2.3d and 2.3e. The theoretical trends for currents passing through Schottky junctions with barrier heights of 0.76eV and 0.82eV (dashed lines) are also plotted in Fig. 2.3d, and are given by,

B qV  a J A*2 T ekT e kT 1 , (2.2)  where A* refers to the Richardson’s constant (120 A/cm2K2), T is the temperature, k is Boltzmann’s constant, q is the elementary charge and Va refers to the applied voltage (negative for reverse bias and positive for forward bias). B refers to the Schottky barrier height and is represented by  and

 for the Au/Si and etchant/Si interfaces, respectively (Figs. 2.3b and 2.3c).

As can be seen in Fig. 2.3d, the J-Va curves for all of the samples initially follow Eq. (2.2).

However, as the values of J and Va rise, the experimental trends deviate increasingly from the calculated trend. This is because, at large J, the J-Va relationship becomes dominated by the resistance of the HF solution and the bulk Si instead of the interface [106]. This portion of the J-

Va trend is ohmic and thus, shows up as a curve in the semi-log graph shown in Fig. 2.3d.

Nevertheless, the experimental J-Va curves at small applied voltages conform to Eq. (2.2), and the experimental data can be fitted to evaluate the Schottky barrier height. From the data in Fig. 2.3d, we obtained a B value of 0.82eV for lightly doped n-type silicon with the Au anodic contact and

0.76eV for lightly doped p-type silicon, regardless of the anodic contact material (Au or Si).

For the case of n-type silicon with a perforated Au anodic contact, a rectifying interface is formed [108, 109]. The applied voltage mainly drops across the Au/Si interface, and the main contribution to the Schottky barrier height, B, in this case, is N (i.e. B = N = 0.82 eV). This value was confirmed with the Mott-Schottky plot for Au/n-Si, as shown in Fig. 2.4. It can be seen that the x-intercept of the plot, which corresponds to the built-in potential of the Au/n-Si interface, is

0.56V. Given that the doping concentration of the substrate is 1015/cm3, the energy difference between the conduction band and the Fermi level can be calculated to be 0.26eV. Therefore,

65 according to the Mott-Schottky plot, the Schottky barrier height, N, can be calculated to be

0.26eV+0.56eV = 0.82 eV, which is exactly the same as that obtained through the J-Va plot. It is also in good agreement with previous reported Schottky barrier heights of 0.77–0.82 eV for Au/ n-type silicon contact [108, 109].

Figure 2.4 Mott-Schottky plot of Au/n-Si. The measurements were conducted at 1 MHz using Agilent 4980A.

Au/p-Si forms an ohmic contact [110], and therefore, the applied voltage is primarily dropped across the etchant/p-Si interface. As additional proof of this, the J-Va characteristics for anodic etching of p-type Si in HF solution without the perforated Au was measured and from Fig.

2.3d and 2.3e, it can clearly be seen that the J-Va characteristics for anodic etching of p-Si in HF with and without the perforated Au is the same. This implies that the etchant/p-Si interface is current limiting, and therefore B = P = 0.76eV. Unlike the case with Au/n-Si interface, however, we were unable to verify this value with Mott-Schottky plots for the HF/p-Si interface as the standard reference electrodes of commercial electrochemical measurement systems, such as the

66 porous glass plug, are susceptible to damage by the HF electrolyte. It should be noted, however, that the result is in reasonable agreement with the previous reported value of 0.62eV [111, 112].

Given that the band gap (Ec – Ev) of silicon is 1.12eV, P and N were found to be 0.3eV and

0.36eV, respectively.

To further verify the validity and reproducibility of the Schottky barrier heights derived from the J-Va plots in this section, we have also performed the same experiments and analysis on lightly doped silicon samples coated with a perforated Pt film instead of an Au film. Fig. 2.5 shows the J-Va plots for both Au and Pt catalysts.

Figure 2.5 Current density-applied voltage, J-Va, plots for electrochemical etching of lightly doped silicon substrates, etched using Au or Pt.

We determined the barrier heights for Pt using the same methods used for Au, and the results were shown in Table 2.1. In our model, for p-Si, the barrier mainly remains at HF-p-Si 67 interface regardless of where the contact is, as both Pt-p-Si and Au-p-Si contacts are ohmic.

Therefore, this barrier should not be affected by the metal, which is consistent with the data shown in Table 2.1. Both Au and Pt yield a barrier around 0.76eV for p-Si.

Table 2.1 Schottky barrier heights and breakdown voltage VBR (n-Si, silicon contact) determined from experimental J-Va trends obtained for Au and Pt. Experimental configuration Au Pt p-Si, metal contact 0.76eV 0.77eV p-Si, silicon contact 0.76eV 0.77eV n-Si, metal contact 0.82eV 0.89eV

For n-Si, both Au/n-Si and Pt/n-Si form rectifying contacts, so the voltage is mainly dropped across this metal-silicon interface when anodic contact is made through the metal.

Therefore, the measured barrier heights are the Schottky barrier heights for the metal-n-Si contacts.

We obtained 0.82eV for Au, and 0.89eV for Pt, which are consistent with values reported in literature [108, 109, 113]. These results, therefore, establish the trustworthiness of the Schottky barrier heights.

2.4 MAAE on lightly doped p-type silicon substrate

When p-type silicon substrates were subjected to electrochemical anodic etching, it was found that a minimum voltage of 0.3V was required before appreciable silicon etching (J 

1mA/cm2) occurred, regardless of where the anodic contact was made (Fig. 2.3d and 2.3e). Once the applied voltage crossed this threshold, for the case in which the perforated Au was the anodic contact, the contrast in Fig. 2.6a suggests that the silicon nanowires were solid, and the wires

68 remained straight. However, when the contact was made through silicon, two cases were observed.

For Va = 0.3V, the silicon nanowires were similar to those obtained with the perforated Au contact, with no porous silicon formed under the perforated Au (Fig. 2.6b). However, if Va > 0.3V, a thick layer of porous silicon was found under the perforated Au film (Fig. 2.6c) and the silicon nanowires were highly porous with rough sidewalls and more bending (Fig. 2.6d).

Figure 2.6 Representative SEM images showing the morphology of the nanowires obtained for electrochemical etching of p-type silicon substrates. The etch duration in each case was 10min. White solid arrow points to porous silicon, white dashed arrow points to solid silicon and the white dashed line demarcates the porous/ solid silicon interface. The scale bar represents 1µm. Note that the entire silicon layer underneath the nanowires shown in (d) is porous.

To understand these results, it is necessary to turn to electronic band diagrams for the Au/Si and etchant/Si interfaces. The first observation to be made is that the Schottky barriers at the Au/Si and etchant/Si interfaces are different. With reference to Figs. 2.3b and 2.3c, with N = 0.82eV, P

= 0.3eV, N = 0.36eV and P = 0.76eV, it can be seen that EC for the Au/Si interface is pinned at

0.82eV above the EF (Fermi level), and EV is pinned at 0.3eV below EF. For the etchant/Si interface, however, EC is pinned at 0.36eV above the equilibrium EF and EV is pinned at 0.76eV below the equilibrium EF. Therefore, at equilibrium, there will be band bending in the region where the silicon under the Au joins the silicon under the HF i.e. X = 0, as shown in Fig. 2.7a. This bend at the Au/Si and the etchant/Si interfaces results in an electric field that will repel any hole attempting to diffuse from the Au/Si interface to the etchant/Si interface, unless the holes have sufficient energy to overcome the energy barrier,  (= 0.46eV for our experiments). In other words, excess holes injected in the silicon will preferentially accumulate under the Au/Si interface as compared to the etchant/Si interface. This result is in line with those obtained from simulations conducted by

Huang et al. [99].

Figure 2.7 (a) Energy band diagram at the silicon surface (Y = 0), showing band bending in Si at X = 0

(where the Au meets the HF). EF here refers to the equilibrium Fermi level. The red arrow shows holes 70 being repelled by the energy barrier,  (= 0.46eV). (b) Energy band diagram at the etchant/p-Si interface before (solid lines) and after (dashed lines) the application of a positive voltage, Va, through the perforated

Au film. Holes are initially repelled from the interface (red arrows) due to an energy barrier, Vbi, but after

Va is applied, they (green arrows) face no barrier.

Turning to the specific case of p-type silicon with the perforated Au anodic contact, electronic holes could pass easily from Au to silicon, since the interface is effectively ohmic with a low Schottky barrier of 0.3eV [110]. Thus, the applied voltage, Va, is mainly dropped across the etchant/p-Si interface. An examination of the etchant/p-Si interface in Fig. 2.7b reveals that for Va

= 0, a potential barrier of Vbi = P – (EF – EC) prevents significant hole current from crossing the interface and participating in the silicon dissolution reaction. However, with the application of Va,

2 this potential barrier is reduced such that when Va  0.34V, J  1mA/cm , based on computations from Eq. (2.2). This is in line with our observation from experiments that J > 1mA/cm2 only when

Va  0.4V (Fig. 2.3d and 2.3e).

Since the rate of silicon dissolution was faster than the injection rate of holes [18], the injected holes were not able to diffuse significantly away from the Au/Si interface before being consumed in vertical etching of silicon. In addition, the energy barrier, , introduced by the perforated Au film at the surface of silicon would have further discouraged the diffusion of holes away from the Au/p-Si interface. Therefore, the majority of the holes injected into silicon through the perforated Au were involved in the dissolution of silicon directly underneath the perforated Au, leading to a highly selective etching process which results in the solid nanowires seen in Fig. 2.6a.

The etching process described above is similar to that for MACE, with the difference being that the holes for MACE are produced by the reduction of H2O2, whereas the holes for MAAE are supplied by an external power source. It is, therefore, not surprising to find that the silicon 71 nanowires obtained in Fig. 2.6a resemble those obtained through MACE of silicon [13, 15, 25,

114].

Unlike the case of anodic contact through the perforated Au, when the anodic contact is made through the silicon, holes are not supplied through the perforated Au mesh but through the bulk of the silicon. As a result, the holes no longer need to pass through the Au/p-Si interface to enter the silicon substrate, but are free to move to the Au/p-Si interface and the etchant/p-Si interface from the backside of the substrate, as shown in Fig. 2.8. However, for a significant amount of holes to travel to the etchant/Si interface for the dissolution of silicon, the applied voltage has to reduce the Schottky barrier, Vbi, substantially (Fig. 2.8a). As in the case of the

2 perforated Au anodic contact, Va  0.34 V is required for J  1mA/cm to flow through the electrochemical etching circuit. This explains the experimental observation that J  1mA/cm2 when Va  0.3V for MAAE of P-Si substrates with anodic contact made through Si (Figs. 2.3d and

2.3e).

Figure 2.8 Energy band diagrams at the (a) etchant/p-Si interface and (b) Au/p-Si interface before (solid lines) and after (dashed lines) the application of a voltage of Va (blue arrow). In this case, Va < Vbi, the applied voltage at the etchant/p-Si interface is too low to overcome the energy barrier. As a result, holes injected through the bulk silicon preferentially accumulate at the Au/p-Si interface and cause etching, as illustrated in (c).

For the p-Si substrates used in this study, Vbi = 0.46V. Therefore, when Va = 0.3 V, there is still a potential barrier of 0.16eV for holes to overcome to reach the etchant/Si interface, as shown in Fig. 3.7a. On the other hand, no barrier exists at the Au/Si interface (Fig. 2.8b). Therefore, for Va = 0.3V, holes are attracted to the Au/Si interface and cause a higher etch rate for the silicon under the perforated Au than in the regions where the silicon is uncoated (Fig. 2.8c). Note that etching of the silicon in the uncoated regions is essentially regular anodic etching, which leads to the formation of porous silicon. Therefore, in this case, no porous silicon formation is expected, which is in agreement with the morphology of the nanowires shown in Fig. 2.6b.

Once Va reaches 0.4V (i.e. Va  Vbi), the potential barrier at the etchant/p-Si interface is reduced to 0.06V, and there is no longer an energy barrier preventing holes from reaching the etchant/p-Si (Fig. 2.9a). Therefore, the etchant/p-Si interface, like the Au/p-Si interface (Fig. 2.9b), attracts holes and silicon dissolution also takes place at the regions not covered by the Au (Fig.

2.9c). This effectively leads to regular anodic etching, and porous silicon formation occurs in these areas.

Figure 2.9 Energy band diagrams at the (a) etchant/p-Si interface and (b) Au/p-Si interface, before (solid lines) and after (dashed lines) the application of a voltage of Va (blue arrow) through the silicon substrate

(Va = Vbi). Here, the applied voltage has overcome the energy barriers at the Au/p-Si and etchant/p-Si interfaces, and holes injected through the bulk silicon can reach both interfaces. As a result, silicon is etched under the Au and porous silicon is also formed away from the Au, as illustrated in (c). Green arrows indicate the movement of the holes.

As porous silicon is formed, HF will permeate through the pores and new etchant/p-Si interfaces will form so that anodic etching continues. Because of the high resistivity of porous silicon, most holes will not be able to reach the porous silicon formed at the original etchant/p-Si interface to cause complete dissolution of the porous silicon there. Moreover, the formation of porous silicon is isotropic and can eventually undercut the perforated Au. Therefore, as the porous silicon grows thicker under the perforated Au, more and more of the applied voltage is dropped across the highly resistive porous silicon layer, such that it eventually insulates the perforated Au, effectively ending the selective etching process that generates the nanowires (Fig. 2.9c).

In summary, for p-Si with anodic contact made through the silicon substrate, an applied voltage of at least 0.3V is required to overcome the built-in potential barrier at the etchant/p-Si interface before silicon etching occurs. For Va = 0.3V, MAAE dominates over regular anodic etching and silicon nanowires are formed with no porous silicon regions underneath them. For Va

 0.4V, however, MAAE and regular anodic etching compete, resulting in the formation of porous silicon nanowires on top of a thick layer of porous silicon.

2.5 MAAE on lightly doped n-type silicon substrate

When MAAE was performed on n-type silicon substrates, it was found that a much higher voltage was required to produce the same etching current density when the anodic contact was made through the silicon rather than the perforated Au (Fig. 2.10a). The J-Va plot for the case of silicon anodic contact suggests that the etching current was produced by a voltage breakdown at the Au/n-Si interface. However, the breakdown voltage observed here is much lower than the value typically reported for Au/n-Si diodes (100V) [115]. Nevertheless, the solid silicon nanowires that

75 formed in both cases exhibit similar characteristics of vertical and smooth sidewalls without any trace of a porous silicon layer (Fig. 2.10b–d). At higher current densities, the n-Si nanowires fabricated using MAAE (anodic contact made through the silicon) appeared to be more porous and mechanically weaker (Fig. 2.10e) than those fabricated at lower current densities.

Figure 2.10 (a) J-Va plot for MAAE of n-Si in 4M HF with the anodic contact made through the perforated Au and through the silicon. (b) – (e) SEM images showing the morphology of the nanowires obtained for 76 electrochemical etching of n-type silicon substrates. The etching durations were (b) 10 min, (c) 10 min, (d) 10 min, and (e) 1 min. MAAE was the only etching mechanism operating, as no porous silicon, an indication of regular anodic etching, can be observed. The scale bar represents 1µm.

Fig. 2.11a shows that when the anodic contact is made through the perforated Au with the

Au/n-Si interface forward biased, electronic holes can be readily injected into the n-Si from the perforated Au. Similar to the case with MACE (no external bias) and MAAE of p-Si (with a perforated Au anodic contact), the holes are concentrated under the perforated Au. When HF comes into contact with this thin layer of silicon where the holes are concentrated, the holes will then travel to the etchant/n-Si interface (Fig. 2.11b) and participate in the silicon dissolution reactions, bringing about highly selective etching of silicon under the Au. This results in the n-Si nanowire morphology seen in Fig. 2.10b, which is very similar to the morphology observed for

MACE and MAAE of p-Si (anodic contact made through the perforated Au).

Figure 2.11 (a) Energy band diagram showing that hole injection rate from Au to n-Si (green arrow) is higher when a positive voltage (blue arrow) is applied to the perforated Au. (b) Energy band diagram showing how holes transferred from the perforated Au in (a) are trapped at the etchant/n-Si interface near the Au, causing silicon dissolution. (c) Schematic diagram showing the injection of holes into n-Si through the Au and how these holes lead to selective etching at the Au/n-Si interface.

When the anodic contact is shifted to the silicon, the path that the holes take to the Au/n-

Si and etchant/n-Si interfaces become less straightforward. Unlike the case with p-type Si, holes introduced from the backside of the silicon would be eliminated through recombination with electrons in n-type silicon before reaching the Au/n-Si or etchant/Si interfaces [106]. Instead, holes are injected into the interfaces when the applied voltage causes reverse-bias breakdown at the sharp edges of the Au coating due to electric field crowding [116], as illustrated in Fig. 2.12a which depicts the field line concentration in the depletion region at the edges of the Au/n-Si interface. At 78 a sufficiently large reverse bias, this strong asymmetric field strength at the edges of the Au film can reach the critical field strength of 105 V/cm required to cause breakdown [117] by impact ionization [106] (Fig. 2.12b) and cause sufficient holes to be generated near the Schottky interfaces for silicon dissolution. This reverse-bias breakdown accounts for the observation that much higher voltages are required to obtain the same etching current density for silicon anodic contact as compared to perforated Au anodic contact. The electric field crowding effect explains why the breakdown voltages observed in our study are much lower than those commonly reported for Au/n-

Si diodes.

Figure 2.12 (a) Schematic diagram showing the electric field crowding effect. The concentration of electric field lines is highest at the Au edges where breakdown occurs. (b) Energy band diagram showing hole generation by impact ionization breakdown when a sufficiently large positive voltage is applied to the n-Si substrate.

Because of the band bending at the surface of the silicon shown in Fig. 2.7a, most of the generated holes will be confined to the region of silicon directly under the Au, so that preferential

79 etching of n-Si under the perforated Au will take place. However, when the concentration of the generated holes is high enough, many holes will overcome the energy barrier, , and diffuse from the Au/n-Si interface to the bare Si surface to cause porous silicon formation there. For this reason, at high applied voltages, which lead to high concentrations of generated holes (reflected as high current density), the silicon nanowires are more porous and mechanically weaker, as observed in

Fig. 2.10e.

To test the proposed model, the breakdown voltages of the perforated-Au/n-Si and continuous-Au/n-Si interfaces in dry conditions (i.e. no HF) were investigated and compared. As can be seen in Fig. 2.13a, the perforated-Au/n-Si interface breaks down at lower voltages as compared to the continuous-Au/Si interface. This is because the perforated Au film has many more edges, causing it to be more susceptible to the field crowding effect.

Figure 2.13 (a) J-Va log-log plots for continuous-Au/n-Si and perforated-Au/n-Si interfaces. The best fit line is also shown for each trend. (b) Plot of ln (1-J0/J) vs ln (|Va|). (c) Calculated and experimental J-Va

81 plots for electrochemical etching of n-Si when the anodic contact was made through the silicon substrate. The HF concentration was varied from 1M to 4M in the experiments.

To quantitatively account for MAAE in n-type silicon, with the anodic contact connected through silicon, we first assume that the rate limiting step in the etching process is the generation of holes through reverse bias breakdown and not the rate of silicon dissolution. This assumption was previously shown to be valid in MACE [18] and will be validated later for MAAE of n-type silicon using a silicon anodic contact. Based on the model described above, the expected current injected per unit area at the Au/n-Si interface under reverse bias can calculated as [106]

B  *2 kT J0  A T e , (2.3) where

1 2 q ||s BqN . (2.4) 4Ks 0

The second term in Eq. (2.4) accounts for Schottky barrier lowering due to the image force [106] and Ks is the dielectric constant of the material (11.8 for Si), o is the permittivity of space (8.85 x

-14 10 F/cm). s is the electric field strength at the surface of the silicon (Y = 0) and is given by [106]

1 2 2qND s  N EEV C  F  a , (2.5) KS0 where the current (J) due the breakdown, is given by [106]

1 JJ g 0 , (2.6) ||Va 1  VBR

and where VBR is the breakdown voltage and g is a constant. Both VBR and g are empirically determined values [106]. Rewriting Eq. (2.6) in logarithmic form, we obtain

J0 ln 1 g ln Va  g ln V BR . (2.7) J

Figs. 2.13b and c show that the experimental trend for ln (1-J0/J) vs ln (Va) follows Eq.

(2.7) very well except at high values of J and Va, for which the resistances associated with the rest of the circuit (e.g. etchant, bulk silicon etc.) distorted the J vs Va trend to a linear relation [106]

-14 (Fig. 2.13c). From Fig. 2.13b, we were able to obtain g = 1.4 x 10 and VBR = 8.5 V.

To further verify our analysis, we have also conducted the same experiments and analysis on silicon samples coated with perforated Pt instead of perforated Au and obtained VBR = 5.6 V, which is in good agreement with the breakdown voltage of 5 V previously reported for Pt/n-Si interfaces subjected to electric field crowding effects [116]. Moreover, it can be observed from

Fig. 2.13c that the J-Va trends do not vary significantly with the concentration of the HF solution for the range of Va tested, suggesting that the rate limiting step is the hole generation process and not the dissolution process, which validates the assumption made above in development of the quantitative model.

2.6 MAAE on heavily doped n-type and p-type silicon substrate

We first measured the J-Va curves of heavily doped substrates, as shown in Fig.2.14. The curves show an ohmic behavior for both types of silicon substrates and with anodic contact to both

Au and Si.

Figure 2.14 Current density–applied voltage, J-Va, plots for electrochemical etching of heavily doped silicon substrates.

When p+ and n+ silicon substrates were subjected to electrochemical anodic etching in HF with perforated Au anodic contacts, the results were similar to those previously obtained for lightly doped p-type and n-type Si substrates (Fig. 2.15). The only difference in this case was that the silicon nanowires appeared to be more porous and were standing on top of a layer of porous silicon.

Given that this was seen for heavily doped substrates but not lightly doped substrates, even though the etching current density and voltage were similar for both, it follows that the formation of this porous layer was caused by material properties rather than process parameters.

Figure 2.15 Representative SEM images at different magnifications showing the morphologies of the nanostructures obtained for (a) p+ and (b) n+ Si substrates with the anodic contact made through the perforated Au. The current densities and durations of etching were (a) 12.5mA/cm2, 10min and (b) 8mA/cm2, 10min. White arrows indicate porous silicon regions. The scale bars in (ai) and (bi) represent 1 µm, and those in (aii) and (bii) represent 500 nm. White arrows point to porous silicon, while the white dashed arrow points to solid silicon. The dashed white line indicates the porous/ solid silicon interface. In (b) all of the area shown under the wires is porous.

It has previously been suggested that dopants in silicon can cause defect sites [118] that lower the energy barrier for silicon dissolution [119], thereby leading to the formation of pores in the silicon. In this case, it is not surprising to observe porous layers underneath the silicon nanowires in MAAE, as heavily doped substrates have a much higher concentration of dopants as compared to lightly doped samples (105 times for the wafers used in this study). 85

When the anodic contact was changed to silicon, the morphologies of the nanostructures obtained on p+ and n+ silicon were very different. For the case of p+ silicon, highly porous silicon nanowires were obtained on a thick porous silicon layer (Fig. 2.16a), while for n+ silicon, a thick porous layer was obtained with very short silicon nanowires on top of it (Fig. 2.16b). These observations suggest differences in the mechanism of anodic etching of p+ and n+ silicon substrates.

Figure 2.16 Representative SEM images at different magnifications showing the morphologies of the nanostructures obtained for (a) p+ and (b) n+ silicon substrates with the anodic contact made through the silicon substrate. The current densities and durations of etching were (a) 23mA/cm2, 5min (bi) 23mA/cm2, 5min and (bii) 28mA/cm2, 5min. Yellow arrows point to a thin layer of anti-reflection coating on the silicon nanowires that was not fully dissolved by the solvent NMP. The scale bars in (ai) and (bi) represent 1 µm while those in (aii) and (bii) represent 500 nm.

For p+ substrates, anodic etching takes place because of the injection of holes from the contact into the silicon. Much like the case of p-type substrates shown in Fig. 2.9c, because of the ohmic nature of the Au/p+-Si and etchant/p+-Si interfaces, the injected holes will cause regular anodic etching and MAAE to take place simultaneously. The end result is therefore similar for both cases, with the formation of porous p+-Si nanowires and a porous layer underneath.

Unlike the case for p-type silicon, however, holes can freely travel past the etchant/p+-Si interface at all voltages and hence, there is no threshold voltage below which the formation of porous silicon is suppressed. Once again, metal assisted anodic etching effectively ceases once the highly resistive porous silicon reaches a thickness large enough to effectively insulate the Au/p+-

Si interface from the applied voltage.

In contrast, anodic etching of n+-Si substrates depends on the surface generation of electron-hole pairs at the etchant/n+-Si interface to provide the holes necessary for silicon dissolution [120, 121]. This surface generation process incorporates tunneling (Fig. 2.17a), as the energy required for an electron to jump from the valence band to the conduction band in this way is less than the band gap. As a consequence, the rate of surface generation can be much larger than the rate of the thermal generation in silicon. However, since this process depends on tunneling, substantial surface generation of holes, and therefore, anodic etching of silicon in HF at low applied voltages, can only take place for n+ substrates with doping concentrations above 1018/cm3

+ [121]. Note that the J-Va trend for electrochemical etching of n -Si is ohmic regardless of where the anodic contact is made, much like the case of p-Si and p+-Si.

Figure 2.17 (a) Energy band diagram illustrating the process of surface generation of electron-hole pairs in n+-Si by means of a tunnelling transition stage. Because this surface generation occurs at the etchant/n+-Si interface, the majority of the holes are concentrated at the surface of the silicon in contact with the HF, where they are consumed in porous silicon formation, as illustrated in (b). As a result, little or no nanowire formation is observed.

As in the case for n-type Si (Fig. 2.7a), the Au/n+-Si interface provides a lower energy level for the surface generated holes to fall to, thus creating an electric field that sweeps the generated holes toward the Au/n+-Si interface and enhancing the etching of silicon under the Au, i.e. MAAE.

Unlike the case for n-type silicon, however, the generation of holes does not take place at the edges of the perforated Au film (i.e. X = 0), where the newly created holes can be rapidly swept by the electric field to the silicon under the Au, but takes place, instead, across the entire etchant/n+-Si interface. Therefore, most of the generated holes will be consumed in the formation of porous silicon (regular anodic etching) at the etchant/n+-Si interface before they are swept to the Au/n+-

Si interface to be used in MAAE (Fig. 2.17b). The net result is, therefore, more rapid formation of porous silicon through regular anodic etching, relative to the rate of metal assisted anodic etching.

This, in turn, prevents significant nanowire formation (Fig. 2.17b).

It is also worth noting that the anodic etching rates of heavily doped silicon substrates in

HF at high current densities appear to be strongly dependent on the exposed crystallographic planes. As can be seen from Fig. 2.16, dendrite branching in <113> directions from a central <100> channel can be observed in the porous layer of the silicon, and also in the silicon nanowires. In addition, instead of obtaining silicon nanowires, electrochemical anodic etching of n+-Si was found to produce regular nanotubes/ nanorings (Fig. 2.16b). Dendritic porous silicon structures have previously been observed for regular anodic etching of lightly doped n-type silicon in an organic electrolyte using illumination on the backside of the wafer [103]. However, a linkage between this result and the result reported here is not clear. This is the first time that aligned dendritic structures have been found in silicon nanowires formed using electrochemical etching of silicon.

2.7 Pt-catalyzed MAAE

Au and Pt show very different catalytic activities in the conventional MACE process.

However, Au and Pt behave similarly for MAAE. As discussed in previous sections, Pt has been used as an alternative catalyst in MAAE to testify the models we proposed.

For lightly doped silicon substrates, the Schottky barrier heights extracted from the J-Va curves support our discussions of mechanisms based on results on Au. The breakdown voltage we extracted for n-Si with anodic contact made through silicon is also in good agreement with the range of breakdown voltages previously reported [116]. In addition, we also carried out

89 morphologic studies with SEM images. For example, Fig. 2.18 shows representative images of lightly n-doped silicon substrates etched from MAAE with silicon anodic contact. It can be seen from the images that only silicon nanowires were produced without porous silicon formation even at very high current densities. This is consistent with the phenomenology in Au catalyzed MAAE.

Pt catalyzed MAAE with other experimental configurations also showed similar morphologies as

Au.

Figure 2.18 SEM images showing the morphology of nanowires obtained by electrochemical etching of N-type silicon substrates (with Pt on the front surface) with the anodic contact made through the silicon substrate. Etching parameters are given for each image.

For heavily doped silicon substrate, we also measured the J-Va curves for Pt catalyzed

MAAE (Fig. 2. 19). The curves also showed similar trends as Au catalyzed MAAE as shown in

Fig. 2. 14. Therefore, it is verified that metals with a similar work function show similar behavior as MAAE catalyst. We can conclude that our model is valid.

Figure 2.19 Current density-applied voltage, J-Va, plots for electrochemical etching of heavily doped Si substrates with Pt.

2.8 Conclusions

The formation of silicon nanowires through the use of metal assisted anodic etching was investigated. Results obtained for varions substrate types and for anodic contact through perforated

Au or through the silicon substrate are summarized in Table 2.2.

Table 2.2 Overview of the nanostructure morphologies observed for each type of wafer and contact location. Contact Wafer type Nanowires Porous layer Source of h+

p (10-20ohm-cm) Yes — External source through

Perforated Au p+ (0.005-0.01ohm-cm) Yes Yes Au/Si interface Equivalent to MACE n (10-30ohm-cm) Yes —

n+ (<0.005ohm-cm) Yes Yes External source through p (10-20ohm-cm) Yes Yes both Au/Si and etchant/Si

interfaces p+ (0.005-0.01ohm-cm) Yes Yes Equivalent to MACE +

Bulk Si Anodic Etching Breakdown at Au/Si n (10-30ohm-cm) Yes — interface Breakdown at etchant/Si n+ (<0.005ohm-cm) — Yes interface

Using J–Va plots, the Schottky barrier heights of the Au/Si and etchant/Si interfaces were determined and energy band diagrams were constructed using the measured barrier heights. These, together with the observed morphologies of etched silicon nanowires and substrates, were then used to show that mechanisms of electrochemical anodic etching of silicon with the anodic contact made through the perforated Au is effectively the same as the mechanisms of the MACE process, regardless of the substrate doping type.

In these cases, holes required for silicon dissolution reactions were injected into the silicon via the perforated Au film, which led to them being concentrated directly under the perforated Au.

As a result, the etch rate was much faster for silicon under the perforated Au than in uncoated silicon regions. Solid nanowires were obtained for lightly doped substrates (of either n or p type), 92 and no porous silicon layers were observed. Etching of heavily doped silicon (of either n or p type) led to formation of porous nanowires on top of porous layers in the substrate.

In contrast, when anodic contact to p-Si was made through the silicon, both regular anodic etching and MAAE took place. If the applied voltage was below a threshold voltage Vbi, MAAE dominated and relatively solid p-Si nanowires were obtained with little or no porous p-Si formed.

However, if the applied voltage was above the threshold voltage, regular anodic etching and

MAAE were concurrent and highly porous silicon nanowires were formed on top of thick porous silicon layers. It was argued that this happens below the threshold voltage, when the Au/p-Si interface was ohmic but the etchant/p-Si interface was not. If the applied voltage exceeds the threshold values, both interfaces become ohmic.

For n-Si, when the anodic contact was made through silicon, solid nanowires formed with no porous silicon underlayers, similar to the case when n-Si was etched with the anodic contact made through the perforated Au film. However, the formation mechanisms were different and it was proposed that the holes required for MAAE with silicon anodic contact were generated when electric field crowding occurred at the edges of the perforated Au, causing reverse bias breakdown at relatively low applied voltages. Using standard analyses from semiconductor physics, the proposed model was shown to agree well with experimental data.

Results obtained for p+-Si with anodic contact through the silicon were the same as results for p-Si: porous silicon nanowires formed over a thick porous silicon layer. Unlike the case for p-

Si, however, there was no threshold voltage below which MAAE could dominate over regular anodic etching, as both the Au/p+-Si and etchant/p+-Si interfaces were ohmic at all applied voltages.

Lastly, electrochemical anodic etching of n+-Si with silicon anodic contact led to formation of very short silicon nanowires on top of a very thick porous silicon layer, indicating that regular anodic etching dominated the etching process. It was argued that this is because the holes required for silicon dissolution were generated at the etchant/n+-Si interface and thus, most of them were consumed in the formation of porous silicon before they could diffuse or drift to the Au/n+-Si interface. This study shows that the morphology of the nanowires and the silicon layer underneath obtained through MAAE depends strongly on the site of hole injection and the electronic energy levels at the metal/Si and etchant/Si interfaces. Analyses of the effects of band structures at the

Au/Si and etchant/Si interfaces can be used to explain the results of both MAAE and MACE, and create a unifed understanding of electrochemical etching in both cases.

Silicon Nanowire Based MOS Capacitors

3.1 Introduction

Nanostructured silicon has been extensively studied due to its potential applications in electrochemical energy storage, sensing, and power management in integrated circuits. In particular, its application in capacitors is attractive since capacitors are promising energy storage devices in autonomous microsystems [122] as they can release energy at high rates leading to high powers, e.g. for data broadcasting. High density capacitors are also widely used as on-chip switched capacitor converters for dynamic power management [45], as well as integrated RF decoupling capacitors [49]. For embedded applications in circuits, a high capacitance density (high capacitance per footprint area) is desirable to scale down the chip size. In current IC technology, capacitors with high capacitance densities is achieved through the use of trench structures [51, 52], as discussed in the introduction chapter. In this case, the increased surface created through fabrication of 3D trench structures leads to the increased capacitance density. As also discussed in chapter 1, there has been considerable research on use of other 3D high surface area structures, such as nanowire arrays [53] as an alternative to silicon trenches.

Using silicon as one electrode, metal-oxide-semiconductor (MOS) capacitors can be built for a range of applications such as on-chip switched capacitor converters for dynamic power management [45] and integrated RF decoupling capacitors [49]. Though previous research has demonstrated an increase of the capacitance density in MOS capacitors based on MACE-generated silicon nanowires [53], that work did not include study of the alternating current (AC) capacitance at various frequencies. During voltage sweeping with AC, silicon electrodes will go through accumulation, depletion and inversion stages[106]. Once the maximum depletion width is

96 comparable to the feature size of the introduced nanostructures, the performance of the device in the depletion and inversion regimes will be affected. Moreover, a high series resistance associated with the capacitor structure will cause a reduction in the effective AC capacitance, and lead to poor performance in some IC applications. In the work described in this chapter, these important characteristics of silicon nanowire MOS capacitors were assessed.

A process was developed to fabricate nanowire capacitors in single crystal silicon substrates as well as in polycrystalline silicon films. The performance of devices with different embedded series resistances were characterized and analyzed under AC conditions.

3.2 Silicon nanowires generated by MACE

Two types of (100) single crystal silicon wafers including p-type (boron-doped, bulk thickness~550 µm and doping~1x1015cm-3), p-type epitaxial wafer (boron-doped, bulk thickness~775µm and doping~1x1019cm-3, epitaxial layer thickness~3µm and p-type doping

~1x1016cm-3) were used to fabricate single crystal silicon based capacitors. A 1.1µm thick intrinsic polycrystalline silicon film was also deposited on a p-type (boron-doped, bulk thickness~550 µm and doping~1x1015cm-3) single crystal silicon substrate by low-pressure chemical vapor deposition

(LPCVD) for poly-Si based capacitor fabrication. The single crystal silicon substrates were then etched with Au catalyzed MACE in a solution with a composition of H2O: HF (49%): H2O2 (30%)

=36:6:1. As the polycrystalline silicon films were not doped, a different etchant with a composition of H2O: HF (49%): H2O2 (30%) =36:6:0.4 was used.

It is preferable to start with a heavily doped substrate, as low series resistance is preferred for better capacitor performance at high operating AC frequency. However, MACE of heavily

97 doped silicon substrates generally leads to silicon nanowires that have a high level of nanoscale porosity [25, 26, 36]. Such porous structures exhibit a high electrical resistance [118] and add additional challenges to the subsequent fabrication process. Therefore, we carried out experiments on wafers with a heavily doped bulk and a lightly doped epitaxial layer, in addition to the standard lightly doped single-crystalline substrates. While reducing the resistance from the bulk silicon at the same time, epitaxial wafers will generate non-porous silicon nanowires as long as the etching is carefully controlled so that it won’t intrude into the heavily doped bulk silicon. If the sample is kept in the etchant for a prolonged time, it will show nanowires with a sharp transition from a non- porous structure in the lightly doped epi layer to a highly nanoporous structure in the heavily doped regime, as shown in Fig. 3.1.

Figure 3.1 Transmission electron micrograph of a silicon nanowire MACE-etched from the epitaxial wafer.

Three types of wafers as described previously were used to etch silicon nanowires for capacitors, including the lightly doped p-type substrate, heavily doped p-type substrate with a lightly doped p-type epitaxial layer and lightly doped p-type substrate with an intrinsic

98 polycrystalline silicon film on top. Fig. 3.2 shows the nanowire morphologies obtained using

MACE (Figs. 3.2a, 3.2b and 3.2c), as well as the as-deposited polycrystalline silicon film before etching (Fig. 3.2d). For poly-crystalline silicon films, wires were successfully produced by increasing the HF concentration and decreasing the oxidant concentration. Though the as- deposited polycrystalline silicon films had a high surface roughness, this did not affect the MACE process and resulted in polycrystalline silicon nanowires.

Figure 3.2 (a) Silicon nanowire arrays from etching lightly doped p-type substrate for 7min; (b) nanowire arrays from etching a heavily doped substrate with a lightly doped epitaxial layer for 7min; (c) nanowires arrays from etching of intrinsic polycrystalline layers on lightly doped substrates for 5min; (d) as-deposited polycrystalline silicon film.

3.3 Conductivity improvement of the silicon nanowires

3.3.1 Silicidation

Single crystal silicon nanowires, as described in section 3.2, are lightly doped and the polycrystalline silicon nanowires are intrinsic. To study the effect of the series resistance contributed from the nanowires, we investigated approaches to reduce the resistance of the nanowires.

First, the possibility of converting the silicon nanowires to silicide nanowires was explored.

We coated the silicon nanowires with a metal for lowering the resistance by silicide formation at an elevated temperature, as shown in Fig. 3.3. We first studied Ni, because it can be readily deposited by sputter deposition or e-beam evaporation. There has also been a lot of research on the formation of nickel silicide [123-127].

Figure 3.3 Schematic representation of silicide formation on silicon nanowires.

Nickel was first deposited using e-beam evaporation onto silicon nanowires (Fig. 3.4b).

Though e-beam evaporation cannot yield a conformal coating of nickel, it was chosen based on the assumption that the whole nanowire should be converted to silicide even if there was only a

100 metal/Si contact at the top of the nanowires. Before e-beam evaporation, the sample was first dipped into Au etchant TFA (Transene Co.) to remove the Au. Then after immersing in a dilute

HF solution to remove the native oxide, the nanowire samples were transferred into the e-beam chamber immediately for nickel coating. It can be seen from Fig. 3.4b that e-beam evaporation led to an approximately 100nm Ni layer on top of and in between the silicon nanowires, as well as sparse Ni particles on the sidewalls. The sample was annealed for 2 hours at 450℃ under reducing gas for silicidation (Fig. 3.4c). Finally, the excess Ni was removed using a Ni etchant at room temperature (Fig. 3.4d). Fig. 3.4c shows silicide formation at the top of the nanowires and the planar silicon in between the nanowires, as can be seen from the contrast in the nanowires.

However, complete conversion of silicon nanowires was not observed. Moreover, the Ni showed dewetting behavior, even though the native oxide should have been removed before nickel deposition.

101

Figure 3.4 (a) Silicon nanowires generated using MACE, (b) after e-beam evaporation of Ni, (c) annealed at 450℃ for 2hours, and (d) after removal of excess Ni.

We then used sputter deposited nickel coatings on another set of silicon nanowires, as sputtering led to a more conformal coating than e-beam evaporation (Fig. 3.5b). The samples then went through the same annealing process as the e-beam samples (Fig. 3.5c), and excess Ni was removed afterwards (Fig. 3.5d). Fig. 3.5c shows that Ni particles on the nanowire sidewalls reacted with silicon to form silicide, as well as the Ni layer at the bottom of silicon nanowires. However,

Ni deposited on top of the wires dewetted.

102

Figure 3.5 (a) Silicon nanowires generated using MACE, (b) after sputtering deposition of Ni, (c) annealed at 450℃ for 2hours, and (d) after removal of excess Ni.

Various techniques were used to characterize the silicided nanowires in Fig. 3.5d. XRD was carried out on the sample before and after silicidation. The two sets of data were compared to extract new peaks that appeared after silicidation, as shown in Fig. 3.6a. The peaks correspond well to the NiSi phase. The selected area electron beam diffraction showed that the silicide phase was only present in some regions (Fig. 3.6c). In other regions, however, only silicon was observed

(Fig. 3.6d). Therefore, silicide formation was not conformal along the nanowire.

103

Figure 3.6 (a) XRD peaks from silicided wires, (b) TEM image, and (c) and (d) the selected area electron diffraction of nanowires after silicidation and excess Ni removal.

We also investigated the effect of adding an extra step to clean the surface of the silicon nanowires. After the HF dip before placing the sample in the sputter chamber to remove native oxide, back sputtering was also used right before Ni sputtering. The nanowires’ shapes (Fig. 3.7b) were different compared to the sample without back sputtering (Fig. 3.5b). The nanowires were successfully silicided, as can be seen from the change in the nanowires and the substrate before and after annealing. However, the nanowires became twisted and bent after annealing, which made it difficult to use them for device application. Moreover, from the zoomed in image in Fig. 3.7d, threadlike materials formed after annealing. They either are the result of the silicidation reaction or from the impurities in the sputter chamber. The reason for this is unclear.

104

Figure 3.7 (a) Silicon nanowires generated using MACE, (b) after sputter deposition of Ni after back sputtering, and (c) and (d) annealed at 450℃ for 2hours.

Another approach was to use atomic layer deposition to deposit Pt on the wires to form platinum silicide, which has superior coating conformity compared to the previous methods.

MACE-etched lightly doped n-type silicon pillars were coated with 30nm thick Pt films using atomic layer deposition and then heated to 550 ºC. Unfortunately, we found that the wires did not react uniformly, and that when silicides did form, the large grain size led to the lump formation

(Fig. 3.8b). Cross sectional samples were prepared using focused ion beam as shown in Fig. 3.8c.

From the HRTEM images in Fig. 3.8d and e, we found lattice spacings corresponding to Pt (110) or Pt2Si (110) near the edge and lattice spacings corresponding to PtSi (110) close to the center.

105

We concluded that silicide did form on the samples, but the silicide was large-grained and led to a significant change of the pillar geometry. In summary, etched nanowires were found to result in non-conformal reactions with both Pt and Ni over a wide range of conditions.

Figure 3.8 (a) Silicon nanowires coated with ALD Pt, (b) nanowires after annealing, (c) cross sectional TEM images of silicide nanowires after annealing, (d) HRTEM mage near the edge of a nanowire and (e) HRTEM image close to the center of a nanowire.

106

3.3.2 Post-MACE doping

Because of difficulties with siliciding the nanowires, we looked at an alternative approach to improve the conductivity of silicon nanowires, i.e. post-MACE doping (Fig. 3.9) to increase the doping concentration on the surface layer of the wafer. We studied doping process for both n-type and p-type nanowires from phosphorus and boron doping source wafers, respectively. During the doping process, P2O5 or B2O3 vapor will evolve from the source wafer. The oxide vapor will then form a thin layer on the silicon wafer surface that then acts as the doping source during diffusion.

The reactions that occur at the interfaces are as follows:

2B2 O 3 +3Si 4B+3SiO 2 , (3.1)

2P2 O 5 +5Si 4P+5SiO 2 . (3.2)

Figure 3.9 Schematic representation of post-MACE doping.

The n-type samples were doped from a solid doping source wafer (PH-950, Saint-Gobain), which had silicon pyrophosphate (SiP2O7) on a porous silicon carbide substrate. The doping process was carried out at 925℃ for 30min. This is an intermediate temperature within the 107 recommended temperature window of 875℃ to 950℃. At a high temperature of 950℃, a thick oxide layer formed, resulting in severe deformation of the nanowires. Therefore, the intermediate temperature was chosen to reduce the oxide film thickness, while still enabling a relatively high doping concentration compared to lower temperatures such as 875℃. The samples were deglazed in dilute HF solution to remove the oxide after doping. As can be seen from Fig. 3.10a-c, nanowires remained vertical after the doping and deglaze process. A comparison between original nanowires and doped nanowires revealed that the doping process did not severely change the geometry of the nanowires, except some sharpening at the tip of the nanowires. We have also carried out an EDX study on the sample, which showed a uniform distribution of phosphorous in the nanowires (Figs.

3.10d, 3.10e). We also did a quantitative mapping as shown in Fig. 3.10f. The results showed an atomic ratio of phosphorous to Si of roughly 6:100, indicating a high concentration of dopants in silicon. The doping process was also studied with the p-type doping source, as detailed in the following paragraphs, since this process was used for MOS capacitor fabrication.

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Figure 3.10 SEM images of (a) as generated n-type silicon nanowires, (b) nanowires after doping and before oxide removal, (c) silicon nanowires after the deglaze process, (d) TEM image of a doped nanowire after the deglaze, (e) phosphorous mapping on the nanowire in (d), (f) elemental mapping of Si, P, O across the nanowire. The inset in (f) shows the mapping path on the nanowire.

The p-type doping was carried out with a boron source wafer (BN-1250, Saint-Gobain), that is composed of BN and SiO2. Before the doping process, the wafer was first activated following the procedure suggested by the vendor in order to form an active B2O3 layer on the surface. We chose to dope at 950℃ for 30min, as the nanowires were significantly deformed at higher temperatures (1000-1100℃). A test of this process on the silicon nanowires showed that the wires were robust over the entire process, and negligible geometric changes were observed even on long nanowires (Fig. 3.11).

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Figure 3.11 SEM images of (a) as generated p-type silicon nanowires, nanowires (b) after doping and (c) after the deglaze process.

We also carried out studies on the diffusion profile under this doping condition, following

Eq. (3.3) assuming intrinsic diffusion of boron in silicon.

x C x, t  Css erfc. (3.3) 2 Dt

In this equation, Css is the surface concentration of boron, which was assumed to stay at the solubility limit of 1.5 1020 atoms/cm3 at 950℃ [128]. The diffusivity D was taken to have the value 4 1015 cm2/s. After 30min of doping, the dopant distribution profile showed a heavy doping above 1 1018 atoms/cm3 within 100nm distance into Si (Fig. 3.12), which was the radius scale of the nanowires fabricated in this thesis. Moreover, considering the shape of the nanowires, the dopants came in from all exposed surface. Therefore, the nanowires were heavily doped under such conditions compared to the original doping concentration of 1 1015 atoms/cm3 from the lightly doped p-type wafer. We also carried out sheet resistance measurement to determine whether the dopants were electrically active. A lightly doped n-type planar silicon substrate (10-20Ω-cm)

110 went through the same boron doping process as discussed above, which led to a p-n junction formation. The resistivity of the boron doped surface layer can be calculated using Eq. (3.4):

 Rxsj. (3.4)

The doping concentration of phosphorous in the n-type silicon was 2 1014 to 5 1014 atoms/cm3,

which yielded a junction depth x j around 0.18µm, as seen in Fig. 3.12. The measured sheet

resistance Rs was 61Ω/sq. This led to a resistivity around 0.001 Ω-cm. Considering the doping concentration is not uniform within this 0.18µm region, a more complex model is necessary to calculate the resistivity more precisely. However, our calculation provides a rough estimation and confirmed the doping process significantly improved the conductivity of the surface silicon layers.

Figure 3.12 Boron concentration vs. distance into Si.

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In the MOS capacitor fabrication process flow that will be discussed later, the doped sample was heated to 950℃ after doping for the silicon dioxide dielectric growth. This acts as an additional annealing process that flattens the dopant distribution, leading to a more uniform dopant profile in the nanowires. Therefore, we therefore relied on this approach for reducing the nanowire resistance.

3.4 Single crystal silicon nanowire based capacitors

3.4.1 Fabrication and capacitance measurements on four types of devices

We developed a process to fabricate MOS capacitors based on silicon nanowires generated by MACE, as shown in Fig. 3.13. After the MACE process, the Au catalyst was removed from the silicon nanowire sample. The samples were then subjected to a dry thermal oxidation process at

950℃ with a target oxide thickness of 35nm. A seed layer of 10nm Cr/ 100nm Au was then deposited by e-beam evaporations, and this was followed by a lithography step to define the capacitor area for electroplating of the gate metal (Ni). Finally, the resist and seed layer underneath the resist were removed, and the back contact was made by evaporating 10nm Cr/100nm Au layers.

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Figure 3.13 Process flow for silicon nanowire based capacitor fabrication.

Four different types of single crystal silicon based capacitors were fabricated following the process flow described above, as summarized in Table 3.1. A post-MACE doping from a solid boron source was carried out on as-etched nanowire arrays from epitaxial wafers to further reduce their resistance, which resulted in the Type IV device in the table.

Table 3.1 Descriptions of the four MOS single-crystalline capacitors. Device type Type I Type II Type III Type IV Silicon Planar Lightly doped Epi-wafer with Epi-wafer with electrode p-type nanowires~600 nm nanowires~600 nm, type nanowires~1.2 µm (no additional with an additional doping) doping of nanowires

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Schematic of the electrode

An Agilent B1500A system was used to make both quasi-static and high frequency capacitance-voltage (CV) measurements. Then CV characteristics of these four types of wafers were measured, as shown in Fig. 3.14. By comparing Figs. 3.14a and 3.14b, it can be seen that an increase by a factor of 4.5 in capacitance density was achieved with nanowire structures, as approximately expected from the geometry of the nanowire arrays according to the scaling equations detailed in the next section. Moreover, lightly doped Si nanowire electrodes on top of heavily doped bulk substrates (Type III, Fig. 3.1c) have a smaller frequency dispersion in the accumulation regime than lightly doped nanowires on lightly doped substrates (Type II, Fig. 3.14b), which demonstrates that the bulk resistance plays a dominant role in the capacitance of nanowire- based capacitors at high frequencies. The large frequency dispersion in the Type II device might result from the existence of both high capacitance densities and high resistance. The Type IV devices (Fig. 3.14d) show a more stable capacitance across the entire gate voltage range compared to Type III devices (Fig. 3.14c). This is because nanowires in Type IV devices are so heavily doped that the oxide capacitance dominates in all three regimes: accumulation, depletion and inversion.

However, the frequency dependence of the negative-bias capacitance is not significantly different in Type III and IV devices, suggesting that the nanowires do not contribute significantly to the overall series resistance that limits the effective AC capacitance. The hysteresis seen in the double

114 sweep CV curves and the bump in the low frequency CV curves in Fig. 3.14a suggest a relatively large interface trapped charge density, which can be improved through optimization of the dielectric deposition and annealing process. The lateral frequency dependent shift in all figures is also related to a large interface trapped charge density. The small drop in the negative bias capacitance in Fig. 3.14d compared to Fig. 3.14c may be due to process variations.

Figure 3.14 CV curves of four types of 100 µm *100 µm devices: (a) (double sweep) at various AC frequencies for a Type I capacitor; (b) (single sweep) at various AC frequencies for a Type II capacitor; (c) at various AC frequencies for a Type III capacitor; (d) at various AC frequencies for a Type IV capacitor.

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3.4.2 Scaling of device performance with nanowire array geometries

Having demonstrated that use of nanowire structures leads to an increase in the capacitance density, we have developed a quantitative framework for analyzing the effect of nanowire geometry on device performance. We calculate the dependence of the accumulation capacitance on nanowire array geometrical characteristics. We treat the nanowire devices as cylindrical capacitors in parallel. Therefore, the capacitance of the sidewall of a single nanowire capacitor can be expressed as [53]

2  l C  0 r , (3.5) single ln b/a

where  0 is the permittivity in vacuum,  r is the dielectric constant, a is the initial diameter of the nanowire, b is the diameter after thermal oxidation, and l is the length of the nanowires. The

capacitance from the sidewalls of all the nanowire arrays can be calculated by multiplying Csingle by the number of nanowires, as shown in equation (3.6):

2  l A C 0 r , (3.6) all ln b/a p2 where A is the chip area and p is the period of the array. In addition to the capacitance from the nanowire sidewalls, the total capacitance should also include the contribution from the top surface of the nanowires and the planar silicon in between the nanowires. They can be treated together as a planar Si MOS capacitor with an area of A and dielectric thickness of (b-a)/2. This capacitance is calculated using the following equation:

 C 0 r A, (3.7) planar ba  /2

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Therefore, the total capacitance of a nanowire based MOS capacitor is estimated as

2 l A   C 00rr    A . (3.8) total ln b/a p2  b a / 2

The increase factor achieved with a silicon nanowire capacitor over a planar MOS capacitor with the same dielectric material and thickness is

Ctotal la(b ) Increase Factor=2 1. (3.9) Cpplanar ln b/a

In Type II single crystal nanowire capacitors, p is 400nm, a is 180nm, b is 249nm

(dielectric thickness tox is 34.5nm), and l is 1.2µm, which should yield an increase factor of 6. The experimentally determined factor of 4.5 is less than expected, which might be due to the resistance effect under the AC test conditions, the non-uniform wire lengths or dielectric thickness on the silicon nanowires. The capacitance density versus period and length are shown in Figs. 3.15a and

3.15b, respectively. In both figures, the measured data from current devices are marked with blue triangles, while the red stars show the theoretical results. It is also clear from these two figures that the experimental values were lower than the theoretical value, as discussed earlier in this paragraph.

The grey area represents regimes of nanowire geometry that are currently beyond the range of ready fabrication using the process described above.

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Figure 3.15 Dependence of capacitance density on (a) the period of the nanowire array; (b) the nanowire length.

We can further improve the capacitance density by using nanowire arrays with higher aspect ratios that can still be readily prepared by MACE and better dielectric. For instance, if we use nanowire arrays with the parameters of p=400nm, a=200nm, b=210nm (silicon dioxide

2 dielectric thickness tox=5nm), and l=9 um, the capacitance density can be as high as 25µF/cm , which is comparable to 23 µF/cm2 as reported for state of the art silicon trench capacitors in the literature [51].

3.4.3 The effect of nanowire diameter on the capacitor performance

Additionally, we investigated the effect of the nanowire diameter on device performance.

When the nanostructure feature size is comparable to the maximum full depletion width of the device, nanowires might be fully depleted during the voltage sweeping. If they are fully depleted

118 before reaching inversion regime, the device will go through four different stages as shown in Fig.

3.16.

Figure 3.16 Four stages that a device goes through if the nanowires can be fully depleted.

For planar MOS capacitors, the maximum depletion width depends on the doping level of the substrate. The maximum depletion thickness is given by

2s sT 2kT N A xdmax ,  sT ln , (3.10) qNAi q n

where xd max is the maximum depletion thickness,  s is the absolute permittivity of silicon, sT is the surface potential at threshold between the surface and bulk of silicon, q is the elementary charge,

N A is p-type doping concentration, ni is the intrinsic carrier concentration, k is the Boltzmann 119 constant, T is the room temperature. When the maximum depletion thickness exceeds the radius of the nanowires, they will be fully depleted before inversion. Table 3.2 shows the critical nanowire diameters below which they will be fully depleted. From this table, a Type II device with nanowire diameters of 180nm and a doping level of ~1x1015cm-3 should be fully depleted. To be more accurate, though, the electrostatics in the nanowires are different from a planar surface due to their cylindrical geometry. In nanowires, the maximum depletion width also depends on the nanowire

radius. However, even for the limit of full depletion of the nanowires ( xrdmax  NW ), the depletion layer width only increases by a factor of 2 compared to the depletion of a planar surface [129].

Therefore, the calculations made above with one a dimensional depletion model are good approximations to determine whether the nanowires in this work are fully depleted.

Table 3.2 Critical nanowire diameters for different doping concentrations.

Dopant concentration Maximum depletion width Critical nanowire diameter

1x1015cm-3 887.8nm 1775.6nm

1x1018cm-3 35.2nm 70.4nm

We assessed whether nanowires in a Type II device are fully depleted by obtaining a Mott-

Schottky plot from experimental data measured from Type I and II devices at 1kHz (Fig. 3.17). In the depletion regime the relationship in the Mott-Schottky plot should be linear, following the equation:

12 kT 2  (V VFB  ) . (3.11) CSC s0 qN A q

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By fitting a line to the data in the planar device plot, we extract the doping level from the slope of the line and the flat band voltage from the intercept. The obtained doping level is

1.12x1015cm-3, which matches the wafer description from the vendor.

Figure 3.17 Mott-Schottky plots for 100um*100um Type I and II devices measured at 1 kHz.

The nanowire device has a linear regime with the same slope as the planar device, indicating that nanowires have fully depleted. This is because the nanowires only contribute to the surface topography increase, which means under the same gate voltage, the Type II device has a larger capacitance density compared to the Type I device. Therefore, the nanowire device should show a linear depletion with a smaller slope but the same intercept in Mott-Schottky plots. In the current case, however, the two devices have the same slope, meaning that the nanowire device has the same characteristics as the planar device during most of the depletion process. This is reasonable as once nanowires are fully depleted, the active surface area becomes that of the initial

121 footprint. Therefore, the analysis on experimental data agrees with the theoretical prediction shown in Table 3.2. In summary, for nanowires with larger diameters that do not fully deplete, a change in the slope in the linear regime in the Mott-Schottky plot will occur. For nanowires with different diameters that will be fully depleted, a shift of curves with the same slope but different intercepts is expected.

Finally, though the nanowires always contribute to scaling of the capacitance density in the accumulation and inversion regimes of MOS capacitors. Their effects in the depletion regime are more complicated. For lightly doped substrates, reducing the diameters of the nanowires will not contribute to the capacitance density in the depletion regime (Table 3.2). However, for heavily doped substrates, reducing nanowire diameters will continue to improve capacitor performance down to diameters of about 70nm.

3.5 Polycrystalline silicon nanowire based capacitors

Having proved that nanowire-array capacitors can effectively increase the capacitance density in single crystal silicon wafers, we further demonstrated a fabrication process for deposited polycrystalline silicon films, so as to demonstrate that devices can be fabricated on top of the metallization stack or on other types of substrates.

We fabricated three types of polycrystalline silicon capacitors for comparison: planar and nanowire MOS capacitors with nanowire lengths of 550nm (Fig. 3.2c) and 660nm. As a proof of concept, polycrystalline silicon films were deposited on silicon wafers for convenience. The samples were then fabricated following the same process used for single crystal silicon devices, and their capacitance-voltage characteristics were subsequently measured, as shown in Fig. 3.18.

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As the polycrystalline silicon film was intrinsic, a doping step was also applied on the polycrystalline nanowires. The doping concentrations in the polycrystalline silicon nanowires were even higher than the single crystal nanowires discussed in previous sections, considering the high diffusivity of boron in polycrystalline silicon due to grain boundary diffusion. The polycrystalline silicon film deposited on the backside of the wafer during LPCVD was also doped using the same procedure, so that ohmic contact could be made to the bottom of the wafer for subsequent fabrication and characterization.

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Figure 3.18 CV curves at various AC frequencies for (a) a 100µm*100 µm polycrystalline planar capacitor; (b) a 100 µm *100 µm polycrystalline 550nm nanowire based capacitor. (c) a 100 µm *100 µm polycrystalline 660nm nanowire based capacitor. (d) Capacitance densities measured at 1kHz of these three types of devices versus the wire length.

The CV characteristics showed an enhanced capacitance density with the increase in the surface area achieved by using silicon nanowires. The 550nm nanowire device had a ~2 times increase in capacitance density compared to the planar device, while the 660nm nanowire device achieved an increase factor of 3, as can be seen in Fig. 3.18d. The theoretical increase compared to a perfectly planar substrate should be 3.4 and 3.9 for these two devices, respectively. The

124 discrepancy between the experimental data and theoretical prediction could be caused by two factors. First, the planar poly-Si we used had a very rough surface, so it was not a perfectly planar substrate (Fig. 3.2d). Second, the non-uniformity of the MACE process could lead to some variations in the wire lengths, which can be significant for these short polycrystalline silicon nanowires. We also noticed that the polycrystalline planar and nanowire devices here had similar

CV curve shapes to the single crystal Type IV devices (as shown in Fig. 3.12d). This is as expected because both the planar and nanowire devices were heavily doped due to the extra doping step.

However, large frequency dispersions were observed for poly-Si nanowire based devices, as seen in Figs. 3.18b and 3.18c, compared to Type IV single-crystalline device. This is because the polycrystalline nanowire device was built on lightly doped silicon wafers, while the Type IV single-crystalline device was fabricated on epi-wafers with a heavily doped bulk substrate. This further confirms our conclusion that the resistance from the bulk substrate dominates in the overall series resistance. Moreover, the frequency dispersion was further increased with increasing capacitance on long nanowires, as can be seen in Fig. 3.18c. Therefore, we have shown very similar capacitance density trends in polycrystalline silicon devices, which illustrates that this process can also be used to build high capacitance density MOS capacitors using polycrystalline silicon films.

3.6 Conclusion

In summary, we have developed a new process for fabrication of single crystal silicon nanowire array capacitors with well-defined device areas. The effect of the series resistance on device performance has been thoroughly studied through a comparison of various devices. The expected increase in capacitance density was observed for nanowire devices compared to planar

125 devices. We also found that in the current devices, for which contact to the silicon from the back of the wafer, the bulk resistance of the wafer dominates in defining the overall series resistance, and hence the frequency response under AC oscillations. We then theoretically quantified scaling of device performance with nanowire array period and length. Predictions from the proposed model are in good agreement with measured capacitance densities. In addition, we also found that the effect of nanowire diameter in the depletion regime is more complicated, and have verified that

180nm diameter nanowires in the Type II devices were fully depleted before inversion.

Finally, based on the fabrication process for single crystal silicon nanowire devices, we further developed a modified process for polycrystalline silicon nanowire capacitors. From their

CV characteristics, we concluded that polycrystalline silicon nanowire devices follow very similar trends as the single crystal devices. Therefore, the devices built in deposited films are not fundamentally different from those fabricated in single crystal wafers.

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127

Silicon Nanowire Based Supercapacitors

4.1 Introduction

Supercapacitors, also called electrochemical capacitors, have drawn more and more attention due to their high power density and long cycle life. They are promising devices for filling the gap between batteries and electrostatic capacitors. As demonstrated in the Ragone plot (i.e. plot of specific power vs. specific energy) in Fig. 4.1 [130], batteries generally have a large specific energy but low specific power, while electrostatic capacitors have large specific power but low specific energy. Supercapacitors, however, have a larger power density than batteries, and a larger energy density than electrostatic capacitors. Therefore, it is desirable to make a supercapacitor device with an optimized combination of these two properties.

Figure 4.1 Specific power versus specific energy for various energy storage devices [130].

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In recent years, the rapid growth of portable electronics has raised the demand for highly efficient solid state micro power systems. There has been a lot of effort in improving solid state micro supercapacitor performance by using novel electrode materials and structures. The most popular electrode materials so far are carbon or carbon composites [55, 131-136]. Though devices made with these materials reach high specific capacitances, on the order of F/cm2, they are made using methods that would be difficult to integrate with current chip manufacturing processes.

However, to further reduce the size of portable electronics it is desirable to make such solid state micro supercapacitors integrated with electronics on the same chip, using CMOS compatible processes. Therefore, silicon is an obvious candidate for an electrode material.

There has been much research to achieve high performance electric double layer type supercapacitors using silicon based materials. Various silicon structures synthesized using the VLS method have been used to increase the electrode surface area for high electrochemical performance

[56-61]. However, these studies tested electrode performance using a three-electrode setup in an ionic liquid electrolyte for stable electrochemical performance. This approach is only able to achieve a specific capacitance on the order of tens of µF/cm2, which is one order of magnitude higher than planar silicon electrodes. Silicon nanostructures including porous silicon generated using anodization [137] and porous silicon nanowires etched using metal-assisted chemical etching

[62, 138] showed capacitance densities as high as 325 mF/cm2, due to their high surface area.

However, the electrodes were only tested in aqueous or ionic liquid electrolytes and passivation layers such as SiC [138] or an ultrathin carbon sheath [62, 137] were necessary to achieve stable performance. These coating processes require a temperature of 800-900℃, which significantly exceeds the maxim CMOS processing once device structures have been fabricated (~400℃).

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Moreover, no studies have been carried out implementing such extremely high aspect porous silicon nanostructures in solid electrolytes, where mechanical failure is very likely to occur.

As an alternative to rely only on the enlarged silicon surface area, silicon nanostructures can also be used as scaffolds to make pseudocapacitive type electrodes. In this case, the challenge of obtaining high capacitance densities is solved in two steps. The first step is to introduce three dimensional structures to increase the effective silicon surface area per footprint. The second step is to modify the silicon surfaces with pseudocapacitive materials to further enhance supercapacitor performance. A variety of materials have been studied, such as NiO [139], polypyrrole polymer

[140] and RuO2 [76, 77]to achieve better performance than bare silicon electrodes. The criteria in choosing the appropriate surface coatings/modifications are that they should lead to high electrochemical performance and that they can be created through a CMOS compatible technique.

Considering these requirements, ruthenium oxide stands out due to its high gravimetric capacity

[63], good conductivity of 37 µΩ∙cm [64], and good cyclability. Moreover, atomic layer deposition

(ALD) of ruthenium oxide [141] is preferred over solution based methods [76]. Warren et al. demonstrated a 4800 times increase in the specific capacitance of porous silicon electrodes by additional ALD coating of RuO2 [77]. However, all these pseducapacitive type silicon based electrodes were studied only in liquid electrolytes.

There have also been some reports on RuO2 based solid state on-chip supercapacitors, where planar silicon is used as the substrate and does not contribute to the supercapacitor performance. For example, Yoon et al. demonstrated a solid state on-chip supercapacitor with the

2 structure of RuO2/LiPON/RuO2, which achieved a specific capacitance of 6.4mF/cm [142]. In their work, a large amount of RuO2 (200nm for each electrode) was deposited by reactive sputtering.

Gnerlich et al. also demonstrated an on-chip micro-supercapacitor with a solid electrolyte using 130

ALD RuO2 coating on virus templated electrodes, which yielded a device capacitance around

0.6mF/cm2 [79]. They also reported recently that a specific capacitance as high as 203mF/cm2 can be achieved on the same virus template with a solid electrolyte [75], at the expense of further sacrificing the CMOS compatibility of the process by depositing RuO2 from a strong oxidant RuO4 solution. However, such devices are limited in either the high material/process cost or involvement of an irregular virus template, which can be solved by using silicon nanostructures directly as scaffolds for RuO2 deposition.

Building on earlier studies, in the research to be reported here, Si nanowire array electrodes were coated with RuO2 using ALD and they were tested in 1M sodium sulfate aqueous electrolyte using a three-electrode setup. Various samples were analyzed to determine the dependence of the electrode performance on the silicon nanostructure geometry, as well as the ruthenium oxide loading. Finally, a symmetrical solid state full supercapacitor device was made based on the composite electrodes and a polymer-based solid electrolyte, as shown in Fig. 4.2.

Figure 4.2 Schematic of a symmetrical solid state supercapacitor. 131

4.2 Materials and experiment

4.2.1 Electrode fabrication

The silicon nanowire arrays were fabricated using MAAE of (100) heavily doped n-type silicon wafers using the procedure described in Chapter 3, with the contact through the Au mesh.

Then ruthenium oxide was deposited using ALD using precursors of Ru(EtCp)2 kept at 110℃ and

O2 kept at room temperature in a commercial ALD chamber for the target cycles. The growth temperature was kept at 290℃. The morphologies of the samples were routinely observed using a

Zeiss/Leo Gemini 982 SEM. In addition transmission electron microscopy and Energy-dispersive

X-ray spectroscopy (EDX) were sometimes carried out using a JEOL 2010 FEG Analytical

Electron Microscope. X-Ray diffraction (XRD) tests were performed using a Panalytical

Multipurpose Diffractometer. X-ray photoelectron spectroscopy (XPS) measurements were made using a PHI Versaprobe II X-ray Photoelectron Spectrometer.

4.2.2 Solid state supercapacitor fabrication

Polyvinyl alcohol powder (PVA, Molecular weight~125000) was purchased from Sigma-

Aldrich. The solid PVA/H2SO4 electrolyte was prepared by dissolving PVA (1 g) into 10 mL deionized water. One gram of H2SO4 was then added into the solution. This aqueous solution was then vigorously stirred in a water bath at 85 °C and then cooled to room temperature.

The as-prepared electrodes were cut into 1cm by 1cm pieces, and 10nm Ti and 100nm Al was evaporated by e-beam as the back contact. The polymer-based gel-electrolyte was spin-coated onto the substrate at 1K rpm speed and baked for 10min at 45°C. Each chip was cut into halves using a diamond pen, resulting in two samples with an area of 0.5cm by 1cm. Another layer of electrolyte was then spin-coated on one of the electrodes at 3K rpm speed, followed by stacking

132 of the other sample on top of it. Finally, the symmetrical device was baked in an oven at 45°C for

30min to fully solidify the electrolyte. Pt wires were bonded as wiring to the backside Al using silver paste.

4.2.3 Electrochemical testing

The electrodes were first tested using a three-electrode setup in 1M sodium sulfate aqueous solution with a potentiostat, as shown in Fig. 4.3. A piece of Al foil was placed between heavily doped n-type silicon and the bottom copper plate to make ohmic contact. The reference electrode was a commercial saturated Ag/AgCl electrode and the counter electrode was a platinum mesh.

Repeated cyclic voltammetry and galvanostatic charge-discharge measurements were carried out on all samples. For cyclic voltammetry tests in 1M Na2SO4 aqueous electrolyte, the potential was scanned at 200mV/s, 100mV/s, 50mV/s, 20mV/s and 5mV/s between -0.2V and 0.8V vs. Ag/AgCl, respectively. The charge-discharge experiments were carried out at different current densities and the cut-off voltage range was -0.2V to 0.8V vs. Ag/AgCl. Electrochemical impedance spectroscopy (EIS) was performed across a frequency range of 7MHz and 5mHz with a potential amplitude of 10mV.

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Figure 4.3 Electrochemical cell set up for three electrode test in aqueous electrolyte.

For solid state supercapacitors made with heavily doped n-type silicon, Pt wires were bonded as wiring to the Al using silver paste. The cell was tested with two contacts using cyclic voltammetry between -0.5V and 0.5V. The charge-discharge tests were carried out in the voltage window 0V to 1V. Finally, the cell stability was tested by monitoring charge and discharge at a constant current density for a large number of cycles.

4.3 ALD of RuO2 and characterization

The main electrode performance study was carried out using the aqueous electrolyte and focused on the effects of ALD loading effect and nanowire array geometry. Three different types of heavily doped n-type substrates were studied; planar Si substrates, and silicon nanowire arrays with fixed diameters (180nm), spacings (220nm) and lengths of 1.8 or 6.4μm, as shown in Fig. 4.4.

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These samples will be referred to as planar Si, SiNW1, and SiNW2, respectively, in the following discussions.

Figure 4.4 SEM images of silicon nanowire arrays before ALD that are (a) 1.8μm tall and (b) 6.4μm tall.

The samples then went through ALD chamber for RuO2 deposition. To analyze the effect of the number of ALD cycles on the electrochemical performance, two batches of the three types of samples were subjected to 150 and 400 ALD cycles. The cycle numbers will be added to the electrode description to distinguish between the two batches. For example, SiNW1-150cyc represents the electrodes composed of 1.8μm tall Si NW arrays and coated using 150 ALD cycles.

TEM analysis showed that a sparse coating of nanoparticles was achieved after 150 ALD cycles, as can be seen in Fig. 4.5a. When the cycle number was increased to 400, nanoparticles impinged into each other, forming a relatively continuous coating on the surfaces of the nanowires, as shown in Fig.4.5b. TEM imaging at different locations on the 6.4μm long nanowires (Fig. 4.5c-e) indicated that the coating was relatively uniform from the top to the bottom of the nanowires.

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Figure 4.5 TEM images of (a) a SiNW1-150cyc sample and (b) a SiNW2-400cyc sample. Higher magnification TEM images of the (c) top, (d) middle, and (e) bottom of a SiNW2-400cyc nanowire. (f) A HRTEM image of a nanoparticle on a SiNW2-400cyc nanowire.

HRTEM showed that most of crystalline nanoparticles had lattice constants corresponding to Ru, as shown in Fig. 4.5f. We also did EDX on the sample shown in Fig. 4.5b to confirm the elemental composition of the coating, as shown in Fig. 4.6. We found that a large amount of ruthenium and oxygen were detected (Fig. 4.6c, d and e). The quantitative ratio between ruthenium and oxygen was much higher than 1:2, the atomic ratio of the desired RuO2 phase. This is consistent with the HRTEM analysis that most crystallites are elemental Ru.

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Figure 4.6 EDX result for the 6.4µm nanowires after 400 ALD cycles. (a) TEM image of a collection of nanowires, and (c), (d), and (e) elemental mapping of silicon, oxygen and ruthenium, respectively. (b) Summary of the quantitative results on the percentage of these elements.

XRD was also used to confirm the crystalline phase of the ALD deposited materials on all samples, as shown in Fig. 4.7. XRD measurements were carried out on planar silicon substrates without ALD and various samples that went through the ALD process. The new peaks that appeared for the samples after ALD coating corresponded to Ru metal and no peaks were associated with the crystalline RuO2 phase.

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Figure 4.7 XRD of various samples with and without the ALD process.

Though XRD measurements revealed that no crystalline RuO2 was deposited during the

ALD process, it was still possible that amorphous ruthenium oxide existed in the samples.

Therefore, we performed semi-quantitative XPS analysis on the SiNW2-150cyc electrode, as shown in Fig. 4.8. The asymmetric peaks indicate the presence of Ru with multiple oxidation states.

The deconvolution analysis reveals dominant peaks at ~ 280.1 and 284.2 eV that correspond to metallic Ru 3d5/2 and 3d3/2 doublet peaks, and additional peaks at the positions ~ 1 eV higher with respect to the metallic Ru, which arise from RuO2 [143]. Quantification using the metallic and oxide component spectral fits gives ~40% oxide phase and ~60% metallic phase in this 150-cycle coated sample.

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Figure 4.8 XPS spectra and deconvolution analysis (Ru 3d) showing the presence of ruthenium oxide.

By further optimizing the ALD recipe, it should be possible to fully eliminate the ruthenium metal phase. However, while previous researchers have also reported deposition mostly Ru metal instead of pure RuO2 using ALD [77], they still observed excellent electrochemical activity from the deposited material. Therefore, we proceeded with the as-generated electrodes to study the effect of the coated material on three dimensional silicon nanowire arrays.

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4.4 Electrochemical test on electrodes in aqueous solution.

As described previously, both cyclic voltammetry and charge-discharge tests were carried out on the samples. The specific capacitance was extracted from cyclic voltammetry using Eq.

(4.1). In this equation, j represents the current density, V is the range of potentials scanned, s is the scan rate, and C is the areal specific capacitance,

jdV C   . (4.1) 2Vs

The capacitance can also be determined from the charge-discharge curves according to Eq.

(4.3). Here, E is the specific energy, j represents the constant discharge current density, V is the discharge potential window and C is the specific capacitance.

1 E CV2 jVdt , (4.2) 2 

2 jVdt  C  . (4.3) V 2

4.4.1 Cyclic Voltammetry of 150 ALD cycles electrodes

As the characterization showed that the materials deposited during ALD were a mixture of ruthenium metal and ruthenium oxide, we will use RuOx to represent the ALD coated material in the following discussions. We first tested the batch of heavily doped n-type samples with 150 ALD cycles of RuOx, as well as a planar bare silicon sample without RuOx as a control. The cyclic voltammetry of these samples are shown in Fig. 4.9.

140

Figure 4.9 Cyclic Voltammetry curves for heavily doped n-type samples coated using 150 ALD cycles: (a) planar Si w/o RuOx; (b) planar Si-150cyc RuOx; (c) SiNW1-150cyc RuOx; (d) SiNW2-150cyc RuOx.

For this batch of electrodes, the cyclic voltammetry curves changed shapes with the aspect ratio of nanowires used. They were more tilted toward the diagonal direction at high scan rates for longer silicon nanowires used. Some local broad peaks showed up for the silicon nanowire based electrodes in Fig. 4.9 (c) and (d), while these were not observed for the planar uncoated silicon electrode, as shown in Fig. 4.9 (b). The tilting of the curves is known to be a result of increasing resistance. To analyze the influence of resistance loss, we carried out EIS to determine the resistance in this batch of devices, giving the results shown in Fig. 4.10.

141

Figure 4.10 EIS of bare planar Si and various samples coated using 150 ALD cycles. The inset focuses on the high frequency region.

In the impedance spectroscopy, the first intercept with the x axis at high frequency is the equivalent series resistance (ESR), including the resistance of the electrode and the contact resistance between the electrode and the current collector. The semicircle at lower frequencies is related to transfer of electrochemically related charges, and its diameter represents this charge transfer resistance. It is clear from Fig. 4.10 that longer silicon nanowire electrodes show a larger charge transfer resistance. We believe this increasing resistance is the result of sparse coating of

RuOx after 150 ALD cycles, as evidenced from the TEM images in Fig. 4.5. We have also drawn a schematic diagram showing the charge transfer process in these samples, as shown in Fig. 4.11.

As the electrical contact is made through the back of the silicon wafer, the electrons must travel all the way along the silicon nanowires to be collected. Considering the small diameter of the

142 nanowires, as well as their porosity generated during the wet etching step, they are probably not good electron conducting paths [118]. Moreover, the longer the nanowires are, the higher the resistance would be. To avoid this resistance, a continuous current collecting layer should be deposited before deposition of the RuOx layer in the future.

Figure 4.11 A schematic diagram of charge transfer in silicon nanowire electrodes coated with RuOx using

150 ALD cycles. The orange particles are the RuOx.

As can be seen in Figs. 4.5(a) and 4.11, more silicon surface is exposed to the electrolyte with increasing nanowire length for 150 ALD cycle samples. It is possible that the CV shape deviation from ideal squares and the appearance of local broad peaks in Fig. 4.9 (c) and (d) are associated with presence of exposed silicon surface. Therefore, we did cyclic voltammetry tests on a bare silicon nanowire sample with 1µm wire length, shown in Fig. 4. 12. The large increase of the current densities towards the +0.8V vs. Ag/AgCl is due to the oxidation of the silicon surface

[138]. A comparison between Fig. 4.9 (c), (d) and Fig 4.12 showed that the CV curves of 150 ALD cycle-coated silicon nanowire electrodes evolve toward the shape of observed for the bare silicon nanowires. This indicates that the amount of silicon surface that is not covered by RuOx plays a significant role in the overall electrode performance.

143

Figure 4.12 Cyclic Voltammetry curves for a bare heavily doped n-type silicon nanowire sample.

In summary, 150 cycle coating with the ALD recipe that was used yielded a sparse RuOx coating on silicon nanowires, leading to an increasingly high resistance to the collection of electrochemical charges with increasing nanowire lengths. Moreover, this sparse coating also led to a large amount of exposed silicon surface that went through irreversible reactions in the aqueous electrolyte. Therefore, these were not ideal electrodes for supercapacitor applications.

4.4.2 Cyclic Voltammetry of 400 ALD cycles batch electrodes

We then tested the silicon nanowire samples coated with RuOx using 400 ALD cycles. The cyclic voltammetry results for these samples are shown in Fig. 4.13.

144

Figure 4.13 Cyclic Voltammetry curves for various types of heavily doped n-type samples: (a) planar Si-

400cyc RuOx; (b) SiNW1-400cyc RuOx; (c) SiNW2-400cyc RuOx.

These samples showed more rectangular curves than 150 ALD cycle samples, even for the

6.4µm long silicon nanowire sample. From the EIS data shown in Fig. 4.14, no semicircles that corresponded to transfer of electrochemically generated charges were observed in all samples, indicating that the charge transfer resistance was independent of the nanowire geometry. The slightly larger resistance in the SiNW2-400cyc RuOx sample is probably related to the porous layer underneath the SiNWs generated during MAAE, as reported previously for etching of heavily doped substrates [144].

145

Figure 4.14 EIS of bare planar Si and various samples coated with RuOx using 400 ALD cycles. The inset focuses on the high frequency region.

The observed difference in electrochemical performance between 150 cycle and 400 cycle samples difference can be understood by considering the much more conformal and continuous coating of RuOx nanoparticles on the 400 cycle samples, as shown in Fig. 4. 6. Even on the longest silicon nanowires we studied, the coating was very uniform from the top to the bottom of the nanowires. Two things should be noted. First, the continuous coating prevented the exposure of the silicon surface to the electrolyte. Second, the continuous coating provided a lower resistance electron current path, as shown in the schematic below in Fig. 4.15. The electrons, in this case, did not go through the narrow porous silicon nanowires to contribute to the capacitance. The coating acted both as the active electrode material and the current collector. Therefore, the resistance did

146 not increase when the aspect ratio of the silicon nanowires was increased. Moreover, the characterization discussed earlier revealed that a large portion of the material deposited using ALD was Ru metal, which would further reduce the resistance of the nanowire coating.

Figure 4.15 A schematic diagram of charge transfer in silicon nanowire based electrodes coated with RuOx using 400 ALD cycles. The orange particles are the RuOx.

One issue noted for the 400 cycle samples was the relatively sharp peak around 0.2V, as can be seen in Fig. 4.13. This peak was also seen in the Planar Si-150cyc RuOx electrode in Fig.

4.9 (b). This peak is probably associated with the oxidation of Ru species (e.g. Ru/Ru(II), +0.255V) or even contaminations during the ALD process. However, we are not able to identify the reactions associated with this peak.

4.4.3 Scalability of specific capacitance based on cyclic voltammetry

The extracted specific capacitance versus the scan rates for all seven samples discussion in the previous two sections is plotted in Fig. 4.16. It was observed that the specific capacitance decreased with increasing scan rate in all samples. This was expected because low scan rates ensured enough time for charge to be fully stored or released. Even 150 ALD cycles of RuOx resulted in a specific capacitance increase of over two magnitudes compared to the bare planar silicon substrates. This demonstrates that the material deposited with our ALD recipe was 147 electrochemically active. The highest specific capacitance, about 19mF/cm2, was achieved with the SiNW2-400cyc RuOx sample.

Figure 4.16 Specific capacitance versus scan rate for various types of heavily doped n-type samples.

We next consider the scalability of the specific capacitance with respect to the geometry of the nanowire arrays. For simplicity, we assume a conformal coating of ruthenium oxide film on the silicon nanowire array. The specific capacitance is calculated using Eq. (4.4) for planar electrodes and Eq. (4.5) for nanowire-based electrodes.

Cplanar t R R C R A , (4.4)

A C t  al   C  t  C A , (4.5) nw Rp2 R R R R R

Cnw al Ratio  2 1. (4.6) Cpplanar

148

In these equations, tR is the thickness of the RuO2 film, R is the density of RuO2, CR is the gravimetric specific capacitance of RuO2, A is the chip area, a is the diameter of the initial silicon nanowire diameter, l is the silicon nanowire length, and p is the period of the nanowire array.

At slow scan rates, slow electrochemical processes can also contribute to the electrode performance. Therefore, we chose to compare the scalability of the specific capacitance at the slowest test scan rate. The experimental data and the theoretical increase ratios for the three samples with 150 and 400 ALD cycles extracted from 5mV/s curves are listed in Table 4.1. As shown in this table, the experimental increase ratio matched nicely with the theoretical ratio, thus demonstrating the scalability of the specific capacitance performance with to the aspect ratio of nanowire arrays.

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Table 4.1 Scalability of specific capacitance with the nanowire array geometry. Si scaffolds Specific capacitance at Experimental Theoretical

5mV/s (µF/cm2) increase ratio increase ratio

Planar 497 1 1

150cyc SiNW1 (1.8µm) 3951 7.9 7.4

ALD SiNW2 (6.4µm) 11111 22.4 23.6

Planar 712 1 1

400cyc SiNW1 (1.8µm) 5729 8.0 7.4

ALD SiNW2 (6.4µm) 18815 26.4 23.6

We also analyzed the specific capacitance dependence on the ALD cycle numbers, and the results are summarized in Table 4.2. In general, the samples with 400 ALD cycles showed an improvement in capacitance density compared to those with 150 ALD cycles. However, the results do not scale with the ALD cycle numbers. The cyclic voltammetry tests showed an increase by a factor of 1.4 for heavily doped n-type planar electrodes at 5mV/s when the ALD cycle number was increased from 150 to 400. One possible explanation was that the electrochemical performance mainly came from the electrode surface layers, and the effective surface area did not scale 1:1 with the cycle number. Similar behavior and explanation have been reported on electrodeposited ruthenium oxide film electrodes in the literature [145]. As discussed earlier, the performance degradation in nanowire-based electrodes with increasing scan rate was worse for the 150 cycle samples than the 400 cycle samples. This can also be seen in the results in Table 4.2.

150

Table 4.2 Effects of ALD cycle number on electrode performance in cyclic voltammetry. Sample type Scan rate 150cyc specific 400cyc specific Ratio

(mV/s) capacitance (µF/cm2) capacitance (µF/cm2)

5 497 712 1.43

20 370 524 1.42

Planar 50 308 401 1.30

100 268 350 1.31

200 237 308 1.30

5 3951 5729 1.45

20 2380 3979 1.67

SiNW1 (1.8µm) 50 1718 3185 1.85

100 1265 2710 2.14

200 870 2342 2.69

5 11111 18815 1.69

20 5866 12926 2.20

SiNW2 (6.4µm) 50 3986 9699 2.43

100 3011 7561 2.51

200 2144 5760 2.68

4.4.4 Charge-discharge test on 400 ALD cycle electrodes

As discussed earlier, the 400 ALD cycles samples are more ideal electrode materials.

Therefore, we also did the galvanostatic charge-discharge measurements on these samples, with the results shown in Fig. 4.17. Planar Si electrodes without ALD RuOx was also tested for comparisons.

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Figure 4.17 Charge-discharge curves at various current densities for various types of heavily doped n-type samples: (a) planar Si without RuOx; (b) planar Si-400cyc RuOx; (c) SiNW1-400cyc RuOx; (d) SiNW2-

2 400cyc RuOx. The legends show the current densities with units of mA/cm .

We used the integration method to calculate the specific capacitance so that we would not overestimate the electrode performance. The extracted specific capacitance values versus the discharge current densities are plotted in Fig. 4.18 for all four samples. The specific capacitance decreased with increasing current densities for all three RuOx-coated samples. This was because at high current densities, there was inadequate time for ion diffusion to all the active electrode surface. Within the range of current densities we tested, the planar Si-400cyc RuOx showed a more

152 than two magnitudes increase in the specific capacitance. SiNW1-400cyc RuOx also showed another 8 times increase over planar Si-400cyc RuOx. SiNW2-400cyc RuOx, the samples with the longest nanowires, showed roughly 40 times higher specific capacitance over planar Si-400cyc

RuOx.

Figure 4.18 Specific capacitance at various charge-discharge current densities for various types of heavily doped n-type samples: (a) planar Si without RuOx; (b) planar Si-400cyc RuOx; (c) SiNW1-400cyc RuOx;

(d) SiNW2-400cyc RuOx.

4.5 Solid state supercapacitor

4.5.1 Cyclic voltammetry of 400 ALD cycles devices

Electrochemical studies in the aqueous electrolyte revealed that electrodes with 400 ALD cycles were better electrodes for supercapacitor applications. Therefore, we made symmetrical

153 solid state supercapacitors on these electrodes as shown in the schematic diagram (Fig. 4.2), following the method described in section 4.2.2. Cyclic voltammetry was carried out between -

0.5V to 0.5V, giving the results shown in Fig. 4.19.

Figure 4.19 Cyclic voltammetry of symmetrical solid state devices made with various electrodes, (a) planar

Si w/o RuOx, (b) planar Si-400cyc RuOx; (c) SiNW1-400cyc RuOx; (d) SiNW2-400cyc RuOx.

Specific capacitance values were extracted from CV curves and are shown in Fig. 4.20.

The highest specific capacitance of the complete solid state device was obtained using SiNW2-

2 400cyc RuOx samples, with a value of 6.5mF/cm . In the solid state device, ALD coatings on planar Si also yielded a capacitance enhancement of more than two magnitudes compared with

154 bare Si. The specific capacitance also scaled with the surface area of the silicon scaffolds. At the slowest scan rate, 2mV/s, the SiNW1-400cyc RuOx-based device showed an approximately 5.5 times increase over the planar Si-400cyc RuOx based device, and SiNW2-400cyc RuOx-based device showed a 15.4 times increase over the planar Si-400cyc RuOx-based device. The weaker scaling in the solid electrolyte than seen in the aqueous electrolyte might be due to either the imperfect filling of the polymer-based electrolyte between the spacings of the nanowires, or due to damage to the nanowires, such as detachment from the substrate, during spin coating and baking of the electrolyte.

Figure 4.20 Specific capacitance of symmetrical solid state devices made with various electrodes, including planar Si w/o RuOx, planar Si-400cyc RuOx, SiNW1-400cyc RuOx and SiNW2-400cyc RuOx at various scan rates.

155

4.5.2 Charge-discharge test of 400 ALD cycle devices

The symmetrical solid state supercapacitors were tested through galvanostatic charge- discharge experiments at various current densities between 0V and 1V. The charge-discharge curves are shown in Fig. 4.21. RuOx-modified electrodes showed nearly symmetrical charge/discharge curves at all current densities.

Figure 4.21 Galvanostatic charge and discharge curves for symmetrical devices with various electrodes over a range of discharge rates, (a) planar Si w/o RuOx, (b) planar Si-400cyc RuOx; (c) SiNW1-400cyc

2 RuOx; (d) SiNW2-400cyc RuOx. The units of the legends are mA/cm .

156

The specific capacitance was calculated from discharge curves (Fig. 4. 22). SiNW2-400cyc

2 RuOx showed the highest specific capacitance, 2.9mF/cm . Similar to the values extracted from

CV measurements, the 400 ALD cycle devices showed an increase of over two orders of magnitude in the specific capacitance in charge-discharge conditions compared to uncoated planar Si electrodes. Moreover, when tested at 0.08mA/cm, an additional 4 times increase and 15 times increase in the specific capacitance was achieved by SiNW1-400cyc RuOx and SiNW2-400cyc

RuOx-based devices, respectively, compared to planar Si-400cyc RuOx deivces.

Figure 4.22 Specific capacitance calculated from charge and discharge curves for symmetrical devices with various electrodes over a range of discharge rates, including planar Si w/o RuOx, planar Si-400cyc RuOx,

SiNW1-400cyc RuOx, and SiNW2-400cyc RuOx.

157

As discussed earlier, long cycle life is another key advantage of supercapacitors. We also tested the stability of the supercapacitor device based on SiNW2-400cyc RuOx electrodes, which had the highest specific capacitance among all the devices we fabricated. The stability test was conducted by charging and discharging the device at a constant current density of 0.4mA/cm2 in a potential window from 0V to 1V. Fig. 4.23 shows the specific capacitance as a function of charge- discharge cycle number for this device. A capacitance retention of approximately 92% was obtained after 10000 charge-discharge cycles, indicating good stability of the device.

Figure 4.23 The specific capacitance versus charge-discharge cycle number for the solid state supercapacitor device based on SiNW2-400cyc RuOx electrodes at a discharge current density of 0.4mA/cm2.

158

4.6 Comparison with solid state supercapacitors made using other methods

We have successfully fabricated solid state on-chip supercapacitors with a specific capacitance as high as 6.5 mF/cm2 when measured at a scan rate of 2mV/s. In Figure 4.24, we compare this performance with other results from the literature, including results for MOS capacitors as described in Chapter 3, state of the art micro trench capacitors [47, 51, 52], and other types of solid state supercapacitors for on-chip applications. The supercapacitors demonstrated in this work showed a more than two order of magnitude higher specific capacitance than the MOS capacitors we fabricated or state-of-the-art micro trench capacitors. The specific capacitance is also comparable to representative work on carbon based solid state supercapacitors [55, 131, 135].

Finally, our devices are also comparable with other on-chip solid state supercapacitors based on

RuO2 [75, 79, 142]. Though higher specific capacitances were achieved in reference 6 [131] and 9

[75], the active electrode material is deposited through a solution-based approach, which is a less preferable method for integration with current chip manufacturing processes compared to ALD deposition.

159

Figure 4.24 A comparison chart of solid state capacitors including our nanowire based MOS capacitors; state-of-the art micro trench capacitors as reported in Ref. 1 [47], Ref. 2 [51],and Ref. 3 [52]; carbon-based solid state on-chip supercapacitors from reference 4 [135], 5 [55], and 6 [131], RuO2 based solid state on- chip supercapacitor from reference 7 [79], reference 8 [142], reference 9 [75] and our solid state on-chip supercapacitors based on Si-RuOx composite electrodes.

A more detailed comparison between three on-chip solid state supercapacitors based on

RuOx generated by CMOS compatible thin-film deposition techniques is shown in Fig. 4.25a. The specific capacitance is normalized by the thickness of the RuOx for a fair comparison, as the film thickness represents the material and process cost of the thin film deposition process. In our work, the 400 ALD cycle process yields an approximately 30nm thick RuOx layer, which results in a

2 normalized specific capacitance as high as 217mF/cm per µm of RuOx. This is better than reported

2 for device based on ALD RuO2 coatings on virus templated electrodes (19.3mF/cm per µm thick

160

2 RuOx) [79] (reference 7), and on-chip devices made using sputtered RuO2 (32mF/cm per µm thick

RuOx) [142] (reference 8).

For energy storage purposes, high specific energy and high power are desired. These can be calculated using Eq. (4.7) and Eq. (4.8) below.

1 E CV 2 , (4.7) 2

E P  . (4.8) t

In these equations, C is the specific capacitance extracted from galvanostatic charge-discharge curves, V is the voltage window, and t is the discharge time. Due to the lack of information in cited literature shown in Fig. 4.25a, a Ragone plot of the specific energy versus the specific power was only plotted with devices made in this work, as shown in Fig. 4.25b. Within the range we tested, the energy densities drop slightly with increasing power for each device. It is also clear that the enlarged electrode surface area from the incorporation of high aspect ratio silicon nanowires lead to more than a one order of magnitude higher specific energy, without sacrificing the specific power compared with a planar Si-400cyc device.

161

Figure 4.25 (a) A comparison chart of specific capacitance normalized by the thickness of RuOx deposited in Si CMOS compatible thin film deposition techniques for a variety of solid state on-chip supercapacitors including this work, ALD RuOx [79] and sputter deposited RuOx [142]. (b) Areal Ragone plot of four types of solid state devices discussed in this chapter.

4.7 Conclusions

In this work, an ALD process for deposition of RuOx was developed to modify silicon nanowire arrays generated using the MAAE process. We found that a relatively continuous RuOx coating was necessary to passivate the silicon surfaces and to reduce the effect of electrode resistance on electrochemical performance. A continuous coating could only be achieved with

ALD cycle numbers greater than 400. A specific capacitance of 19mF/cm2 was achieved with

SiNW2-400cyc RuOx electrodes scanned at 5mV/s in an aqueous electrolyte. We showed that the specific capacitance measured from both cyclic voltammetry and galvanostatic charge-discharge tests scaled with the aspect ratio of silicon nanowire scaffolds in the aqueous electrolyte.

We then used the high-performance 400 ALD cycle silicon nanowire array electrodes to make solid state symmetrical on-chip supercapacitors. The entire fabrication process was CMOS

162 compatible and the highest temperature used was 290℃ during the ALD step. A specific capacitance of 6.5mF/cm2 was been achieved at a scan rate of 2mV/s, which is comparable with published results on other types of solid state supercapacitors. The performance of our Si nanowire solid state capacitors can be improved by decreasing the nanowire spacing and increasing the nanowire length. Use of thicker ALD films, as in the case of devices described in the literature would also likely lead to improved performance, but this would lead to an increased material and process time cost. A notable advantage of our device is the use of silicon as the starting material, so that the device can be made directly on-chip. Therefore, there is no need for extra steps to attach the supercapacitors to the chip used for information processing. Our nanowire devices also exhibit a good stability over 10000 cycles of charge and discharge. In addition, they show a high specific energy of 0.4µWh/cm2 at 0.03mW/cm2, and 0.32µWh/cm2 at 0.17mW/cm2. The higher specific energy is achieved over planar devices without a drop in the specific power.

163

Summary and Future Work

5.1 Summary

Though discovered only a few decades ago, metal-assisted chemical etching (MACE) has generated a significant amount of interest as a tool for nanostructuring silicon and other semiconductors for use in microelectronic devices and circuits, and in other microsystems. In the work described in this thesis, MACE was investigated as a simple and controllable method for fabricating a variety of silicon nanostructures, mainly ordered array of silicon nanowires. Basic studies of the mechanisms of MACE and development of new related processes were carried out.

In addition, processes for fabrication of high capacitance density nanowire-based on-chip capacitors were developed, and the fabricated devices were characterized and their performance was analyzed through the development of device models.

In Chapter 2, a new method for metal-assisted etching of silicon, metal-assisted anodic etching (MAAE), was described. Different types of silicon were coated with a perforated Au films and nanowires were etched in HF/H2O2 solutions. A Pt wire was used as the cathode while the anodic contact was made through either the patterned Au film or the opposite side of the Si wafer.

The energy band diagrams of the Au/Si and etchant/Si interfaces were analyzed. We found that when the anodic contact was made through p-type Si, regular anodic etching due to electronic hole injection leads to formation of porous silicon simultaneously with metal assisted anodic etching.

When the anodic contact was made through n-type Si, generation of electronic holes through processes such as impact ionization and tunneling-assisted surface generation was required for etching. These results clarify the linked roles of electrical and chemical processes that occur during electrochemical etching of Si. In addition, it was found that metal assisted anodic etching of Si

164 with the anodic contact made through the patterned Au film essentially reproduces the phenomenology of metal-assisted chemical etching (MACE). This provided new insight into the mechanisms of MACE. The new technique MAAE can be carried out without needing an oxidant

(e.g. H2O2) in the etching solution.

In Chapter 3, we described the development of a fabrication process for on-chip MOS capacitors with well-defined sizes, based on single crystal and polycrystalline Si nanowire arrays generated using MACE or MAAE. We demonstrated that under AC charging, the capacitance density of nanowire capacitors could be increased roughly in agreement with the scaling model developed for capacitors made in single crystal substrates and polycrystalline layers on single crystal substrates. Nanowires made from heavily doped silicon in MACE process are nano-porous.

We developed processes for doping non-porous nanowires made in lightly doped silicon, so that the effects of nanowire and substrate resistance on the AC performance of nanowire capacitors could be investigated. Of specific interest was the effects of series resistance on effective capacitance densities under AC operations at various frequencies. We found that the bulk resistance (the wafer resistance) had a dominant effect on the device performance under AC conditions in our devices. Similar results were found for both single crystal and polycrstalline nanowire arrays. Through this work we established that silicon nanowire arrays could be used to increase the capacitance density of capacitors under AC charging, and that nanowire array capacitors could be implemented in polycrystalline silicon films as well as in single crystal substrates.

In Chapter 4, we demonstrated fabrication of on-chip solid state supercapacitors based on silicon nanowire arrays obtained using MAAE. We successfully developed an ALD process to coat silicon nanowires with RuO2. RuO2 was chosen because it can store charges not only through 165 double layer formation but also through redox reactions. Though the material deposited was a mixture of crystalline metallic Ru and amorphous RuO2 according to XRD and XPS analyses, the electrodes still showed high electrochemical performance. Electrochemical tests with a three electrode set up in aqueous electrolyte confirmed the scalability of the specific capacitance with respect to the nanowire array geometry. An increase in the specific capacitance of approximately

40% was found when the number of ALD cycles was increased from 150 to 400 on planar Si electrodes. The highest specific capacitance observed in the aqueous electrolyte was around

19mF/cm2. Through electrochemical tests and electron microscopy, we found that a high ALD cycle number was necessary to form a continuous layer for conducting electrons. Symmetrical full solid state supercapacitor devices were made with a variety of silicon electrodes coated with ALD

400-cycle RuO2. We also demonstrated the scalability of solid state device performance with respect to the aspect ratio of silicon nanostructures. The highest specific capacitance, 6.5mF/cm2, was achieved in devices with the longest silicon nanowire based electrodes. This value is comparable to the best reported performance achieved with solid state supercapacitors made by others, based on the use of structures such as carbon nanotube carpets and virus assembled electrodes. The high specific capacitance we obtained was achieved without sacrificing the power performance compared to planar devices. Our device also retained 92% capacitance after 10000 charge-discharge cycles at 0.4mA/cm2. Importantly, our high performance nanowire supercapacitors were fabricated through CMOS compatible processes.

5.2 Future work

The research described in this thesis has provided a systematic study on the fundamentals of the use of metal-assisted wet etching to form silicon nanowire arrays, as well as the application 166 of these arrays in two types of capacitors. This provides the foundation for many possible future research directions. Here, we give some examples.

In the MAAE studies described in Chapter 2, the analysis of the energy band diagrams of the interfaces in the etching system provided us a new understanding of metal assisted wet etching of silicon. Since no oxidant was used in MAAE, it might be possible to extend this approach to etching of other semiconductor materials such as Ge, which is not stable with the presence in most aqueous oxidant solutions.

The analysis of the ALD process for coating silicon nanowires with RuOx described in

Chapter 4 suggests paths to improved supercapacitor performances. Even at the highest number of cycles, the oxide was coated as discontinuous nanoparticles. The continuity of these layers has an impact on the performance of the capacitors through its ability to provide electrical conduction paths to the substrate. Supercapacitor performances could therefore be further improved by using even more ALD cycles. XRD and XPS also showed the existence of a considerable amount of metallic Ru. It would be useful to investigate optimization of the ALD recipe or introduce post-

ALD treatments to achieve coatings composed predominantly of RuO2. It is also necessary to investigate other materials that are less expensive than RuO2 for use as the active electrode material in supercapacitors, such as MnO2, Co3O4, and conducting polymers. Furthermore, the current device was made by stacking two identical electrodes together. For the next generation, it is desirable to design a device structure with both electrodes on the same chip. Fig. 5.1 shows a schematic of one possible layout for future generations, in which symmetrical electrodes are arranged in an interdigitated pattern and the device is encapsulated in a solid electrolyte. The schematic shows a partial fill of the electrolyte for a better view of the underlying electrode structures. In this scenario, each finger of the interdigitated pattern is a trench filled with silicon 167 nanowire arrays generated using the metal assisted wet chemical etching process. An insulating layer should be deposited on the silicon surface, and this would be followed by deposition of a current collecting layer and the active RuO2 layer. Because the entire surface of the silicon will be covered by an insulating film, no current will flow through the silicon during device operation. In order to achieve a conformal coating on silicon nanowires with high aspect ratios, Al2O3 and TiN are potential materials for insulating and current collecting purposes, respectively, as they can be readily deposited using ALD. After the deposition, the RuO2 and the current collecting layers would be patterned to isolate two sets of interdigitated electrodes. In the schematic, grey represents the silicon substrate, orange represents the RuO2 layer and blue is the insulating layer. The TiN current collector is covered with RuO2 so it is not shown in the figure. The yellow pads represent a contact metal such as Au or Al.

Figure 5.1 A schematic of a nanowire solid state supercapacitor on a single chip. 168

In addition to the energy storage capacitors fabricated as described in this thesis, other devices such as sensors and batteries can also take advantage of silicon nanowire arrays generated using metal assisted wet etching methods. The unique structure of vertical and aligned silicon nanowires is favored for sensing applications due to the higher utilization of sensing area. The wires in the trench is a promising structure to build microfluidic sensors. For batteries, the aligned silicon nanowires allow accommodation of the large volume change during charge/discharge, thus leading to a better cyclability and rate capability. After developing processes for fabrication of sensors and batteries, the most challenging but also promising work is to integrate the capacitors fabricated in this thesis with them. In order to demonstrate such a microsystem, more effort will be needed to develop compatible process for the making of all the different nanowire devices in the same overall process.

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Reference

1. Wagner, R.S. and W.C. Ellis, Vapor-liquid-solid mechanism of single crystal growth. Applied Physics Letters, 1964. 4(5): p. 89-90. 2. Morales, A.M. and C.M. Lieber, A Laser Ablation Method for the Synthesis of Crystalline Semiconductor Nanowires. Science, 1998. 279(5348): p. 208-211. 3. Yi, C., et al., Diameter-controlled synthesis of single-crystal silicon nanowires. Applied Physics Letters, 2001. 78(15): p. 2214-16. 4. Westwater, J., et al., Growth of silicon nanowires via gold/silane vapor-liquid-solid reaction. Journal of Vacuum Science & Technology B, 1997. 15(3): p. 554-557. 5. Zhang, Y.F., et al., Diameter modification of silicon nanowires by ambient gas. Applied Physics Letters, 1999. 75(13): p. 1842-1844. 6. Chen, L., W. Lu, and C.M. Lieber, Chapter 1 Semiconductor Nanowire Growth and Integration, in Semiconductor Nanowires: From Next-Generation Electronics to Sustainable Energy2015, The Royal Society of Chemistry. p. 1-53. 7. Cheung, C.L., et al., Fabrication of nanopillars by nanosphere lithography. Nanotechnology, 2006. 17(5): p. 1339. 8. Keith, J.M., et al., Wafer-scale patterning of sub-40 nm diameter and high aspect ratio (>50:1) silicon pillar arrays by nanoimprint and etching. Nanotechnology, 2008. 19(34): p. 345301. 9. Dimova-Malinovska, D., et al., Preparation of thin porous silicon layers by stain etching. Thin Solid Films, 1997. 297(1–2): p. 9-12. 10. Sarathy, J., et al., Demonstration of photoluminescence in nonanodized silicon. Applied Physics Letters, 1992. 60(13): p. 1532-1534. 11. Steckl, A.J., et al., Doping‐induced selective area photoluminescence in porous silicon. Applied Physics Letters, 1993. 62(16): p. 1982-1984. 12. Li, X. and P.W. Bohn, Metal-assisted chemical etching in HF/H2O2 produces porous silicon. Applied Physics Letters, 2000. 77(16): p. 2572-2574. 13. Choi, W.K., T.H. Liew, and M.K. Dawood, Synthesis of Silicon Nanowires and Nanofin Arrays Using Interference Lithography and Catalytic Etching. Nano Lett, 2008. 8(11): p. 3799-3802. 14. Chang, S.-W., et al., Densely Packed Arrays of Ultra-High-Aspect-Ratio Silicon Nanowires Fabricated using Block-Copolymer Lithography and Metal-Assisted Etching. Advanced Functional Materials, 2009. 19(15): p. 2495-2500. 15. Chang, S.W., et al., Metal-catalyzed etching of vertically aligned polysilicon and amorphous silicon nanowire arrays by etching direction confinement. Advanced Functional Materials, 2010. 20(24): p. 4364-4370. 16. Chartier, C., S. Bastide, and C. Levyclement, Metal-assisted chemical etching of silicon in HF–H2O2. Electrochimica Acta, 2008. 53(17): p. 5509-5516. 17. Lianto, P., et al., Vertical etching with isolated catalysts in metal-assisted chemical etching of silicon. Nanoscale, 2012. 4(23): p. 7532-7539. 18. Lai, C.Q., et al., Mechanics of Catalyst Motion during Metal Assisted Chemical Etching of Silicon. The Journal of Physical Chemistry C, 2013. 117(40): p. 20802-20809.

170

19. Chattopadhyay, S., X. Li, and P.W. Bohn, In-plane control of morphology and tunable photoluminescence in porous silicon produced by metal-assisted electroless chemical etching. Journal of Applied Physics, 2002. 91(9): p. 6134-6140. 20. To, W.K., et al., Fabrication of n-Type Mesoporous Silicon Nanowires by One-Step Etching. Nano Lett, 2011. 11(12): p. 5252-8. 21. Kolasinski, K., The mechanism of galvanic/metal-assisted etching of silicon. Nanoscale Research Letters, 2014. 9(1): p. 432. 22. Peng, K., et al., Uniform, axial-orientation alignment of one-dimensional single-crystal silicon nanostructure arrays. Angew Chem Int Ed Engl, 2005. 44(18): p. 2737-42. 23. Peng, K.Q., et al., Fabrication of Single-Crystalline Silicon Nanowires by Scratching a Silicon Surface with Catalytic Metal Particles. Advanced Functional Materials, 2006. 16(3): p. 387-394. 24. Geyer, N., et al., Model for the Mass Transport during Metal-Assisted Chemical Etching with Contiguous Metal Films As Catalysts. The Journal of Physical Chemistry C, 2012. 116(24): p. 13446-13451. 25. Huang, Z., et al., Metal-assisted chemical etching of silicon: a review. Adv Mater, 2011. 23(2): p. 285-308. 26. Chiappini, C., et al., Biodegradable porous silicon barcode nanowires with defined geometry. Adv Funct Mater, 2010. 20(14): p. 2231-2239. 27. Lee, D.H., et al., Strategies for controlling Si nanowire formation during Au-assisted electroless etching. Journal of Materials Chemistry, 2011. 21(28): p. 10359-10363. 28. Lotty, O., et al., Porous to Nonporous Transition in the Morphology of Metal Assisted Etched Silicon Nanowires. Japanese Journal of Applied Physics, 2012. 51(11S): p. 11PE03. 29. Chen, C.-Y. and C.-P. Wong, Morphological transition of Si surfaces from solid nanowires to porous nanobelts at room temperature. Chemical Communications, 2013. 49(66): p. 7295-7297. 30. Balasundaram, K., et al., Porosity control in metal-assisted chemical etching of degenerately doped silicon nanowires. Nanotechnology, 2012. 23(30). 31. Peng, K., et al., Metal-Particle-Induced, Highly Localized Site-Specific Etching of Si and Formation of Single-Crystalline Si Nanowires in Aqueous Fluoride Solution. Chemistry – A European Journal, 2006. 12(30): p. 7942-7947. 32. Lee, C.-L., et al., Pore formation in silicon by wet etching using micrometre-sized metal particles as catalysts. Journal of Materials Chemistry, 2008. 18(9): p. 1015. 33. Peng, K., et al., Motility of Metal Nanoparticles in Silicon and Induced Anisotropic Silicon Etching. Advanced Functional Materials, 2008. 18(19): p. 3026-3035. 34. Yang, Y.M., et al., Catalysis of dispersed silver particles on directional etching of silicon. Applied Surface Science, 2008. 254(10): p. 3061-3066. 35. Backes, A. and U. Schmid, Impact of doping level on the metal assisted chemical etching of p-type silicon. Sensors and Actuators B: Chemical, (0). 36. Zhong, X., et al., Unveiling the formation pathway of single crystalline porous silicon nanowires. ACS Appl Mater Interfaces, 2011. 3(2): p. 261-70. 37. Geyer, N., et al., Sub-20 nm Si/Ge Superlattice Nanowires by Metal-Assisted Etching. Nano Lett, 2009. 9(9): p. 3106-3110. 38. Wolfsteller, A., et al., Comparison of the top-down and bottom-up approach to fabricate nanowire-based silicon/germanium heterostructures. Thin Solid Films, 2010. 518(9): p. 2555-2561.

171

39. Hidetaka, A., Y. Takayuki, and O. Sachiko, Formation of Periodic Microbump Arrays by Metal-Assisted Photodissolution of InP. Japanese Journal of Applied Physics, 2010. 49(4R): p. 046505. 40. DeJarld, M., et al., Formation of High Aspect Ratio GaAs Nanostructures with Metal- Assisted Chemical Etching. Nano Lett, 2011. 11(12): p. 5259-5263. 41. Laegu, K., et al., Electrical characteristics of highly reliable ultrathin hafnium oxide gate dielectric. Ieee Electron Device Letters, 2000. 21(4): p. 181-183. 42. Lee, B.H., et al., Thermal stability and electrical characteristics of ultrathin hafnium oxide gate dielectric reoxidized with rapid thermal annealing. Applied Physics Letters, 2000. 76(14): p. 1926-1928. 43. Robert F, P., Semiconductor fundamentals 2nd ed. Modular series on solid state devices. Vol. 1. 1989, Reading, Mass: Addison-Wesley Pub. Co. p570. 44. Sze, S.M., Semiconductor devices, physics and technology1985, New York: Wiley. p585- 590. 45. Rarnadass, Y.K., A.P. Chandrakasan, and Ieee, Voltage scalable switched capacitor DC- DC converter for ultra-low-power on-chip applications, in 2007 Ieee Power Electronics Specialists Conference, Vols 1-62007, Ieee, Electron Devices Soc & Reliability Group: New York. p. 2353-2359. 46. Lehmann, V., et al., A novel capacitor technology based on porous silicon. Thin Solid Films, 1996. 276(1–2): p. 138-142. 47. Chengwen, P., et al. A novel, low-cost deep trench decoupling capacitor for high- performance, low-power bulk CMOS applications. in Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on. 2008. 48. Wang, G., et al. Scaling deep trench based eDRAM on SOI to 32nm and Beyond. in 2009 IEEE International Electron Devices Meeting (IEDM). 2009. 49. Roozeboom, F., et al. High-density, low-loss MOS capacitors for integrated RF decoupling. in 2001 International Symposium on Microelectronics, October 9, 2001 - October 11, 2001. 2001. Baltimore, MD, United states: SPIE. 50. Roozeboom, F., et al., Ultrahigh-density trench capacitors in silicon and their application to integrated DC-DC conversion. Procedia Chemistry, 2009. 1(1): p. 1435-1438. 51. Roozeboom, F., et al., ALD Options for Si-integrated Ultrahigh-density Decoupling Capacitors in Pore and Trench Designs. ECS Transactions, 2007. 3(15): p. 173-181. 52. Klootwijk, J.H., et al., Ultrahigh capacitance density for multiple ALD-grown MIM capacitor stacks in 3-D silicon. Ieee Electron Device Letters, 2008. 29(7): p. 740-742. 53. Chang, S.W., et al., Fabrication of silicon nanopillar-based nanocapacitor arrays. Applied Physics Letters, 2010. 96(15). 54. Chmiola, J., et al., Monolithic Carbide-Derived Carbon Films for Micro-Supercapacitors. Science, 2010. 328(5977): p. 480-483. 55. Kaner, M.F.E.-K.a.R.B., Scalable fabrication of high-power graphene micro- supercapacitors for flexible and on-chip energy storage. 2012. 56. Thissandier, F., et al., Are tomorrow's micro-supercapacitors hidden in a forest of silicon nanotrees? Journal of Power Sources, 2014. 269(0): p. 740-746. 57. Thissandier, F., et al., Highly doped silicon nanowires based electrodes for micro- electrochemical capacitor applications. Electrochemistry Communications, 2012. 25(0): p. 109-111.

172

58. Thissandier, F., et al., Micro-ultracapacitors with highly doped silicon nanowires electrodes. Nanoscale Research Letters, 2013. 8(1): p. 38. 59. Thissandier, F., et al., Tuning silicon nanowires doping level and morphology for highly efficient micro-supercapacitors. Nano Energy, 2014. 5(0): p. 20-27. 60. Thissandier, F., et al., Ultra-dense and highly doped SiNWs for micro-supercapacitors electrodes. Electrochimica Acta, 2014. 117(0): p. 159-163. 61. Berton, N., et al., Wide-voltage-window silicon nanowire electrodes for micro- supercapacitors via electrochemical surface oxidation in ionic liquid electrolyte. Electrochemistry Communications, 2014. 41(0): p. 31-34. 62. Alper, J.P., et al., Selective Ultrathin Carbon Sheath on Porous Silicon Nanowires: Materials for Extremely High Energy Density Planar Micro-Supercapacitors. Nano Lett, 2014. 14(4): p. 1843-1847. 63. Liu, X.R. and P.G. Pickup, Ru oxide supercapacitors with high loadings and high power and energy densities. Journal of Power Sources, 2008. 176(1): p. 410-416. 64. Jia, Q.X., et al., Epitaxial growth of highly conductive RuO2 thin films on (100) Si. Applied Physics Letters, 1996. 68(8): p. 1069-1071. 65. Hu, C.C. and Y.H. Huang, Cyclic Voltammetric Deposition of Hydrous Ruthenium Oxide for Electrochemical Capacitors. Journal of The Electrochemical Society, 1999. 146(7): p. 2465-2471. 66. Zheng, J.P., P.J. Cygan, and T.R. Jow, Hydrous Ruthenium Oxide as an Electrode Material for Electrochemical Capacitors. Journal of The Electrochemical Society, 1995. 142(8): p. 2699-2703. 67. Jang, G.-W., E.W. Tsai, and K. Rajeshwar, Charge storage and transport in thermal ruthenium oxide thin films. Journal of Electroanalytical Chemistry and Interfacial Electrochemistry, 1989. 263(2): p. 383-397. 68. Wu, Z.-S., et al., Graphene/metal oxide composite electrode materials for energy storage. Nano Energy, 2012. 1(1): p. 107-131. 69. Wu, Z.S., et al., Anchoring Hydrous RuO2 on Graphene Sheets for High-Performance Electrochemical Capacitors. Advanced Functional Materials, 2010. 20(20): p. 3595-3602. 70. Kim, I.-H., J.-H. Kim, and K.-B. Kim, Electrochemical Characterization of Electrochemically Prepared Ruthenium Oxide/Carbon Nanotube Electrode for Supercapacitor Application. Electrochemical and Solid-State Letters, 2005. 8(7): p. A369- A372. 71. Wang, W., et al., Hydrous Ruthenium Oxide Nanoparticles Anchored to Graphene and Carbon Nanotube Hybrid Foam for Supercapacitors. Sci. Rep., 2014. 4. 72. Lee, B.J., et al., Carbon nanofibre/hydrous RuO2 nanocomposite electrodes for supercapacitors. Journal of Power Sources, 2007. 168(2): p. 546-552. 73. Dinh, T.M., et al., Hydrous RuO2/carbon nanowalls hierarchical structures for all-solid- state ultrahigh-energy-density micro-supercapacitors. Nano Energy, 2014. 10: p. 288-294. 74. Ferris, A., et al., 3D RuO2 Microsupercapacitors with Remarkable Areal Energy. Advanced Materials, 2015. 27(42): p. 6625-6629. 75. Gnerlich, M., et al., Selective deposition of nanostructured ruthenium oxide using Tobacco mosaic virus for micro-supercapacitors in solid Nafion electrolyte. Journal of Power Sources, 2015. 293: p. 649-656.

173

76. Wang, X., et al., Fabrication of a symmetric micro supercapacitor based on tubular ruthenium oxide on silicon 3D microstructures. Journal of Power Sources, 2014. 252: p. 64-72. 77. Warren, R., et al., Highly active ruthenium oxide coating via ALD and electrochemical activation in supercapacitor applications. Journal of Materials Chemistry A, 2015. 3(30): p. 15568-15575. 78. Jung, H.J., et al., Atomic Layer Deposition of Ruthenium and Ruthenium Oxide Thin Films from a Zero-Valent (1,5-Hexadiene)(1-isopropyl-4-methylbenzene)ruthenium Complex and O2. Chemistry of Materials, 2014. 26(24): p. 7083-7090. 79. Gnerlich, M., et al., Solid flexible electrochemical supercapacitor using Tobacco mosaic virus nanostructures and ALD ruthenium oxide. Journal of Micromechanics and Microengineering, 2013. 23(11): p. 114014. 80. Zhang, M.L., et al., Preparation of large-area uniform silicon nanowires arrays through metal-assisted chemical etching. Journal of Physical Chemistry C, 2008. 112(12): p. 4444- 4450. 81. Li, X., et al., Influence of the Mobility of Pt Nanoparticles on the Anisotropic Etching Properties of Silicon. Ecs Solid State Letters, 2013. 2(2): p. P22-P24. 82. Chen, H., et al., Wafer-Scale Synthesis of Single-Crystal Zigzag Silicon Nanowire Arrays with Controlled Turning Angles. Nano Lett, 2010. 10(3): p. 864-868. 83. Hildreth, O.J., A.G. Fedorov, and C.P. Wong, 3D Spirals with Controlled Chirality Fabricated Using Metal-Assisted Chemical Etching of Silicon. Acs Nano, 2012. 6(11): p. 10004-10012. 84. Peng, K., et al., Silicon nanowires for rechargeable lithium-ion battery anodes. Applied Physics Letters, 2008. 93(3): p. 033105. 85. Bang, B.M., et al., Scalable approach to multi-dimensional bulk Si anodes via metal- assisted chemical etching. Energy & Environmental Science, 2011. 4(12): p. 5013-5019. 86. Chang, S., et al., Fabrication of silicon nanopillar-based nanocapacitor arrays. Appl Phys Lett, 2010. 96: p. 153108 - 3. 87. Peng, K.-Q., X. Wang, and S.-T. Lee, Gas sensing properties of single crystalline porous silicon nanowires. Applied Physics Letters, 2009. 95(24): p. 243112. 88. In, H.J., C.R. Field, and P.E. Pehrsson, Periodically porous top electrodes on vertical nanowire arrays for highly sensitive gas detection. Nanotechnology, 2011. 22(35). 89. Tsai, S.-H., et al., Significant Efficiency Enhancement of Hybrid Solar Cells Using Core– Shell Nanowire Geometry for Energy Harvesting. Acs Nano, 2011. 5(12): p. 9501-9510. 90. Peng, K., et al., Aligned Single-Crystalline Si Nanowire Arrays for Photovoltaic Applications. Small, 2005. 1(11): p. 1062-1067. 91. Qu, Y., H. Zhou, and X. Duan, Porous silicon nanowires. Nanoscale, 2011. 3: p. 4060 - 4068. 92. Balasundaram, K., et al., Porosity control in metal-assisted chemical etching of degenerately doped silicon nanowires. Nanotechnology, 2012. 23(30): p. 305304. 93. Canham, L.T., Silicon quantum wire array fabrication by electrochemical and chemical dissolution of wafers. Applied Physics Letters, 1990. 57(10): p. 1046-1048. 94. Lehmann, V. and U. Gösele, Porous silicon formation: A quantum wire effect. Applied Physics Letters, 1991. 58(8): p. 856-858. 95. Lehmann, V., The Physics of Macropore Formation in Low Doped n‐Type Silicon. Journal of The Electrochemical Society, 1993. 140(10): p. 2836-2843. 174

96. Kim, J., H. Rhu, and W. Lee, A continuous process for Si nanowires with prescribed lengths. Journal of Materials Chemistry, 2011. 21(40): p. 15889-15894. 97. Li, X., et al., Fast electroless fabrication of uniform mesoporous silicon layers. Electrochimica Acta, 2013. 94(0): p. 57-61. 98. Li, L., X. Zhao, and C.-P. Wong, Deep Etching of Single- and Polycrystalline Silicon with High Speed, High Aspect Ratio, High Uniformity, and 3D Complexity by Electric Bias- Attenuated Metal-Assisted Chemical Etching (EMaCE). ACS Appl Mater Interfaces, 2014. 6(19): p. 16782-16791. 99. Huang, Z.P., et al., Metal-assisted electrochemical etching of silicon. Nanotechnology, 2010. 21(46): p. 465301. 100. Chourou, M.L., et al., Metal-assisted etching of p-type silicon under anodic polarization in HF solution with and without H2O2. Electrochimica Acta, 2010. 55(3): p. 903-912. 101. Weisse, J.M., et al., Electroassisted Transfer of Vertical Silicon Wire Arrays Using a Sacrificial Porous Silicon Layer. Nano Lett, 2013. 102. Geyer, N., et al., Ag-Mediated Charge Transport during Metal-Assisted Chemical Etching of Silicon Nanowires. ACS Appl Mater Interfaces, 2013. 5(10): p. 4302-4308. 103. Föll, H., et al., Formation and application of porous silicon. Materials Science and Engineering: R: Reports, 2002. 39(4): p. 93-141. 104. Kim, J., et al., Au/Ag Bilayered Metal Mesh as a Si Etching Catalyst for Controlled Fabrication of Si Nanowires. Acs Nano, 2011. 5(4): p. 3222-3229. 105. Walsh, M.E., Nanostructuring Magnetic Thin Films Using Interference Lithography, in Electrical Engineering2000, Massachusetts Institute of Technology. 106. Pierret, R.F., Semiconductor device fundamentals1996: Reading, Mass. : Addison-Wesley, c1996. 107. Bard, A.J., Stratmann, M., Licht, S. , Encyclopedia of electrochemistry, Vol. 6: Semiconductor Electrodes and Photoelectrochemistry., 2002, Wiley-VCH. 108. Brook, P. and C.S. Whitehead, Hyperabrupt junctions in Au-Si Schottky diodes by ion implantation. Electronics Letters, 1968. 4(16): p. 335-337. 109. Hecht, M.H., et al., Ballistic-hole spectroscopy of interfaces. Physical Review B, 1990. 42(12): p. 7663-7666. 110. Smith, B.L. and E.H. Rhoderick, Schottky barriers on p-type silicon. Solid-State Electronics, 1971. 14(1): p. 71-75. 111. Liu, D.Q. and D.J. Blackwood, The Role of the Flat-Band Potential in Porous Silicon Formation. Journal of The Electrochemical Society, 2012. 159(12): p. H909-H911. 112. Schlichthörl, G. and L.M. Peter, Deconvolution of the Impedance of the Silicon/Electrolyte Interface by Potential ‐ Modulated ‐ Microwave Measurements. Journal of The Electrochemical Society, 1994. 141(12): p. L171-L173. 113. Purtell, R., et al., Schottky barrier formation at Pd, Pt, and Ni/Si(111) interfaces. Journal of Vacuum Science & Technology A, 1983. 1(2): p. 566-569. 114. Li, X. and P. Bohn, Metal-assisted chemical etching in HF/H2O2 produces porous silicon. Appl Phys Lett, 2000. 77: p. 2572 - 2574. 115. Joo, M.H., et al., Enhancing the breakdown voltages of Au/n-Si Schottky diodes by boron ion beam-induced edge termination. Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, 2000. 168(3): p. 399-403. 116. Lepselter, M.P. and S.M. Sze, Silicon Schottky Barrier Diode with Near-Ideal I-V Characteristics. Bell System Technical Journal, 1968. 47(2): p. 195-208. 175

117. Theunissen, M.J.J., Etch Channel Formation during Anodic Dissolution of N‐Type Silicon in Aqueous Hydrofluoric Acid. Journal of The Electrochemical Society, 1972. 119(3): p. 351-360. 118. Qu, Y.Q., et al., Electrically Conductive and Optically Active Porous Silicon Nanowires. Nano Lett, 2009. 9(12): p. 4539-4543. 119. Cullis, A., L. Canham, and P. Calcott, The structural and luminescence properties of porous silicon. J Appl Phys, 1997. 82: p. 909 - 965. 120. Meek, R.L., n+ Silicon-electrolyte interface capacitance. Surface Science, 1971. 25(3): p. 526-536. 121. Preier, H., Surface carrier generation including tunnel transitions. Surface Science, 1969. 17(1): p. 125-131. 122. Van Voorden, A.M., et al. The Application of Super Capacitors to relieve Battery-storage systems in Autonomous Renewable Energy Systems. in Power Tech, 2007 IEEE Lausanne. 2007. 123. Tinani, M., et al., In situ real-time studies of nickel silicide phase formation. Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2001. 19(2): p. 376. 124. Weber, W.M., et al., Silicon to nickel-silicide axial nanowire heterostructures for high performance electronics. physica status solidi (b), 2007. 244(11): p. 4170-4175. 125. Xu, W., V. Palshin, and J.C. Flake, Nickel monosilicide contact formation in electrolessly etched silicon nanowires deposited onto nickel electrodes. Journal of The Electrochemical Society, 2009. 156(7): p. H544-H547. 126. Yaish, Y.E., et al., Kinetics of nickel silicide growth in silicon nanowires: From linear to square root growth. Journal of Applied Physics, 2011. 109(9): p. -. 127. Hsu, H.-F., et al., Fabrication of Ni-silicide/Si heterostructured nanowire arrays by glancing angle deposition and solid state reaction. Nanoscale Research Letters, 2013. 8(1): p. 224. 128. Gandhi, S.K., VLSI fabrication principles: silicon and gallium arsenide1994: John Wiley. 129. Heiss, M., C. Colombo, and A. Fontcuberta i Morral. Nanowire based heterostructures: fundamental properties and applications. 2011. 130. Simon, P. and Y. Gogotsi, Materials for electrochemical capacitors. Nat Mater, 2008. 7(11): p. 845-854. 131. Kaempgen, M., et al., Printable Thin Film Supercapacitors Using Single-Walled Carbon Nanotubes. Nano Lett, 2009. 9(5): p. 1872-1876. 132. Yuan, L., et al., Flexible Solid-State Supercapacitors Based on Carbon Nanoparticles/MnO2 Nanorods Hybrid Structure. Acs Nano, 2012. 6(1): p. 656-661. 133. Xiong, G., et al., Graphitic Petal Electrodes for All-Solid-State Flexible Supercapacitors. Advanced Energy Materials, 2013: p. n/a-n/a. 134. Wang, G., et al., Solid-State Supercapacitor Based on Activated Carbon Cloths Exhibits Excellent Rate Capability. Advanced Materials, 2014: p. n/a-n/a. 135. Ben, H., et al., Highly flexible, all solid-state micro-supercapacitors from vertically aligned carbon nanotubes. Nanotechnology, 2014. 25(5): p. 055401. 136. Wang, S., et al., High-performance all solid-state micro-supercapacitor based on patterned photoresist-derived porous carbon electrodes and an ionogel electrolyte. Journal of Materials Chemistry A, 2014. 2(21): p. 7997-8002.

176

137. Chatterjee, S., et al., Electrochemical and Corrosion Stability of Nanostructured Silicon by Graphene Coatings: Toward High Power Porous Silicon Supercapacitors. The Journal of Physical Chemistry C, 2014. 118(20): p. 10893-10902. 138. Alper, J.P., et al., Silicon carbide coated silicon nanowires as robust electrode material for aqueous micro-supercapacitor. Applied Physics Letters, 2012. 100(16): p. -. 139. Tao, B., et al., Preparation and electrochemistry of NiO/SiNW nanocomposite electrodes for electrochemical capacitors. Electrochimica Acta, 2010. 55(18): p. 5258-5262. 140. Aradilla, D., et al., An innovative 3-D nanoforest heterostructure made of polypyrrole coated silicon nanotrees for new high performance hybrid micro-supercapacitors. Journal of Materials Chemistry A, 2015. 3(26): p. 13978-13985. 141. Warren, R., et al. ALD ruthenium oxide-carbon nanotube electrodes for supercapacitor applications. in Micro Electro Mechanical Systems (MEMS), 2014 IEEE 27th International Conference on. 2014. 142. Yoon, Y.S., et al., Solid-state thin-film supercapacitor with ruthenium oxide and solid electrolyte thin films. Journal of Power Sources, 2001. 101(1): p. 126-129. 143. Qadir, K., et al., Intrinsic Relation between Catalytic Activity of CO Oxidation on Ru Nanoparticles and Ru Oxides Uncovered with Ambient Pressure XPS. Nano Lett, 2012. 12(11): p. 5761-5768. 144. Lai, C.Q., et al., Metal assisted anodic etching of silicon. Nanoscale, 2015. 7(25): p. 11123- 11134. 145. Park, B.-O., et al., Performance of supercapacitor with electrodeposited ruthenium oxide film electrodes—effect of film thickness. Journal of Power Sources, 2004. 134(1): p. 148- 152. 146. Yae, S., et al., Catalytic activity of noble metals for metal-assisted chemical etching of silicon. Nanoscale Research Letters, 2012. 7(1): p. 1-5. 147. daRosa, C.P., E. Iglesia, and R. Maboudian, Copper deposition onto silicon by galvanic displacement: Effect of Cu complex formation in NH4F solutions. Electrochimica Acta, 2009. 54(12): p. 3270-3277. 148. Aoyagi, H., et al., Basic properties of anodized porous silicon formed under uniform current density. Electronics and Communications in Japan (Part II: Electronics), 1994. 77(4): p. 97-105.

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Appendix A Effects of Catalyst Type and Structure in Metal-Assisted

Chemical Etching (MACE)

A.1 Comparison between Ag, Au and Pt

As mentioned in Chapter 1, the catalyst type can also play a significant role in MACE. A review on three most commonly used catalysts Ag, Au and Pt is presented here, including a literature review and experiments conducted in this work.

Among those three catalysts, Ag was reported as the most unstable one in the etchant solution. Duan’s group proposed the idea that Ag catalyst dissolved into Ag+ and then redeposited on silicon substrate [36]. Fig. A.1 shows the schematic of the formation of porous silicon nanowires on highly doped wafers, and nonporous nanowires on lightly doped wafers through Ag assisted etching. Their studies showed that Ag metal converted to the soluble ionic form and re- nucleated on the sidewalls of nanowires. They also concluded that highly doped wafers with a high concentration of defects tended to attract more Ag+ to redeposit along the sidewall of nanowires, thus leading to a more porous nanowire structure.

178

Figure A.1 A schematic representation of silicon nanowire formation with Ag catalyzed MACE from highly and lightly doped wafers [36].

Geyer et al. also demonstrated experimentally that silver will dissolve and redeposit in etchant solution [102]. They designed an experiment with the setup shown in Fig. A.2, in which a massive Ag wire was placed in direct contact with a silicon substrate patterned with strips of photoresist. Two regimes named as A and B, referring to locations away from the Ag wire and close to the Ag wire respectively, were studied. They found etching in both regimes, which supported the model that Ag dissolved and redeposited in the MACE process.

Figure A.2 Experimental setup for studying the effect of electronic transport in Ag catalyzed MACE [102]. 179

We carried out similar experiments with Au catalyst. A macroscopic Au wire was placed in close proximity with a p-type silicon substrate in H2O2/ HF solution for 10 min, as shown in Fig.

A.3a. The two materials were separated by a 400 nm thick perforated photoresist film. Unlike the case when an Ag wire was used, no Au nanoparticles or etching were observed on the silicon surface as shown in Fig. A.3b. This showed that Au was stable in the etching solution, unlike Ag, which went through dissolution and re-deposition in the presence of HF and H2O2. This result was consistent with those from previous reports [18, 104].

Figure A.3 (a) Schematic diagram showing a macroscopic Au wire placed in close proximity with a p-type

Si substrate in 0.2M H2O2/4M HF solution, separated by a perforated photoresist film. (b) SEM images at various magnifications showing that no etching occurred after 10 min. The artifacts in the pictures are photoresist that have not been properly removed. The images are taken around these artifacts as they assist in finding the right depth of field, which is difficult to do when the surface, like in this case, is too smooth.

180

Pt presents great as a catalyst for MACE, since it does not create mid-gap states like Au and is widely used for silicide formation in semiconductor industry. As Pt is also a noble metal, it is conceivable that Pt will be as stable in the etchant solution as Au. Meanwhile, Pt nanoparticles were reported to show a much higher catalytical activity and thus a higher etch rate than Au, while

Ag is comparable to Au in the etch rate [146]. To confirm this, we studied the difference between

Au and Pt with our MACE procedure, using a perforated continuous film of these two metals.

After applying the same etchant chemistry used for Au, we observed that Pt catalyzed etching resulted in nanowires with low-stiffness and high porosity, as shown in Fig. A.4a. It was concluded previously that the porosity of nanowires obtained from MACE was caused by the lateral diffusion of excess holes generated by the catalyst [17]. Therefore, a more porous nanowire structure from Pt catalyzed etching indicates that under the same etching condition, Pt generates holes at a much higher rate than Au due to its higher catalytic activity. The excess holes that cannot be consumed at the Pt/Si interface then diffuse laterally, leading to extensive etching in the nanowires.

As mentioned in the literature review of MACE in Chapter 1, the etchant chemistry can be altered to reduce the generation and lateral diffusion of excess holes. Reducing the oxidant concentration can decrease the amount of holes injected into silicon. Meanwhile, increasing the

HF concentration will accelerate the consumption of holes that contribute to the vertical etching of silicon nanowires. By adjusting these two parameters together, we were able to generate solid nanowires at a reasonable etching rate with a Pt catalyst, as shown in Fig. A.4b.

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Figure A.4 SEM of Si nanowires etched with Pt under (a) conventional etchant chemistry used with Au catalyst in this thesis; (b) modified etchant chemistry.

A.2 Sandwiched catalyst Au/Cu/Au

Though Au is the most commonly used metal catalyst in MACE, it creates mid-gap states and diffuses rapidly in silicon. Therefore it is desirable to replace Au with other metals that are more CMOS compatible. In addition to Ag and Pt discussed in the previous section, we also investigated a cheaper catalyst, Cu. We first patterned Cu in the same way as Au to generate a perforated Cu mesh. The sample then went through the same MACE process we used for Au catalyzed etching. As can be seen from Fig. A.5, Cu itself resulted in a porous layer on the silicon surface rather than silicon nanowires.

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Figure A.5 An SEM image of Cu catalyzed etching of silicon.

When only Cu was used, as discussed above, porous silicon formed instead of silicon nanowires. Moreover, it was difficult to acquire a full picture of what occurred during Cu catalyzed etching, as the silicon surface had likely been polished during the etching. Inspired by Au/Ag bilayer metal mesh catalyst used by Kim et al. to prevent dissolution of Ag [104], we designed a trilayer catalyst stack of Au/Cu/Au to further investigate the effect of Cu had on MACE. The reason we used a trilayer catalyst stack instead of a bilayer was that Cu was more unstable in the etching solution than Ag, therefore sealing both the top and bottom of Cu was necessary to further minimize the Cu exposure to the solution.

We followed the standard MACE process with the novel catalyst structure of 15nm

Au/15nm Cu/15nm Au on two types of wafers, including lightly doped n-type and p-type silicon substrates. As the overall catalyst thickness was 45nm, we also carried out MACE with 45nm thick

Au catalyst in addition to the standard 20nm Au metal film to determine the catalyst film thickness effect. All three different samples were etched in the standard etchant solution for 30min. The

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SEM images of the n-type silicon substrate after etching were shown in Fig. A.6. The nanowires etched from 20nm Au, 45nm Au and Au/Cu/Au catalysts exhibited lengths of 5.6μm, 5.3μm, and

9.6μm respectively. We first concluded that the catalyst film thickness within our test window did not affect the etch rate and nanowire morphologies. We also observed that the sandwiched catalyst yielded longer nanowires than pure Au catalyst. Moreover, nanowires from the sandwiched catalyst were tapered, leading to sharper tips. Nanowires etched from the sandwiched catalyst were also more porous than those etched from pure Au catalyst, especially at the tip of the nanowires.

Figure A.6 SEM images of nanowires generated from lightly doped n-type silicon with (a) 20nm Au catalyst, (b) 45nm Au catalyst, (c) and (d) Au/Cu/Au catalyst.

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We then analyzed the sample etched with the trilayer stack before and after MACE with

Energy Dispersive X-ray Spectroscopy (EDX) to determine the role that Cu played during the etching. We found that Cu signal disappeared from the spectrum after etching, as shown in Fig.

A.7. We therefore propose the following model based on this observation. Cu first dissolves into its ionic form with the presence of HF and the oxidant. Then a displacement reaction occurs between Cu ions and the silicon, leading to the dissolution of silicon as reported in literature [147].

During this displacement reaction, Cu ions are also reduced back to elemental Cu atoms. The reaction stops once all the Cu ions have reacted with the silicon, if only HF is present in the solution.

However, with the presence of the oxidant, Cu can be oxidized into its ionic form again and the reaction repeats. In addition, most Cu atoms are locally confined so the displacement reaction process also contributed to the etching of silicon, thus leading to a higher etch rate. On the other hand, some of the Cu ions slowly diffuse into the solution and redeposit on the surface of silicon nanowires, leading to etching in the nanowires. The tapered tips of the nanowires are a result of their longer exposure time in the etching solution. This mechanism explains the higher etching rate and the tapered nanowire tips observed with the Au/Cu/Au catalyst.

Figure A.7 EDX of silicon substrate with the Au/Cu/Au catalyst (a) before and (b) after MACE.

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Appendix B Dissolution Valence and Porosity of Silicon in MAAE

B.1 Introduction

The dissolution valence of silicon is defined as the amount of electronic holes needed to dissolve one silicon atom. As mentioned in previous chapters, it is widely accepted that MACE process occurs according to the overall reaction shown below [17]:

nn4  Si6 HF  H O  H SiF  nH O  ( )H  . (B.1) 222 2 2 6 2 2

4+ As can be seen from the equation above, silicon atoms will all end up in the Si state.

However, the dissolution valence (n in the equation) can deviate from 4 due to the hydrogen produced during MACE, and so far there has been no accurate way to determine it.

With the MAAE process we invented, it becomes possible to determine the dissolution valence in MAAE experimentally. MAAE has an accurate control on the applied current density that is linked to the number of electronic holes injected into the system. The amount of silicon atoms can be calculated by measuring the weight change before and after etch. The ratio between the number of holes and silicon atoms then can be determined, which is the dissolution valence.

While conducting MAAE at different current densities, we will be able to find the trend of dissolution valence with respect to the current densities.

Moreover, we can calculate the amount of geometrically removed silicon atoms from

MAAE by measuring the dimension of silicon nanowire arrays from SEM images. The porosity is defined as the missing mass in the structure over the mass of the structure if it is solid. Fig. B.1 shows a schematic of the structure obtained from MAAE which includes an array of porous silicon nanowires on top of a porous layer.

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Figure B.1 A schematic of silicon nanostructures generated from MAAE.

The parameters of the sample are defined as follows: d is the diameter of nanowires, p is the period of nanowire array, l is the length of nanowires, A is the total etching area, ρ is the density of silicon, t is the thickness of porous layer, m1 is the mass of sample before MAAE and m2 is the mass after etch. So we have the following equations:

 d 2 Missing mass of the structure m12  m  1  ( )  A  l , (B.2) 4 p

2  d Mass the structure should have if solid  A   l  t , (B.3) 4 p 

2 dd2    Porosity P m12 m1 ( )  A l    A  l t  . (B.4) 44pp       

We have carried out MAAE on all four types of wafers: lightly and heavily doped p-type, lightly and heavily doped n-type silicon substrates. Each sample was tested using both metal contact and silicon contact configurations, as described in Chapter 2. All the experiments were conducted using the standard MAAE etchant composition.

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B.2 Dissolution valence

The experimental data for all four types of wafers are shown in Table B.1 to Table B.4, respectively.

Table B.1 Experimental data and calculated dissolution valence for lightly doped n-type silicon. Current Voltage Etched Weight before Weight after Dissolution /mA /V area/cm2 etching /mg etching /mg valence n 3 0.5 1*0.65 287.3175 287.0575 3.03 Metal 5 0.6 1*0.6 269.1248 268.7104 3.17 contact 10 0.7 1*0.7 247.8026 247.0223 3.36 15 0.9 1*0.75 264.6247 263.2273 2.82 20 1.2 1*0.6 288.0381 286.4033 3.21 3 4.6 0.7 294.2421 294.0048 3.32 Silicon 5 5.5 0.7 275.8312 275.3781 2.90 contact 10 6.5 0.7 308.7355 307.9836 3.49 15 7.2 0.7 315.3662 313.9117 2.71 20 8.5 0.7 287.5662 286.0228 3.40

Table B.2 Experimental data and calculated dissolution valence for lightly doped p-type silicon. Current Voltage Etched Weight before Weight after Dissolution /mA /V area/cm2 etching /mg etching /mg valence n 3 0.4 1*0.8 250.6111 250.3585 3.12 Metal 5 0.6 1*0.6 246.8942 246.5237 3.54 contact 10 0.7 1*0.75 260.2358 259.4012 3.14 15 0.8 1*0.85 235.5357 234.1989 2.95 20 1.0 1*0.9 229.0486 227.4291 3.24 3 0.3 0.7 355.1500 354.9339 3.64 Silicon 5 0.4 0.7 330.0973 329.6449 2.90 contact 10 0.6 0.7 314.0095 313.1371 3.01 15 0.8 0.7 272.9161 271.6766 3.18 20 1.0 0.7 299.5468 298.0460 3.50

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Table B.3 Experimental data and calculated dissolution valence for heavily doped n-type silicon. Current Voltage/ Etched Weight before Weight after Dissolution /mA V area/cm2 etching /mg etching /mg valence n 3 0.4 1*0.7 254.9026 254.6943 2.52 Metal 5 0.5 1*0.9 235.6520 235.2612 2.24 contact 10 0.7 1*0.7 250.7775 250.1850 2.95 15 0.8 1*0.9 256.2066 255.2788 2.83 20 1.0 1*0.9 277.2446 276.0018 2.82 3 0.2 0.7 279.5083 279.2528 2.05 Silicon 5 0.3 0.7 275.3492 274.9633 2.27 contact 10 0.5 0.7 277.8913 277.2328 2.66 15 0.6 0.7 294.4120 293.5031 2.89 20 0.8 0.7 273.9094 272.7037 2.90

Table B.4 Experimental data and calculated dissolution valence for heavily doped p-type silicon. Current Voltage Etched area Weight before Weight after Dissolution /mA /V /cm2 etching /mg etching /mg valence n 3 0.6 1*0.5 262.9052 262.6873 2.41 Metal 5 0.6 1*0.8 277.3176 276.9341 2.28 contact 10 0.7 1*1 261.3079 260.6349 2.60 15 0.9 0.8*0.7 286.1463 285.0995 2.51 20 1.0 1*0.6 270.9592 269.6500 2.67 3 0.3 0.7 296.8979 296.6456 2.08 Silicon 5 0.4 0.7 298.1325 297.7007 2.03 contact 10 0.6 0.7 304.9590 304.2363 2.42 15 0.8 0.7 302.1668 301.1179 2.50 20 1.0 0.7 301.2128 299.6657 2.26

The dissolution valence for each type of samples with respect to the anodic current densities are plotted in Fig. B.2.

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Figure B.2 Dissolution valence for (a) lightly doped n-type silicon, (b) lightly doped p-type, (c) heavily doped n-type silicon, (d) heavily doped p-type for both Au and Si anodic contacts.

In Fig. B.2, the dissolution valence varies between 2 and 4, and no obvious trend is observed. One possible explanation is that our current density window is not big enough to show the trend of dissolution valence. Researchers have determined the dissolution valence for anodization of silicon [148], as shown in Fig. B.3. Our experimental condition is 8 wt% HF solution, and the current densities are 4-30 mA/cm2. According to Fig. B.3, this is a relatively

190 small range. If we further expand the HF concentration and current density range, we might be able to see a trend.

Figure B.3 An equicontour map of the dissolution valence of anodization of silicon.

B.3 Porosity in silicon nanostructures

We then calculated the porosity of silicon nanostructures generated from lightly doped n- type silicon with Au contact according to Eqs. (B.2)-(B.4). The diameter of the nanowires are

200nm and the period is 400nm. The lengths of nanowires are determined from SEM images shown in Fig. B.4. The corresponding porosities are shown in Table B.5.

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Figure B.4 SEM images of silicon nanostructures generated from lightly doped n-type silicon with MAAE metal contact at current densities of (a) 4.6 mA/cm2, (b) 8.3 mA/cm2, (c) 14.3 mA/cm2, and (d) 20 mA/cm2.

Table B.5 Porosities of lightly doped n-type silicon etched from MAAE. Current density / mA/cm2 4.6 8.3 14.3 20 Porosity 49% 94% 162% 318%

Though the porosity is increasing with the increase of current density as shown in Table

B.5, the porosity calculated by this method reaches values beyond 1. We saw similar results with all other types of substrates as well. It turns out while calculating the porosity using the equations described previously, the nanowire length has a huge effect on the porosity. For example, changing the length from 1.5um to 1.6um will change the porosity from 50% to 20%. So it is not a reliable

192 approach to calculate the porosity, considering that the etching won’t be perfectly uniform across the sample during MAAE. Therefore, to determine the porosity, we either need to find a way to identify the nanowire length profile across the whole substrate accurately, or we need to use other approaches such as Brunauer–Emmett–Teller (BET).

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