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Fabrication of Capacitors Based on Silicon Nanowire Arrays Generated by Metal-Assisted Wet Chemical Etching by Wen Zheng

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Fabrication of Capacitors Based on Silicon Nanowire Arrays Generated by Metal-Assisted Wet Chemical Etching by Wen Zheng Fabrication of Capacitors Based on Silicon Nanowire Arrays Generated by Metal-Assisted Wet Chemical Etching By Wen Zheng B.S. Department of Chemistry, Tsinghua University (2010) SUBMITTED TO THE DEPARTMENT OF MATERIALS SCIENCE AND ENGINEERING IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY IN MATERIALS SCIENCE AND ENGINEERING AT THE MASSACHUSETTS INSTITUTE OF TECHNOLOGY June 2016 © 2016 Massachusetts Institute of Technology. All rights reserved Signature of Author . Department of Materials Science and Engineering May 20, 2016 Certified by . Carl V. Thompson Stavros Salapatas Professor of Materials Science and Engineering Thesis Supervisor Accepted by . Donald R. Sadoway Chair, Departmental Committee on Graduate Studies 1 Fabrication of Capacitors Based on Silicon Nanowire Arrays Generated by Metal-Assisted Wet Chemical Etching By Wen Zheng Submitted to the Department of Materials Science and Engineering at the Massachusetts Institute of Technology on May 20, 2016 in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy Abstract Capacitors with high capacitance density (capacitance per footprint area) have potential applications in autonomous microsystems that harvest energy from the environment, as they can store and release energy at high rates. Use of high surface-to-volume ratio structures has been demonstrated as an effective way to increase the electrode area, and therefore to improve the capacitance density, while still keeping the footprint area low. The goal of this thesis was to first develop an understanding of the mechanisms of metal assisted wet chemical etching for fabrication of arrays of silicon nanowires, and then use this understanding to build nanowire array on-chip capacitors in silicon substrates, in order to eliminate additional packaging and enable local and efficient energy delivery. Two types of capacitors were investigated: electrostatic metal-oxide- semiconductor (MOS) capacitors for power management, and supercapacitors for energy storage purposes. For both types of devices, enlarged surface area per footprint was achieved by utilizing the arrays of silicon nanowires. Fundamental studies of the roles of metals in metal-assisted chemical etching (MACE) of silicon were conducted. Lithography techniques were used to generate patterns in metal films which when subjected to MACE resulted in formation of ordered arrays of silicon nanowires. Investigation of various metal catalysts showed that Pt is a more active catalyst than Au, while Cu is not stable in the etchant. Tapered silicon nanowires can be generated by adding a layer of Cu between two Au layers, and etching occurs much faster than when a pure Au catalyst is used. 2 While carrying out research on the mechanisms of MACE, we developed a new electrochemical method for formation of arrays of silicon nanowires, metal-assisted anodic etching (MAAE). In this process, the etchant consists of HF alone, and does not include an oxidant. In both processes, HF is used as an etchant. However, in MACE, electronic holes are supplied through reduction of an oxidant (e.g. H2O2), while in MAAE, electronic holes are supplied through an external circuit, with anodic contact to either the metal or the silicon. In both contact cases for MAAE, the metal catalyzes the etching process and leads to controlled formation of silicon nanowires, without the need for an oxidant. This discovery, and its analysis, provided new insights into the mechanisms of both MAAE and MACE, and also opened the possibility for use of metal catalyzed electrochemical etching of other materials that cannot survive the HF/oxidant mixture. Processes for fabrication of on-chip capacitors based on silicon nanowires were next developed. We first fabricated on-chip MOS capacitors with nanowire arrays etched using MACE with both single crystal silicon substrates and polycrystalline silicon films. For wires made in both cases, the capacitance density followed a same scaling trend related to their geometries. Epitaxial wafers were used with a post-etch doping process to reduce the series resistance in the devices in order to obtain a better frequency response, as desired for high frequency circuits. To achieve higher capacitance densities for energy storage purposes, we also designed a solid state supercapacitor device based on nanowires etched using MAAE with heavily doped n-type silicon substrates. The silicon nanowires were coated with RuO2 using atomic layer deposition (ALD) to achieve a high capacitance. In this case, charge is stored through the formation of an electrical double layer and through reversible redox reactions. We showed that the capacitance density of these devices roughly scaled with the increased surface area of silicon nanowire arrays. The solid state supercapacitor achieved a capacitance density of 6.5mF/cm2, which is comparable to the best results achieved with other types of on-chip supercapacitors. In contrast with other processes for forming on-chip supercapacitors, the supercapacitors we demonstrated were fabricated using a fully complementary metal-oxide-semiconductor (CMOS) technology compatible process. Moreover, the Si nanowire-based device achieved this high capacitance density without sacrificing power performance compared to the planar device. Thesis Supervisor: Carl V. Thompson Stavros Salapatas Professor of Materials Science and Engineering 3 Acknowledgement First of all, I would like to thank my advisor, Professor Carl V. Thompson, for his guidance and support during my time at MIT. He is an advisor who really cares about his students. As a tremendous mentor, he has been extremely encouraging with patience to help me overcome the difficulties. His visions always inspired me to look at things from a new perspective. I would also like to thank my committee members, Professor Caroline Ross and Professor Eugene Fitzgerald, for their kindness and valuable comments on my research. I did most of my work using MTL, NSL and CMSE facilities. I would like to thank all the research staffs, in particular Kurt Broderick at MTL and James Daley at NSL, who have been extremely helpful in offering technical support. I want to thank my colleagues in the Materials for Micro and Nano Systems Group, especially Ahmed Al-Obeidi, Changquan Lai for their useful discussions and valuable collaborations. I also want to thank Robert Mitchell, Hang Yu, Gye Hyun Kim, Thomas Batcho, Jinghui Miao, Lin Xu, Yoon Ah Shin, Hangbo Zhao and other past members of the group. It has been a great honor for me to work with them all. A special thanks to my friends and family, especially to my parents, my mother-in-law and father-in-law for all the sacrifices that they have made on my behalf. Finally, I would like to express my deepest gratitude to my beloved husband, Zhongying Wang. Thank you for believing in me and encouraging me through tough moments. To my beloved daughter Emily Jiayao Wang, who has been a source of endless joy and strength for me. I cannot be more grateful for having your company towards the end of this experience. 4 5 Table of Contents Introduction .................................................................................................................. 24 1.1 Motivation and background ............................................................................................. 24 1.2 Metal-assisted chemical etching (MACE) ....................................................................... 25 1.2.1 Comparison with other fabrication techniques for silicon nanowires ................... 25 1.2.2 Mechanism ............................................................................................................ 30 1.2.3 Factors influencing MACE .................................................................................... 34 1.2.4 Applications to semiconductors other than silicon ................................................ 40 1.3 Literature review on two types of on-chip capacitors ..................................................... 42 1.3.1 Silicon based metal-oxide-semiconductor (MOS) capacitors ............................... 42 1.3.2 On-chip supercapacitors ........................................................................................ 49 Metal-Assisted Anodic Etching (MAAE) .................................................................... 58 2.1 Introduction ...................................................................................................................... 58 2.2 Materials and methods ..................................................................................................... 60 2.2.1 Metal film patterned by interference lithography .................................................. 60 2.2.2 Etching and characterization ................................................................................. 62 2.3 Establishing the Schottky barrier heights ........................................................................ 63 2.4 MAAE on lightly doped p-type silicon substrate ............................................................ 68 2.5 MAAE on lightly doped n-type silicon substrate ............................................................ 75 6 2.6 MAAE on heavily doped n-type and p-type silicon substrate ......................................... 84 2.7 Pt-catalyzed MAAE ......................................................................................................... 89 2.8 Conclusions.....................................................................................................................
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