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IBM 6X86mx Microprocessor Databook Introduction

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IBM 6X86mx Microprocessor Databook Introduction IBM 6X86MX Microprocessor Databook Introduction NOTICE TO CUSTOMERS: Some of the information contained in this document was obtained through a third party and IBM has not conducted independent tests of all product characteristics contained herein. The product described in this document is sold under IBM’s standard warranty. The information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applica- tions where malfunction may result in injury or death to persons. The information contained in this document does not effect or change IBM’s product specifications or warranties. Nothing in this docu- ment shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All the information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environ- ments may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will IBM be liable for any damages arising directly or indirectly from any use of the information contained in this document. 6x86MX™ is a trademark of Cyrix Corporation. MMX™ is a trademark of Intel Corporation Revision History Order Number Release Date Description of Changes G522-0318-00 June 1997 First Release G522-0318-01 September 1997 Voltage specification changes to chapters 1, 4, and the appendix. Changes to overall format and layout. G522-0318-02 (www only) April 1998 Power changes to chapter 4. Added Device Identification Registers to chapter 2. Added 100MHz bus and deleted 60MHz bus information in chapter 4. G522-0318-03 (www only) June 1998 Changes made to DC characteristics and power dissipation specs in chapter 4. G522-0318-04 (www only) July 1998 Changes made to timing specs in chapter 4. G522-0318-05 (www only) July 29, 1998 263 MHz spec added to Tables 4-5 and Table 4-6 © International Business Machines Corporation 1998 Printed in the United States of America April 1998. All Rights Reserved © Cyrix Corporation 1998 IBM and the IBM logo are registered trademarks of the IBM Corporation. IBM Microelectronics is a trademark of the IBM Corporation. Cyrix is a registered trademark of the Cyrix Corporation. 6x86 and 6x86MX are trademarks of Cyrix Corporation. Pentium and MMX are trademarks or registered trademarks of Intel Corporation. UNIX is a registered trademark in the United States and other countries licensed exclusively through X/Open Company Limited. Windows, Windows NT and Windows 95 are trademarks or registered trademarks of Microsoft Corporation. Other company, product, and service names may be trademarks or service marks of others. Product names used in this publication are for identification purposes only and may be trademarks of their respective compa- nies. IBM Corporation, 1000 River Street, Essex Junction, Vermont 05452-4299, United States of America. Page ii IBM 6x86MX Microprocessor Databook Introduction Features •Enhanced Sixth Generation Architecture • X86 Instruction Set Including MMX Instructions - Dual 7-Stage Integer Pipeline - 64K 4-Way Unified Write-Back Cache - Full MMX Instruction Set - 2 Level TLB (16 Entry L1, 384 Entry L2) - Runs Windows 95, Windows 3.x, Windows NT, - Branch Prediction with a 512-entry BTB DOS, UNIX, OS/2, Solaris, and others - Optimized for both 16 and 32-Bit Code - High Performance 80-Bit FPU • Other Features - Register Renaming - Socket 7 Pinout Compatible - 2.9 V Core, 3.3 V I/O - Flexible Core/Bus Clock Ratios (2, 2.5, 3, 3.5) - Leverages Existing Infrastructure Description The IBM 6x86MX™ processor offers significant The IBM 6x86MX processor achieves high perfor- enhancements over the IBM 6x86™ CPU. The IBM mance through use of two optimized superpipelined 6x86MX processor design quadruples the cache integer units, an on-chip floating point unit, and a size, triples the TLB size, increases the frequency large 64 KByte first level cache. The superpipelined scalability to 200 MHz and beyond, and is compat- architecture reduces timing constraints and ible with MMX™ technology. The IBM 6x86MX CPU increases frequency scalability. Advanced architec- contains a scratchpad RAM feature, supports perfor- tural techniques include register renaming, mance monitoring, and allows catching of both SMI out-of-order completion, data dependency removal, code and SMI data. The IBM 6x86MX CPU delivers branch prediction and speculative execution. Many high 16- and 32-bit performance running Windows® data dependencies and resource conflicts have NT™, Windows 95™, OS/2™, DOS, UNIX®, and been eliminated, allowing higher performance for other operating systems. both 16- and 32-bit software. Block Diagram Instruction Address Superpipelined Direct-Mapped 32 Instruction Data 16 Entry Integer Unit 128 32 Level 1 X Linear A31-A3 Address 32 TLB BE7#-BE0# 32 X Data 32 Address Six Way 32 256 Byte Instruction 64 384 Entry Y Linear 512 Entry FPU with Line Cache D63-D0 MMX Bus Level 2 Address BTB Y Data TLB Extension Interface Unit 64 64 KByte Unified Cache Memory CLK 64 Management CPU Core FPU Data Unit Cache Unit Data Control 32 X Physical Address 32 Bus Interface Y Physical Address The IBM 6x86MX processor is designed by Cyrix Corporation and manufactured by IBM Microelectronics. IBM 6x86MX Microprocessor Databook Page iii Introduction Page iv IBM 6x86MX Microprocessor Databook Table of Contents 2.0 Features..................................................................................................................... iii 3.0 Description ................................................................................................................ iii 4.0 Block Diagram........................................................................................................... iii 5.0 ARCHITECTURE OVERVIEW ................................................................................. 1-1 5.1 Major Differences Between the IBM 6x86MX and 6x86 Processors........................................... 1-2 5.2 Major Functional Blocks .............................................................................................................. 1-3 5.3 Integer Unit.................................................................................................................................. 1-4 5.4 Cache Units............................................................................................................................... 1-11 5.5 Memory Management Unit ........................................................................................................ 1-13 5.6 Floating Point Unit ..................................................................................................................... 1-14 5.7 Bus Interface Unit...................................................................................................................... 1-15 6.0 PROGRAMMING INTERFACE ................................................................................ 2-1 6.1 Processor Initialization ................................................................................................................ 2-1 6.2 Instruction Set Overview ............................................................................................................. 2-3 6.3 Register Sets............................................................................................................................... 2-4 6.4 System Register Set.................................................................................................................. 2-10 6.5 Model Specific Registers........................................................................................................... 2-30 6.6 Time Stamp Counter ................................................................................................................. 2-30 6.7 Performance Monitoring ............................................................................................................ 2-31 6.8 Performance Monitoring Counters 1 and 2 ............................................................................... 2-31 6.9 Debug Registers........................................................................................................................ 2-36 6.10 Test Registers ........................................................................................................................... 2-38 6.11 Address Space .......................................................................................................................... 2-38 6.12 Memory Addressing Methods.................................................................................................... 2-39 6.13 Memory Caches ........................................................................................................................ 2-47 6.14 Interrupts and Exceptions.......................................................................................................... 2-50 6.15 System Management Mode ...................................................................................................... 2-56 6.16 Shutdown and Halt.................................................................................................................... 2-65 6.17 Protection .................................................................................................................................. 2-66 6.18 Virtual 8086 Mode ....................................................................................................................
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