Three Representations of Logic Functions Logic Functions of 2 Variables

AND OR NOT X YF0F1F2F3F4F5F6F7 0 000000000 1. Logic Expression X.Y X+Y X’ X 0 100001111 ~X !X 1 000110011 2. Truth Table XYX.Y XYX+Y 1 101010101 00 0 00 0 XX' X Y F8 F9 F10 F11 F12 F13 F14 F15 0 011111111 01 0 01 1 01 0 100001111 1 0 0 1 0 1 1 0 101 0 0 0 1 1 0 0 1 1 11 1 11 1 1 101010101

3. Circuit Diagram • F1 is called a logical AND, denoted by X.Y / Schematic • F6 is called an XOR (Exclusive-OR), denoted by X ⊕ Y • F7 is called OR, denoted by X + Y • F8 is NOR, denoted by X + Y • F9 is called an XNOR (Exclusive-NOR), denoted by X ⊕ Y • F14 is NAND, denoted by X.Y 1 2

Truth Tables for 2 Variable Functions Which Truth Tables Are the Same?

1)BAF 2) ABF X Y AND X Y OR X Y XOR 000 000 0 0 0 0 0 0 0 0 0 010 010 0 1 0 0 1 1 0 1 1 101 101 1 0 0 1 0 1 1 0 1 110 110 1 1 1 1 1 1 1 1 0

X Y NAND X Y NOR X Y XNOR 0 0 1 0 0 1 0 0 1 3) BAF 0 1 1 0 1 0 0 1 0 110 1 0 1 1 0 0 1 0 0 101 1 1 0 1 1 0 1 1 1 010 000

3 4

Logic Gate Symbols Half and Full Adder Truth Tables

• AND denoted by X.Y • NAND denoted by X.Y 1)BAS 2) ABC 000 000 011 010 101 100 110 111 • OR denoted by X + Y • NOR denoted by X + Y

CBAS CBAC 0 0 0 0 0 0 0 0 • XOR denoted by X ⊕ Y • XNOR denoted by X ⊕ Y 0011 0010 0101 0100 0110 0111 • NOT denoted by X’ or X 1001 1000 1010 1011 1100 1101 1111 1111

5 6 Truth Table with Three Inputs Truth Table with Four Inputs

XYZW F • Three inputs X, Y, and Z; Output is F • Four inputs X, Y, Z, and W; Output is F 0000 0 • Logic Function: • Logic Function: 0001 0 F = 1 if and only if there is a 0 to the left of a 1 in the input F = 1 if and only if number of variables 0010 0 • Truth Table: with value 1 is more than the number of 0011 0 X Y Z F Min term variables with value 0 0100 0 0 0 0 0 • Truth Table: 0101 0 0 0 1 1 0110 0 0 1 0 1 0111 1 0 1 1 1 • Logic Expression: 1000 0 1 0 0 0 F= 1 0 1 1 1001 0 1 1 0 0 1010 0 1 1 1 0 1011 1

1100 0 • Logic Expression: 1101 1 F= 1110 1 1111 1

7 8

The Idea of Min Term / Product Term Truth Table with Two Inputs

XY F A B X Y Min Term • Two inputs X and Y; Output is F 00 1 1 0 0 0 X' Y' • Logic Function: 0 1 X' Y 01 0 0 0 F = 1 if and only if X = Y 1 0 X Y' • Truth Table: 10 0 0 0 1 1 X Y XY F Min Term

11 1 0 1 00 1 X’Y’ 01 0 X’Y • Each row in a truth table represents a unique combination of 10 0 XY’ variables 11 1 XY • Each row can be expressed as a logic combination specifying • Logic Expression: when that row combination is equal to a 1 F=X’Y’.1 + X’Y.0 + XY’.0 + XY.1 • The term is called a MIN TERM or a PRODUCT TERM =X’Y’ + XY • Thus F = A + B = X’Y’ + XY

9 10

Min / Product terms for more variables Multiplexer Circuit

XYZW Min Term s f (s, x , x ) XYZ Min Term sx x f (s, x , x ) 1 2 1 2 1 2 x 0000 X' Y' Z' W' 0 1 0 0 0 0 000 X' Y' Z' 0001 X' Y' Z' W 1 x2 001 X' Y' Z 0010 X' Y' Z W' 0 0 1 0 010 X' Y Z' 0011 X' Y' Z W 0 1 0 1 More compact truth-table representation 011 X' Y Z 0100 X' Y Z' W' 0 1 1 1 0101 X' Y Z' W 100 X Y' Z' 1 0 0 0 101 X Y' Z 0110 X' Y Z W' f=s’xf = s’.x1 +sx+ s.x2 0111 X' Y Z W 1 0 1 1 110 X Y Z' x 1000 X Y' Z' W' 1 s 111 X Y Z 1 1 0 0 1001 X Y' Z' W 1 1 1 1 1010 X Y' Z W' f x1 0 f 1011 X Y' Z W Truth Table x s 2 1 1100 X Y Z' W' x 1101 X Y Z' W 2 1110 X Y Z W' Circuit Graphical symbol 1111 X Y Z W

11 12 Canonical Sum-of-Product Expression Shorthand Notation for Canonical SOP

• A product (min) term is a unique combination of variables: • We can also assign an integer to represent each input – It has a value of 1 for only one input combination combination – It is 0 for all the other combinations of variables • Thus the function produces a 1 for input combinations 2, 4, 7 • To write an expression, we need not write the entire truth table • Therefore, the function can be written as f(x,y,z)= ∑m(2,4,7) • We only need those combinations for which function output is 1 Index for • For example, for the function below: f = x’yz’+xy’z’+xyz x y z f shorthand x y z f Min t erm notation 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 1 x’yz’ 0 1 0 1 2 0 1 1 0 0 1 1 0 3 1 0 0 1 xy’z’ 1 0 0 1 4 1 0 1 0 1 0 1 0 5 1 1 0 0 1 1 0 0 6 1 1 1 1 7 1 1 1 1 xyz

• This is called the Canonical Sum-of-Product (SOP) Expression 13 14

Max / Sum Terms Canonical Product-of-Sum Expression

• A max (sum) term is also a unique combination of variables • A function can also be written in terms of max terms – However, it is opposite of a min term • The function is product of all max terms for which function is 0 – It has a value of 0 for only one input combination • For example, the same function of three variable x, y, and z – It is 1 for all the other combinations of variables produces 0 for xyz=000, 011, 101, then – That is why it is called a max (sum) term – F = (x+y+z).(x+y’+z’).(x’+y+z’) – Each row in truth table has a max term corresponding to it • This is called the Canonical Product-of-Sum (POS) Expression • Example, a max term (x+y+z) is 0 for combination xyz=000 only • The function can also be written as F(x, y, z)= ∏ M (0,3,5) X Y Z F F’ X Y Max Term 0 0 0 0 1 F = (F’)’ 0 0 X + Y 0 0 1 1 0 = (x’y’z’ + x’yz + xy’z)’ 0 1 X + Y’ 0 1 0 1 0 = (x+y+z).(x+y’+z’).(x’+y+z’) 1 0 X’ + Y 0 1 1 0 1 1 1 X’ + Y’ 1 0 0 1 0

1 0 1 0 1 1 1 0 1 0 1 1 1 1 0

15 16

Truth Tables and Logic Expression for Adder Multiple Forms and Equivalence

A B C X Y • Canonical Sum-of-Product form X (A, B,C) = m(1,2,4,7) 0 0 0 0 0 ∑ • Canonical Product-of-sum form 0 0 1 1 0 Y(A, B,C) = ∑m(3,5,6,7) • How to convert one from other? 0 1 0 1 0 • Minterm expansion of X to minterm expansion of X’ 0 1 1 0 1 – Just take the terms that are missing 1 0 0 1 0 X (A,B,C) = ∑m(1,2,4,7) X '(A, B,C) = ∑m( ) 1 0 1 0 1 X (A,B,C) = ∏M ( ) 1 1 0 0 1 Y(A, B,C) = M ( ) • Maxterm expansion of X to maxterm expansion of X’ 1 1 1 1 1 ∏ – Just take the terms that are missing

X = A’B’C + A’BC’ + AB’C’ + ABC X (A, B,C) = ∏M ( ) X '(A,B,C) = ∏M ( ) Y = A’BC + AB’C + ABC’ + ABC

17 18 Boolean Algebra Axioms of Boolean Algebra

• An algebraic structure consists of • 1a: 0.0 = 0 – a set of elements {0, 1} – binary operators {+, .} 1b: 1+1 = 1 – and a unary operator { ’ } • 2a: 1.1 = 1 2b: 0+0 = 0 • Introduced by George Boole in 1854 • 3a:01=10=03a: 0.1 = 1.0 = 0 • An effective means of describing circuits built with switches 3b: 1+0 = 0+1 = 1 George Boole • A powerful tool that can be used for • 4a: If x=0, then x’ = 1 designing and analyzing logic circuits 1815-1864 4b: If x=1, then x’ = 0

19 20

Single-Variable Theorems Two- and Three-Variable Properties

• 5a: x.0 = 0 Null • 10a: x.y = y.x Commutative 5b: x+1 = 1 10b: x+y = y+x • 6a: x.1 = x Identity • 11a: x.(y.z) = (x.y).z Associative 6b: x+0 = x 11b: x+(y+z) = (x+y)+z • 7a: x. x = x Idempotency • 12a: x .(y+z) = xy+xzx.y + x.z Distributive 7b: x+x = x 12b: x+y.z = (x+y).(x+z) • 8a: x.x’ = 0 Complementarity • 13a: x+x.y = x Absorption 8b: x+x’ = 1 13b: x.(x+y) = x • 9: (x’)’ = x Involution

21 22

Other Properties Simplify Logic Function by Algebraic Manipulation

• Combining X Y Z F 14a: x.y+x.y’ = x • F =X’YZ+X’YZ’+XZ 0 0 0 0 14b: (x+y).(x+y’) = x =X’Y(Z+Z’)+XZ by Distributive 0 0 1 0 =X’Y(1)+XZ by Complementarity 0 1 0 1 =X’Y+XZ by Identity 0 1 1 1 • DeMorgan’s Theorem 1 0 0 0 1 0 1 1 15a: ((y)x.y)’ = x’+ y’ X 1 1 0 0 1 1 1 1 15b: (x+y)’ = x’.y’

Y • Another form of Absorption Z F=X’YZ+X’YZ’+XZ 16a: x+x’.y = x+y 16b: x.(x’+y) = x.y X Y F=X’Y+XZ Z 23 24 Principle of Duality DeMorgan’s Theorem in Terms of Logic Gates

• Dual: x x 1 x – A dual of a Boolean expression is derived by replacing . by +, 1 1 x + by ., 0 by 1, and 1 by 0 and leaving variables unchanged 2 x2 x2 – In general duality: fD(x1,x2,…,xn,0,1,+,.) = f(x1,x2,…,xn,1,0,.,+) • Principle of Duality: (a) x1 x2 = x1 + x2 – If any theorem can be proven, the dual theorem can also be proven. – A meta-theorem (a theorem about theorems) x1 • Examples: x1 x1 x – Multiplication and factoring: 2 x2 x2 • (x+y).(x’+z) = x.z+x’.y and x.y+x’.z=(x+z).(x’+y) (b) x + x = x x – Consensus: 1 2 1 2 • (x.y)+(y.z)+(x’.z)=x.y+x’z and

25 26

Using NAND to Implement SOP Using NOR to Implement POS

x1 x1 x1 x1 x x2 2 x2 x2 x x 3 3 x3 x3 x x 4 4 x4 x4 x x 5 5 x5 x5

x 1 x1 x 2 x2 x 3 x3 x 4 x4 x 5 x5 27 28

Order of Precedence of Logic Operators A Typical CAD (Computer-Aided Design) System

• From highest precedence to lowest: NOT, AND, OR Design conception • We can use parenthesis to change the order

DESIGN ENTRY • Examples: Hardware Schematic Description capture Functional f = X’+X.Y is the same as Truth table Language simulation f = ((X’)+(X.Y))

Design correct? f = X.(Y+Z) is NOT the same as Simple No Translation Yes f = X.Y+Z synthesis Logic synthesis, Merge physical design, timing simulation INITIAL SYNTHESIS TOOLS Boolean equations

29 30 Karnaugh map Location of Min-terms in K-maps x x x • Karnaugh map (K-map) allows viewing the function in a picture 1 2 3 x x form 1 2 0 0 0 m x • Containing the same information as a truth table 0 3 00 01 11 10 • But terms are arranged such that two neighbors differ in only 0 0 1 m 1 one variable 0 m 0 m 2 m 6 m 4 • It is easy to identify which terms can be combined 0 1 0 m 2 • Example: 0 1 1 m 3 1 m 1 m 3 m 7 m 5 Aith3iblA map with 3 variables A B C F 1 0 0 m 0 0 0 1 4 (b) Karnaugh map 0 0 1 1 1 0 1 m 5 AB 0 1 0 0 1 1 0 m C 00 01 11 10 0 1 1 1 6 0 1 0 1 1 1 0 0 1 1 1 1 m m2 + m6 = x1’ x2 x3’ + x1 x2 x3’ 1 1 1 1 0 7 1 0 1 0 = x2 x3’ 1 1 0 1 1 1 1 1 (a) Truth table

31 32

Simplification using K-map Examples of 3-Variable K-map

x x • Groups of ‘1’s of size 1x1, 2x1, 1x2, 2x2, 4x1, 1x4, 4x2, 2x4, or 1 2 x3 4x4 are called prime implicants (p.159 in textbook). 00 01 11 10 0 0011 AB AB fx= 1x3 + x2x3 C 00 01 11 10 C 00 01 11 10 1 1 0 01 0 1 0 1 1 0 1 0 1 1 • A ‘1’ in the 1 1 K -map1 1 can0 be used by more than1 1 one 1 group1 0 • Some rule-of-thumb in selecting groups: x1x2 – Try to use as few group as possible to cover all x 3 00 01 11 10 ‘1’s. – For each group, try to make it as large as you can 0 1111 fx= + x x (i.e., if you can use a 2x2, don’t use a 2x1 even if 1 0 0 01 3 1 2 that is enough).

33 34

Karnaugh maps with up to 4 variables K-map Example for Adder functions

• Example: 1, 2, 3, and 4 variables maps are shown below A B C S Cout S(A, B,C) = m(1,2,4,7) A AB AB ∑ A B 0 1 C 00 01 11 10 CD 00 01 11 10 0 0 0 0 0 Cout(A, B,C) = m(3,5,6,7) 0 0 0 1 0 0 1 1 1 1 00 1 1 1 1 0 0 1 1 0 ∑ 1 1 1 0 1 1 1 0 1 0 01 1 0 1 0 0 1 0 1 0 11 0 1 1 0 0 1 1 0 1 S Cout 10 0 1 1 0 100 1 0 AB AB C 00 01 11 10 C 00 01 11 10 1 0 1 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 1 1 • What if a function has 5 variables? 1 1 1 1 1

S = A’B’C + A’BC’ + AB’C’ + ABC Cout = BC + AC + AB

35 36 K-map with Don’t Care Conditions Examples

• Don’t care condition is input combination that will never occur. • Simplify the following function considering: • So the corresponding output can either be 0 or 1. – the sum-of-products form -- the product-of-sums form • This can be used to help simplifying logic functions. • Example: F(A,B,C,D)=Σ m(1,3,7,11,15)+ Σ D(0,2,5) CD CD AB 00 01 11 10 AB 00 01 11 10 CD CD AB 00 01 11 10 AB 00 01 11 10 00 1 0 0 1 00 1 0 0 1 00 d 1 1 d 00 d 1 1 d 01 1 1 1 d 01 1 1 1 d 01 0 d 1 0 01 0 d 1 0 11 0 d 1 1 11 0 d 1 1 11 0 0 1 0 11 0 0 1 0 10 0 0 0 1 10 0 0 0 1 10 0 0 1 0 10 0 0 1 0

F = CD+A’B’ F = CD+A’D d: Don’t Care Condition 37 38

1-bit building blocks to make n-bit circuit Full adder & multi-bit ripple-carry adder

4-bit ripple-carry adder • Design a 1-bit circuit with proper “glue logic” to use it for n-bits • Two half adders can be used to add 3 bits – It is called a bit slice • n-bit adder can be built by full adders A3 – The basic idea of bit slicing is to design a 1-bit circuit and Full Cout3 • n can be arbitrary large B3 then piece together n of these to get an n-bit component C3 Adder Sum3 Half Adder C B A B • Example: A2 Full Cout2 • AhA ha lf-adder add s t wo 1 -bit i nput s A B B2 C2 Adder Sum2 • Two half adders can be used to add 3 bits AB S C CSCS • A 3-bit adder is a full adder 00 00 A1 Cout1 • A full adder can be a bit slice 01 10 CS Cout B1 Full Sum1 to construct an n-bit adder A B 10 10 C1 Adder 11 01 Sum A Cout A0 Cout0 Half Adder B Full B0 Full CS Adder Sum0 C Adder Sum Ci 39 40

Multiple Function Unit Design ADD/SUB unit design

• Design a unit that can do more than one function • Separate ADD and SUB units are expensive • In that case, we can design a function unit for each operation like • We can simplify the design ADD, SUB, AND, OR, .... • A - B is the same as adding negation of B to A • And then select the desired output • How to negate? • For example, if we want to be able to perform ADD and SUB on – 2’s complement (i.e., take 1’s complement and add 1) two given operands A and B, and select any one – Adding 1 is also expensive • Then the following set up will work – It needs an n-bit adder in general – However, we only need to add two bits in each stage A • In the first stage, we need to add 1’s complement of LSB and 1 ADD • In other stages, we need to add carry output of previous bit to 1’s complement of current bit B MUX A • We select B or negation of B depending on the requirement Result SUB • We add A to the selected input to obtain the result B Select 41 42 Multiplexing and Multiplexer Multiplexer Implementation

• Multiplexers are circuits which select one of many inputs • In here, we assume that we have one-bit inputs • We can write a logic expression for output F as follows (in general, each input may have more than one bit) F = X’ Y’ Z’ I0 + X’ Y’ Z I1 + X’ Y Z’ I2 + X’ Y Z I3 + X Y’ Z’ I4 + X Y’ Z I5 + X Y Z’ I6 + X Y Z I7 • Suppose we have eight inputs: I0, I1, I2, I3, I4, I5, I6, I7 • This circuit can be implemented using • We want one of them to be output based on selection signals – eight 4-input AND gates and one 8-input OR gates • 3 bits of selection signals to decide which input goes to output • Note the order of selection signals X Y Z F X Y Z F – X is MSB and Z is LSB 0 0 0 I0 I0 I1 I2 I3 I4 I5 I6 I7 0 0 0 I0 8-to-1 Multiplexer 0 0 1 I1 0 0 1 I1 0 1 0 I2 X S2 0 1 0 I2 I0 I1 I2 I3 I4 I5 I6 I7 0 1 2 3 4 5 6 7 0 1 1 I3 Y S1 0 1 1 I3 1 0 0 I4 Z S0 F 1 0 0 I4 X S2 0 1 2 3 4 5 6 7 1 0 1 I5 Y S1 1 0 1 I5 1 1 0 I6 1 1 0 I6 Z S0 F 1 1 1 I7 1 1 1 I7

43 44

Implementing 4-to-1 MUX using 2-to-1 MUXs Making a 2-bit 4-to-1 Multiplexer

I0 I1 I2 I3 • Four 2-bit inputs A, B, C, D • One 2-bit output F ABCD • Two bits of selection signal X Y 0 1 0 1 S0 S0 2x1 MUX S0 S0 2x1 MUX X Y F 0 0 A 01B 1 0 C X 0 1 2 3 0 1 2 3 1 1 D Y 0 1 4-1 4-1 X S1 X S1 S1 S0 2x1 MUX MUX MUX S0 S0 Y F Y F

F 45 46

Synthesis of Logic Functions using Multiplexers Implementing 3-variable functions with 4x1 MUX

• Multiplexers can be directly used to implement a function • Divide the outputs into 4 groups based on X and Y. • Easiest way is to use function inputs as selection signals • Write the outputs as a function of Z • Input to multiplexer is a set of 1s and 0s depending on the • There are only 4 possibilities: F=Z, F=Z’, F=0, F=1 function to be implemented • We use a 8-to-1 multiplexer to implement function F X Y Z F • Three select signals are X, Y, and Z, and output is F 0 0 0 0 ZZ’01 X Y Z F F=Z • Eight inputs to multiplexer are 101011001 0 1 0 1 1 0 0 0010 0 1 1 • Depending on the input signals 0 0 0 1 0 1 0 1 0 1 2 3 0 0 1 0 F=Z' S1 – multiplexer will select proper output 0 1 1 0 X 4x1 MUX 0 1 0 1 1 0 0 0 Y S0 F=0 10101100 0 1 1 0 1 0 1 0 1 0 0 1 1 1 0 1 F X S2 1 0 1 1 1 1 1 1 F=1 0 1 2 3 4 5 6 7 Y S1 1 1 0 0 Z S0 F 1 1 1 0

47 48 Implementing 4-variable functions with 8x1 MUX Implementing 4-variable functions with 4x1 MUX

A B C D F A B C D F 0 0 0 0 0 0 0 0 0 0 F=D 0 0 0 1 1 0 0 0 1 1 F=D C D C D 0 0 1 0 0 0 0 1 0 0 F=D 0 0 1 1 1 DDD’00 D1 1 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 F=D’ 0 1 0 1 0 0 1 0 1 0 F=C’D’ 01100 1 1 0 0 A S2 012345670 1 2 3 4 5 6 7 01100 1 1 0 0 D 1 F=0 S1 0 1 1 1 0 B 8x1 MUX 0 1 1 1 0 C S0 1 0 0 0 0 1 0 0 0 0 F=0 0 1 2 3 1 0 0 1 0 1 0 0 1 0 F=CD A S1 1 0 1 0 0 F 1 0 1 0 0 4x1 MUX F=D B S0 1 0 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 0 1 F=1 F 1 1 0 1 1 1 1 0 1 1 F=1 1 1 1 0 1 1 1 1 0 1 F=1 1 1 1 1 1 1 1 1 1 1

49 50

Implementing 4-variable functions with 4x1 MUX Definition of Decoder

A B C D F • Suppose we have n input bits (which can represent up to 2n 0 0 0 0 0 distinct elements of coded information). 0 0 0 1 0 n F= • We need a device that allows us to select which of the 2 0 0 1 0 0 elements, devices, memory locations, etc. is being selected. 0 0 1 1 0 • In general: 0 1 0 0 0 – A decoder has n input bits 0 1 0 1 0 F= n 01100 1 1 0 0 – A decoder has 2 (or less) output bits 0 1 1 1 1 – As a rule, all but one of the outputs is zero (deselected) at 1 0 0 0 0 0 1 2 3 any time (called one-hot encoded) 1 0 0 1 0 S1 F= A 4x1 MUX 1 0 1 0 1 B S0 1 0 1 1 1 1 1 0 0 0 F 1 1 0 1 1 F= 1 1 1 0 1 1 1 1 1 1

51 52

2-to-4 Decoder Definition of Encoder

• The 2-to-4 decoder is a block which decodes the 2-bit binary • Encoders perform the inverse function of Decoders. inputs and produces four outputs • An encoder has 2n (or less) input bits and n output bits • One output corresponding to the input combination is a one • The output bits generate the binary code corresponding to the • Two inputs and four outputs are shown in the figure input value • The equations are • Assuming only one input has a value of 1 at any given time y0 – y0 = x1’. x0’ x1 • Example: An 8-to-3 Encoder y1 – y1 = x1’. x0 2-to-4 Inputs Outputs – y2 = x1 . x0’ x0 decoder y2 D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 y3 – y3 = x1 . x0 00000001000 00000010001 • The truth table: A2=D4+D5+D6+D7 x1 x0 y3 y2 y1 y0 00000100010 A1=D2+D3+D6+D7 000001 00001000011 A0=D1+D3+D5+D7 010010 00010000100 00100000101 100100 01000000110 111000 10000000111 53 54 What are the outputs of the following circuits? Priority Encoders

• Each input signal has a priority level associated with it • May have more than one 1’s in the input signals y0 • Outputs indicate the active input that has the highest priority x1 a1 • Example: 4-to-2 priority encoder 2-to-4 y1 4-to-2 y2 – Assume w3 has the highest priority and w0 the lowest x0 decoder encoder a0 – y1 y0 indicate the active input with highest priority y3 – z indicates none of the inputs is equal to 1 w3 w2 w1 w0 y1 y0 z Let i0 = w0 w1’ w2’ w3’ 0000dd0 y0 b0 i1 = w1 w2’ w3’ x1 0001001 i2 = w2 w3’ y1 b1 4-to-2 2-to-4 001x011 i3 = w3 y2 encoder decoder b2 x0 01xx101 Then y0 = i1 + i3 y3 b3 1xxx111 y1 = i2 + i3 x: both 0 and 1 (irrelevant) 55 56

Decoder with Enable Truth Table for 2-to-4 Decoder with Enable

x1 x0 E y3 y2 y1 y0 • A 2-to-4 decoder can be designed with an enable signal • If enable is zero, all outputs are zero 0000000 • If enable is 1, then an output corresponding to two inputs is a 0010001 one, all others are still zero 0100000 • The equations are – y0 = x1’. x0’. E E 0110010 – y1 = x1’. x0 . E 1000000 y0 – y2 = x1 . x0’. E x1 1010100 – y3 = x1 . x0 . E y1 2-4 decoder 1100000 x0 y2 y3 1111000

57 58

Demultiplexers 3-to-8 decoder using a 2-to-4 decoder with Enable

• Perform the opposite function of multiplexers • The 3-to-8 decoder can be implemented using two 2-to-4 • Placing the value of a single data input onto one of the multiple decoders with enable and one NOT gate data outputs • The implementation is as shown • Same implementation as decoder with enable • Enable input of decoder serves as the data input for the x2 E demultiplexer y0 x1 D y1 2-4 decoder y2 y0 x0 x1 y3 y1 E 2-4 DEMUX y4 x0 y2 y3 y5 2-4 decoder y6 y7

59 60 Verilog HDL Verilog Syntax

Popular Hardware Description Languages (HDLs): • Module / Signal names: • Verilog HDL – Start with a letter – More popular with US companies – Follow by any sequence of letter, number, _ and $ – Similar to C / Pascal programming language in syntax – Case sensitive • VHDL • Comment by // or /* */ – More popular with European companies • White spaces (SPACE, TAB, blank line) are ignored. – Simil ar t o Ad a programmi ng l anguage i n synt ax // An example module example1 (x1, x2, x3, f); – More “verbose” than Verilog input x1, x2, x3; // An example output f; module example1 (x1, x2, x3 Uses of Verilog: , f);input x1, x2, x3;output and (g, x1, x2); • Synthesis f;and (g, x1, x2); not (k, x2 not (k, x2); );and (h, k, x3); or (f, g, • Simulation and (h, k, x3); h);endmodule • Verification or (f, g, h); endmodule 61 62

Structural Specification of Logic Circuit Another Example of Structural Specification

module example1 (x1, x2, x3, f); module example2 (x1, x2, x3, x4, f, g, h); input x1, x2, x3, x4; x1 input x1, x2, x3; x output f, g, h; g 3 x1 output f; x g 2 x and (z1, x1, x3); 2 and (z2, x2, x4); f and (g, x1, x2); x4 k not (k, x2); or (g, z1, z2); x f or (z3, x1, ~x3); 3 h and (h, k, x3); or (z4, ~x2, x4); or (f, g, h); and (h, z3, z4); h or (f, g, h); endmodule endmodule

63 64

Behavioral Specification Behavioral Specification Continuous Assignment Procedural (Sequential) Statement

x g x1 1 x x2 2 f f k module example5 (x1, x2, x3, f); k input x1, x2, x3; x h x3 h 3 output f; Declared as variable (register) if assigned // Structural Specification // Behavioral Specification reg f ; module example1 (x1, x2, x3, f); module example3 (x1, x2, x3, f); a valilue in a proced ural statement input x1, x2, x3; input x1, x2, x3; output f; output f; always @(x1 or x2 or x3) Sensitivity list if (x2 == 1) and (g, x1, x2); assign f = (x1 & x2) | (~x2 & x3); f = x1; always block not (k, x2); else and (h, k, x3); endmodule f = x3; or (f, g, h);

endmodule Concurrent statement endmodule 65 66