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Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications

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Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications Journal of Signal and Information Processing, 2012, 3, 122-129 http://dx.doi.org/10.4236/jsip.2012.31016 Published Online February 2012 (http://www.SciRP.org/journal/jsip) Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications Mohamed Atri, Fatma Sayadi, Wajdi Elhamzi, Rached Tourki Electronics and Microelectronics Laboratory, Faculty of Sciences, University of Monastir, Monastir, Tunisia. Email: {Mohamed.Atri, Rached.Tourki}@fsm.rnu.tn, {Sayadi_Fatma, Elhamziwajdi}@yahoo.fr Received January 2nd, 2011; revised September 14th, 2011; accepted November 3rd, 2011 ABSTRACT The LPC “Linear Predictive Coding” algorithm is a widely used technique for voice coder. In this paper we present different implementations of the LPC algorithm used in the majority of voice decoding standard. The window- ing/autocorrelation bloc is implemented by three different versions on an FPGA Spartan 3. Allowing the possibility to integrate a Microblaze processor core a first solution consists of a pure software implementation of the LPC using this core RISC processor. Second solution is a pure hardware architecture implemented using VHDL based methodology starting from description until integration. Finally, the autocorrelation core is then proposed to be implemented using hardware/software (HW/SW) architecture with the existing processor. Each architecture performances are compared for different data lengths. Keywords: Linear Predictive Coding; System on Programmable Chip; FPGA; Co-Design 1. Introduction ferent versions on an FPGA. The system performances have been evaluated with a prototyping board integrating Applications such as cell phones, hearing aids, and digi- embedded Microblaze processor with peripherals on a tal audio devices are applications with stringent con- FPGA Spartan 3. This flexible system enables to reduce straints such as area, speed and power consumption. These overall product cost, achieve target performances, elimi- complex applications can be well addressed by Systems nate risk of obsolescence and finally use industry stan- on Programmable Chip (SoPC). Modern Field Program- dard software development [2]. Pure software imple- mable Gate Arrays (FPGAs) contain many resources that mentation of the LPC is first proposed using MicroBlaze support DSP applications such as embedded multipliers, soft core RISC processor. Second pure hardware archi- Multiply Accumulate (MAC) units and processor cores. tecture is implemented using VHDL description. Finally, The motivation for the introduction of such processor the autocorrelation core is then proposed to be imple- core comes from the idea that most FPGAs contained mented using HW/SW architecture with the existing within an embedded system require interaction level with processor. Each architecture performances are compared an external processor. Moving this processor onto the for different data lengths. The remainder of this paper is chip allows the FPGA and the processor to communicate organized as follows: Section 2 gives a necessary back- without the bottlenecks associated to communicating ground on the LPC analysis and the autocorrelation algo- with off-chip devices. Several programmable logic ma- rithm. The starter board and implementation tools are nufacturers offer FPGAs platform. Altera, Atmel, Xilinx detailed in Section 3. Section 4 introduces the Micro- [1] propose devices that integrate hardware cores of blaze processor. Each architecture implementation details processors such as ARM, MIPS and PowerPC CPUs and/ are depicted in Section 5. Section 6 presents the imple- or allow instantiation of soft processor such as Micro- mentation results. Finally Section 7 concludes the paper Blaze from xilinx and Nios from Altera, DSP and mi- and details some future works. crocontroller cores like PicoBlaze. In this work, we pro- pose different implementation modes of the Linear Pre- 2. LPC Algorithm Overview dictive Coding (LPC) algorithm used in the majority of voice decoding standard. According to its criticality of The LPC algorithm is a widely used technique for voice the LPC algorithm and its reusability property, the win- coder. In fact the human speech is produced in the vocal dowing/autocorrelation bloc seems a good candidate for tract as a combination of vocal cords (in glottis) interact- IP design. This block is thus implemented by three dif- ing with articulators. Actually, it can be modeled by the Copyright © 2012 SciRes. JSIP Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications 123 passage of an excitation signal through a filter. This mo- del called linear predictive coding (LPC) is given in the case of an auto-regressive signal [3,4] and is presented in Figure 1(a). The correspondence between the real world and the mathematical models is given in Figure 1(b) [5,6], This is equivalent to say that the input-output relationship of the filter is given by: Guz sz (1) Az In order to evaluate the LPC model, the linear regres- sion has to be solved, that is to say the coefficients a(i) of the recursive filter are to be found. If the operations in- volved by the LPC analysis are summed-up, this task includes five sub-tasks: A windowing + an autocorrelation, The Levinson Durbin algorithm [7,8], A LP to LSP Conversion [9,10], A LSP Quantization [11], Figure 1. LPC model. Interpolation & conversion of the LSP coefficients. 3 Starter Kit provided by Xilinx [2]. 3. Implementation Approach 3.2. Board and Embedded Processor In order to extract an efficient hardware/software parti- tioning, the processing and communication complexity of The Spartan-3 Starter Board from Xilinx provides a po- the LPC algorithm was evaluated in [12]. A survey of the werful, self-contained development platform for designs. distribution of the different processing complexity parts It features a 200 K gate Spartan-3, on-board I/O devices, of the algorithm is necessary. The aim is to first know to and one MicroBlaze fast asynchronous SRAM, making it what extent it can be interesting to achieve some blocks the perfect platform to experiment with any new design, into hardware rather than software and, secondly, if this from a simple logic circuit to an embedded processor blocks can be used in other applications in order to jus- core. The board also contains a Platform Flash JTAG- tify their specification as a reusable component. programmable ROM, so designs can easily be made non- volatile. The Spartan-3 Starter Board is fully compatible 3.1. Hardware/Software Partitions with all versions of the Xilinx ISE tools. It ships with a power supply and a programming cable, so designs can The windowing/autocorrelation block and the LSP Quan- be implemented immediately with no hidden costs. tization block are the most critical blocks. The technique used for the quantization is specific to the standard G729. Figure 2 shows the Spartan-3 Starter Kit board, the In fact the LSP coefficients are quantized using the LSF main components and features are quoted below: (line spectral frequency) representation in the normalized 200,000-gate Xilinx Spartan-3 XC3S200 FPGA; frequency domain (0, π). Then the quantization is achieved 1M-byte of Fast Asynchronous SRAM; using a two-stage vector quantizer [13]. In fact, rather 3-bit, 8-color VGA display port; than doing the computations, most voice coder use a sim- 9-pin RS-232 Serial Port; ple look-up table. This solution can be efficiently imple- PS/2-style mouse/keyboard port; mented into software. This is the way we have imple- Four-character, seven-segment LED display; mented this block. The other significant sub-block, the Eight slide switches; autocorrelation sub-block, is data computation dominated. Eight individual LED outputs; We thus decided to centres round this block. In fact the Four momentary-contact push button switches. critical operations of the majority of digital signal pro- The implementation of our system will be carried out cessing algorithms are usually the convolution or product using XPS tool (Xilinx Platform Studio) provided by accumulations. A dedicated arithmetic unit achieving a EDK [14] environment (Embedded Development Kits) multiplication and accumulation is generally used to cope as well as the Core Generator tools included in ISE (in- with this problem; it is called a MAC. tegrated software environment), to profit from Xilinx IP To achieve our objectives, we have used the Spartan™- [15] respecting the constraint of time to market (TTM). Copyright © 2012 SciRes. JSIP 124 Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications Figure 2. Spartan-3 starter board. The Spartan 3 starter kit which combines XC3S200 of implementation. The high-pass filter serves as a precau- Spartan 3 FPGA family, provides an environment for tion against undesired low-frequency components. A se- designing an embedded and reconfigurable system based cond order pole/zero filter with a cut-off frequency of on the MicroBlaze softcore processor. 140 Hz is used. The MicroBlaze embedded soft core is a Reduced In- The Linear Prediction (LP) is performed once per struction Set Computer (RISC) optimized for implemen- speech frame using the autocorrelation method with a 30 tation in Xilinx FPGAs. With few exceptions, the Mi- ms asymmetric window. Every 80 samples (10 ms), the croBlaze can issue a new instruction every cycle, main- autocorrelation coefficients of windowed speech are taining single-cycle throughput under most circum- computed and converted to the LP coefficients using the stances. Unlike any other hard processors which are ac- Levinson algorithm. tually implemented in the FPGA at a transistor level, the The LP analysis window consists of two parts: the first soft core is an IP block written in HDL and is imple- part is half a Hamming window and the second part is a mented in the free resources of an FPGA. Therefore it is quarter of a cosine function cycle. The window is given configurable by choosing the components that would be by: included in the system. According to the application type, MicroBlaze proce- 2πn 0.54 0.46cosn 0, ,199 ssor can be configured in several ways to save power or 399 area.
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