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Computer Architecture: from the Orthogonal Valuation of Names up to Structuring the N-Stream

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Computer Architecture: from the Orthogonal Valuation of Names up to Structuring the N-Stream ¢¡¢£¥¤§¦©¨¢ £ ¦¦¦¡¦¤¦ "!¦#¦$ % &'£(¦¡§¦© IKJ LINM )+*-,/.102)435)46708:9<;=6?>A@/.B3C,D02;FEG?) @H+02)+G&. )4.O;F02;F)4. ! ! P IS'T .B@/>A)+QBQO)4G&.¢R @U*&,/.B8 WVXYP ¦©¨Z§¨M¢£ ¦©' ¨¦W[ \¨WVX] M¢¦#V¨\ M§V^V¡§_¤\ ` a W£1V¡bV"¡¢§XY¦© ¢Pc Vd ¨' §' ¨£(¡§d M¢¦¡J( ¨¢¦a§X Me¦© ?¦ *&. )+QB)+6f0 )4) ,hg=, ,/H4G&gi0 )8&)+QQBH4;F)46&H+)4Q¢8&)gj9 6&;ikU)4.OQB;i0 )8&) )46 )lkU) ! ! ! ! *S@UG&.W@/m?02)+6&;=.WgF)nU.2,/8?)^8?) @H+0B)4G&. )+QQBH4;F)46&H+)4Q+op35)46702;F@U6q;=6 >[email protected],D02;FEfG&) *-,/. r J( s§\£ W ¦ )4,/6 @UG?;=Q 8&) ¦©w ,/6&Hltvu WT ¡5x y/zf{/| )+QB) ¦¡ ¦¤¦ {/|U|7{ Computer Architecture: from the orthogonal valuation of names up to structuring the N-stream Jean-Louis Lafitte Universite´ de Genev` e 29 novembre, 2002 ¡ lafi[email protected] 1 2 Remercˆıments It is with quite a genuine gratitude that the author wants to thank people that brought ideas, encour- agements or managerial support for this thesis to be achieved. As the covered subject has started some 26 years ago, (actually sometime in 1976) ... there has been a lot of people that through reflexions comments and criticisms has largely contributed (sometime without knowing it) to this document, hence the real danger of forgetting some of them: High level thinkers of whom I have greatly benefited: Michael Flynn (designer of the IBM 91, whose opinion on the taxonomic part of this study has been a great encouragement), Rip Parmelee a great pointure originally from the IBM Cambridge Scientific Center. Inspirational authors Dick Attanasio (father of VCS), Robert P. Goldberg (the ’72 Harvard PhD of whom, has sparked this study off) and Stretch design folks (whose veterans meeting was held in Pok, this past September). Strong managerial support with which I was privileged to relate to (along the time arrow): F.-H. Raymond, Bobby Lie, J.-J. Duby P.-A. Bobillier, and my thesis directors Bastien Chopard and C.-A. Heritier, whose perseverance, criticisms and encouragements contributed a lot to reach this final stage. On-this-side-of-the-ocean IBM colleagues for their friendship: Guy Anastaze, Maurice Bellot, Pierre Boudet, Pasquale di Cesare, Claude Hans, J.-P. Joly. Skilled physicists and computing practitioners met at CERN: Rene´ Brun, Federico Carminati, Sverre Jarp, Eric McInstosh, Harry Renshall, Paolo Zanella and Rob Veenhof (who con brio swal- lowed the subject of this topics to the point of becoming a brilliant member of the jury). Some twenty years ago, thanks to Jacques Maisonrouge, I had the unique opportunity, in my pro- fessional life, to work with (or along) actual designers and architects from whom I learned a lot as a junior in their midst (in alphabetical order): George H. Bean, Henry Brandt, David Breslford, Justin Butwell, Al Ganek, Pete Gum, Roger Hough, Brian Moore, Andris Padegs, Ron Smith, Pete H. Tallman, Joel Tendler, Julian Thomas, Les Wyman, and more generally folks in 705 and 707 Buildings. Don H. Gibson, an upright fair-demanding (and -rewarding) old timer of the Mid-Hudson Valley, father of the Muffer. Cas Scalzi, a unique designer, bottleneck predictor (and solver), in other terms ... an intuitive fore- designer of great talent, I had the great privilege to know. Enthusiastic and warm supporting fellows, known along those years: Roland Caris and Michel Rothlisber¨ ger. Colleagues who, during dark years at work, have shown good heart to little me as I was convicted of rawing in their midst, thank you so much Claude Alaphilippe and Jules Margerin. My wife Corinne and our direct family for their unfailing steadfast love and support during all those long years. 3 4 5 6 Resum´ e´ de la these:` combler les hiatus... D’une maniere` toute concrete,` le modele` dev´ eloppe´ dans le cadre de ce projet a` l’Universite´ de Genev` e nous permet de considerer´ le traitement des donnees´ irreguli´ eres` dans un environnement parallele.` Cela permet d’accomplir un traitement parallele` ’data-driven’, comportant beaucoup moins de discontinuites´ dans les techniques de ’pipelines’. Ce modele` qui propose d’ameliorer´ les processeurs tant CISC, Vector, RISC, Superscalar, VLIW, que MPP, semble repondre´ aux besoins de ce qu’on nomme High Performance Computing (HPC), tout en offrant aussi ses ben´ efices´ a` tout contexte comportant de larges structures d’index, tel celui des Gestionnaires de Banques de Donnees´ Relationnelles, ou exploitant la technique des fichiers inverses,´ etc .., En effet, il devrait permettre de combler certains des hiatus (ou ecarts)´ qui existent dans un systeme` informatique, et qui ont et´ e´ le souci quasi-constant des concepteurs d’ordinateurs depuis plusieurs decennies.´ Ces hiatus sont represent´ es´ dans la Figure 1: 3rd str. semantic gap 3rd str. semantic gapCISC RISC HLL node A Xme AI D-cache Xc N-cache I-cache memory gap Memory DASD I/O gap node B communication gap Memory Xme: mechanical (algorithmic) automaton Xc: newly proposed engine Figure 1: Combler les hiatus 7 Ces hiatus sont: ¢ Le hiatus semantique´ (semantic gap) caracteris´ e´ par l’ecart´ entre les langages de program- mation et le jeu d’instructions disponible, ecart´ exacerbe´ par la technologie RISC ... et comble´ par les techniques de compilation. Ce hiatus a et´ e´ reduit,´ tant dans le cas des envi- ronnements CISC que RISC, par: 1. le dev´ eloppement des structures superscalaires dans la technologie RISC, 2. la mise a` disposition du calcul vectoriel dans les environnements CISC. Les techniques d’Intelligence Artificielle (IA) sont, pour leur part, tellement eloign´ ees,´ semantiquement´ parlant, des processeurs, que rien, pour ainsi dire, n’a et´ e´ entrepris en vue de combler ce hia- tus (en dehors du projet de Vth Generation, tres` mediatis´ e´ a` l’epoque).´ ¢ Le hiatus memoir´ e (memory gap) qui se situe entre processeur et memoire,´ est le sujet de nombreuses analyses dans le cadre de notre travail. Plusieurs techniques ont et´ e´ utilisees´ dans le passe´ pour tenter de le combler: 1. Elargir le systeme` d’adressage de 8 a` 16 a` 32 a` 64 bits, a et´ e´ un des moyens les plus courants. 2. Des mecanismes´ de cache de plus en plus large, implement´ es´ selon des structures Princeton puis Harvard, ont et´ e´ l’autre moyen prev´ alent. 3. Accroˆıtre le nombre de registres dans les environnements RISC. ¢ Le hiatus des Entree/Sortie´ (I/O gap) a et´ e´ traite´ de differentes´ manieres:` 1. L’architecture de l’IBM System/360 a introduit des Channel Command Words (CCWs) pour controlerˆ les operations´ d’Entree/Sortie´ et leurs sequences´ [5]. Plus tard, au cours de l’ev´ olution de cette architecture, un systeme` d’adressage indirect, CCW Indirect Data Addressing, permit a` un seul CCW de ref´ erencer´ des pages noncontigues¨ en memoire´ centrale; mais ce fut tout, en ce qui concerne le phenom´ ene` d’indirection et l’accent qu’il met sur le hiatus des Entree/Sortie.´ 2. Les single-level store machines, tel l’IBM System/38, permettent aux programmeurs de ne pas avoir a` acceder´ les donnees´ dans des fichiers: les donnees´ sont directement accessibles, d’une maniere` simple, dans l’espace d’adressage mis a` disposition. Une telle approche continue grandement a` reduire´ le hiatus d’Entree/Sortie´ . 3. Les workstations RISC et les PCs possedent,` la plupart du temps, des portes (ports en langue anglaise) ou des out interrupts au travers desquelles les operations´ d’Entree/Sortie´ sont effectuees.´ Le hiatus des Entree/Sortie´ est gigantesque pour ces deux environnements. 4. Des architectures plus recentes,´ comme le systeme` RISC/6000 SP, permettent des systemes` de fichiers paralleles.` Les specifications´ de MPI-2 [118] qui viennent recemment´ d’etreˆ publiees´ constituent 8 en fait un standard gen´ eralisant´ un ensemble de fonctions equi´ valentes, connues sous le nom de MPI-I/O. ¢ Le hiatus de communication entre multiprocesseurs, processeurs paralleles` ou clusters (desormais´ denomm´ e´ ’hiatus de communication’) a et´ e´ traite´ jusqu’alors de differentes´ manieres:` 1. Les bibliotheques` de messages (en particulier le standard emer´ gant connu sous le nom de Message Passing Interface ou MPI) ont tente´ d’emplir ce hiatus en fournissant des fonctions beaucoup plus sophistiquees´ que les simples primitives send/receive. 2. Les Acces` Non-Uniformes a` la memoire´ (Non-Uniform Memory Access, abreg´ e´ NUMA) representent´ une autre tentative pour prendre en compte ce hiatus. 3. Nous traitons aussi du cas de High Performance Fortran (HPF en abreg´ e)´ qui a con- tribue´ a` sa maniere` a` combler le hiatus de communication en permettamt de distribuer des donnees´ sur des noeuds, le traitement reel´ n’ayant lieu qu’en fonction de la localite´ des donnees.´ C’est par l’introduction d’un troisieme` flot d’informations dans le modele` de base de von Neumann (comportant un flot d’instructions et un flot de donnees,´ SISD), que l’on propose d’approcher ces difficultes.´ Le flot, que l’on nommera flot N, ou flot de noms, sera associe,´ comme les deux premiers, a` un cache permettant d’ameliorer´ les performances gen´ erales.´ On parlera donc du N-Stream et de son buffer dote´ d’une structure et d’un fonctionnement adaptes´ de type Shemot. Grace,ˆ tant a` la fois au N-Stream parametrable´ qu’au cache de type Shemot, le modele` propose´ devrait ainsi nous permettre de reduire´ passablement le hiatus memoire.´ ¢ Il est aussi a` prev´ oir que notre modele` puisse aider a` reduire´ le hiatus tant des Entree/Sortie´ que celui de communication. Les etudes´ correspondantes devraient etreˆ entamees´ dans ces directions. ¢ De plus amples etudes´ devraient aussi etreˆ menees´ pour prendre en compte la partie la plus large de ce hiatus, celle due au traitement symbolique.
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