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Intel Xscale® Core Intel XScale® Core Developer’s Manual January, 2004 Order Number: 273473-002 Intel XScale® Core Developer’s Manual Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel® internal code names are subject to change. THIS SPECIFICATION, THE Intel XScale® Core Developer’s Manual IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. Copyright © Intel Corporation, 2004 AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. The ARM* and ARM Powered logo marks (the ARM marks) are trademarks of ARM, Ltd., and Intel uses these marks under license from ARM, Ltd. *Other names and brands may be claimed as the property of others. 2 January, 2004 Developer’s Manual Intel XScale® Core Developer’s Manual Contents Contents 1 Introduction....................................................................................................................................13 1.1 About This Document .........................................................................................................13 1.1.1 How to Read This Document.................................................................................13 1.1.2 Other Relevant Documents ...................................................................................14 1.2 High-Level Overview of the Intel XScale® Core..................................................................15 1.2.1 ARM Compatibility .................................................................................................15 1.2.2 Features.................................................................................................................16 1.2.2.1 Multiply/Accumulate (MAC)....................................................................16 1.2.2.2 Memory Management ............................................................................17 1.2.2.3 Instruction Cache ...................................................................................17 1.2.2.4 Branch Target Buffer..............................................................................17 1.2.2.5 Data Cache ............................................................................................17 1.2.2.6 Performance Monitoring.........................................................................18 1.2.2.7 Power Management...............................................................................18 1.2.2.8 Debug ....................................................................................................18 1.2.2.9 JTAG......................................................................................................18 1.3 Terminology and Conventions ............................................................................................19 1.3.1 Number Representation.........................................................................................19 1.3.2 Terminology and Acronyms ...................................................................................19 2 Programming Model ......................................................................................................................21 2.1 ARM Architecture Compatibility ..........................................................................................21 2.2 ARM Architecture Implementation Options.........................................................................21 2.2.1 Big Endian versus Little Endian .............................................................................21 2.2.2 26-Bit Architecture .................................................................................................21 2.2.3 Thumb....................................................................................................................21 2.2.4 ARM DSP-Enhanced Instruction Set .....................................................................22 2.2.5 Base Register Update............................................................................................22 2.3 Extensions to ARM Architecture .........................................................................................23 2.3.1 DSP Coprocessor 0 (CP0).....................................................................................23 2.3.1.1 Multiply With Internal Accumulate Format .............................................24 2.3.1.2 Internal Accumulator Access Format .....................................................27 2.3.2 New Page Attributes ..............................................................................................29 2.3.3 Additions to CP15 Functionality.............................................................................31 2.3.4 Event Architecture .................................................................................................32 2.3.4.1 Exception Summary...............................................................................32 2.3.4.2 Event Priority..........................................................................................32 2.3.4.3 Prefetch Aborts ......................................................................................33 2.3.4.4 Data Aborts ............................................................................................34 2.3.4.5 Events from Preload Instructions ...........................................................35 2.3.4.6 Debug Events ........................................................................................36 3 Memory Management....................................................................................................................37 3.1 Overview.............................................................................................................................37 3.2 Architecture Model..............................................................................................................38 3.2.1 Version 4 vs. Version 5..........................................................................................38 3.2.2 Memory Attributes..................................................................................................38 3.2.2.1 Page (P) Attribute Bit .............................................................................38 Developer’s Manual January, 2004 3 Intel XScale® Core Developer’s Manual Contents 3.2.2.2 Cacheable (C), Bufferable (B), and eXtension (X) Bits.......................... 38 3.2.2.3 Instruction Cache...................................................................................38 3.2.2.4 Data Cache and Write Buffer.................................................................39 3.2.2.5 Details on Data Cache and Write Buffer Behavior................................. 40 3.2.2.6 Memory Operation Ordering ..................................................................40 3.2.3 Exceptions .............................................................................................................40 3.3 Interaction of the MMU, Instruction Cache, and Data Cache .............................................41 3.4 Control ................................................................................................................................42
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