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Peripheral Interface Adapter (PIA) W65C21S The Western Design Center, Inc. W65C21S Data Sheet Peripheral Interface Adapter (PIA) W65C21S The Western Design Center W65C21S 1 The Western Design Center, Inc. W65C21S Data Sheet WDC reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Information contained herein is provided gratuitously and without liability, to any user. Reasonable efforts have been made to verify accuracy of the information but no guarantee whatsoever is given as to the accuracy or as to its applicability to particular uses. In every instance, it must be the responsibility of the user to determine the suitability of the products for each application. WDC products are not authorized for use as critical components in life support devices or systems. Nothing contained herein shall be construed as a recommendation to use any product in violation of existing patents or other rights of third parties. The sale of any WDC product is subject to all WDC Terms and Conditions of Sales and Sales Policies, copies of which are available upon request. Copyright (C) 1981-2005 by The Western Design Center, Inc. All rights reserved, including the right of reproduction in whole or in part in any form. The Western Design Center W65C21S 2 The Western Design Center, Inc. W65C21S Data Sheet DESCRIPTION • Low Power CMOS N-well silicon gate technology The WDC W65C21S is a very flexible Peripheral Interface • High speed/Low power replacement for Adapter (PIA) for use with WDC’s 65xx and other 8-bit Motorola/Rockwell/AMI/MOS microprocessor families. The W65C21S provides Technology/MOSTEK/HITACHI/ ST programmed microprocessor control of up to two peripheral Microelectronics/GTE/CMD 6520, 6521, 6820, devices (Port A and Port B). Peripheral device control is 6821 PIA’s accomplished through two 8-bit bidirectional I/O Ports, with • Two 8-bit bidirectional I/O ports with individual individually designed Data Direction Registers. The Data data direction control. Direction Registers provide selection of data flow direction • Automatic “Handshake” control of data transfers (input or output) at each respective I/O Port. Data flow • Two interrupts (one for each port) with program direction may be selected on a line-by-line basis with control intermixed input and output lines within the same port. The • Static to 14MHz operation, with high speed Port A, “handshake” interrupt control feature is provided by four CA2 outputs. peripheral control lines. This capability provides enhances • Industrial temperature range control over data transfer functions between the • 40 Pin Plastic Dip and 44 Pin Plastic PLCC microprocessor and peripheral devices, as well as versions bidirectional data transfer between W65C21S Peripheral • 5 volt ± 10% supply requirements Interface Adapters in multiprocessor systems. • Compatible with the 65xx and 68xx family of microprocessors B B A B 3 2 1 0 1 2 S Q Q A C A A A A A S C R R P P P P N V C C I I N VSS 1 40 CA1 PA0 2 39 CA2 6 5 4 3 2 1 PA1 3 38 IRQAB 44 43 42 41 40 PA4 7 39 RS0 PA2 4 37 IRQBB PA3 5 36 RS0 PA5 8 38 RS1 PA4 6 35 RS1 PA6 9 37 RESB PA5 7 34 RESB PA7 10 D0 36 PA6 8 33 D0 PB0 W 11 35 D1 PA7 9 32 D1 PB1 6 12 34 D2 PB0 10 5C21 31 D2 W65C21S PB2 13 33 D3 PB1 11 30 D3 PB3 14 32 D4 PB2 12 S 29 D4 PB4 15 31 D5 PB3 13 28 D5 PB5 16 30 D6 PB4 14 27 D6 PB6 17 29 D7 PB5 15 26 D7 8 9 0 1 2 3 4 5 6 7 8 PB6 16 25 PHI2 1 1 2 2 2 2 2 2 2 2 2 PB7 17 24 CS1 CB1 18 23 CS2B 2 1 2 7 1 2 B C D O I C S S B B B S N D H N W CB2 19 22 CS0 P C C C C V C P R VCC 20 21 RWB Figure 2. 40 Pin DIP Pin Configuration Figure 1. 44 Pin PLCC Pin Configuration FEATURES The Western Design Center W65C21S 3 The Western Design Center, Inc. W65C21S Data Sheet Figure 3. W65C21S PIA Block Diagram D0-D7 (8) (8) PA0-PA7 PERIPHERAL DEVICE PHI2 CA1 A RWB CA2 RS0 RS1 W65C21S 65xx, 68xx CS0 PIA MICROPROCESSOR CS1 FAMILIES CS2B RESB CB1 IRQAB PERIPHERAL IRQBB CB2 DEVICE VSS B (8) PB0-PB7 VCC Figure 4. Interface Signals Relationship The Western Design Center W65C21S 4 The Western Design Center, Inc. W65C21S Data Sheet ABSOLUTE MAXIMUM RATINGS* This device contains input protection against damage due to Parameter Symbol Value Unit high static voltages or electric fields; however, precautions should be taken to avoid application of voltages higher than Supply Voltage V -0.3 to +7.0 Vdc DD the maximum rating. Input Voltage Vdc VIN -0.3 to VDD Notes: +0.3 1. Exceeding these ratings may cause permanent damage, Output Voltage Vdc functional operation under these conditions is not implied. VOUT -0.3 to VDD +0.3 Operating Temp. Range °C TA -40 to +85 Industrial Storage Temperature T -55 to +150 °C STG DC CHARACTERISTICS (VDD = 5.0V + 10%, VSS = 0, TA = -40ºCto +85ºC) Parameter Symbol Min2 Typ.2,3 Max2 Unit1 Test Conditions Input High Voltage VIH 2.0 -- VDD +0.3 V VDD = 5.5V Input Low Voltage VIL -0.3 -- 0.8 V VDD = 4.5V Input Leakage Current V = .4V to 2.4V, V CA1, CB1, CS0, CS1, CS2B, RESB, RS0, RS1, RWB , I -- -- ±10.0 nA IN DD IN = 5.5V PHI2 Three-State (Off State), Leakage Current VIN = 0.4V to 2.4V, ITSI -- -- ±10.0 nA CB2, D0-D7, PB0-PB7 VDD = 5.5V Input High Current VIH = 2.4V, VDD IIH -50 -- -- µA CA2, PA0-PA7 = 4.5V Input Low Current VIL = 0.4V, VDD = IIL -- -- -500 uA CA2, PA0-PA7 5.5V Output High Voltage IOH = -200µA, VDD VOH 2.4 -- -- V D0-D7, PA0-PA7, PB0-PB7 = 4.5V Output Low Voltage CA2, CB2, D0-D7, IRQAB, IRQBB, PA0-PA7, PB0- VOL -- -- 0.4 V IOL = 3.2mA, VDD PB7 = 4.5V Output High Current (Sourcing) V = 1.5V, V t -3.0 -- -20.0 mA OH DD CB2 (Darlington Drive), PB0-PB7 CH = 4.5V Output Low Current (Sinking) V = 0.4V, V CA2, CB2, D0-D7, IRQAB, IRQBB, PA0-PA7, PB0- t 3.2 -- -- mA OL DD OL = 4.5V PB7 Output Leakage Current (Off State) tOFF -- < .1 10.0 nA VOH = 2.4V IRQAB, IRQBB Power Dissipation IDD -- 100 500 uA VDD = 5.5V Notes: 1. All units are direct current (DC) except for capacitance. 2. Negative sign indicates outward current flow, positive indicates inward flow. ○ 3. Typical values are shown for VDD = 5.0V and TA = 25 C 4. All production test loads use test machine capacitance (~30pF) only. 5. Capacitance of all pins is estimated 5.0pF at a 1MHz sample. The Western Design Center W65C21S 5 The Western Design Center, Inc. W65C21S Data Sheet AC TIMING CHARACTERISTICS 14 MHz @ 5V Parameter Symbol Min Max Unit PHI2 Cycle tCYC 70 - ns PHI2 Pulse Width tC 35 - ns PHI2 Rise and Fall Time trc tfc - 5 ns READ TIMING 14 MHz @ 5V Parameter Symbol Min Max Unit Address Set-Up Time tACR 10 - ns Address Hold Time tCAR 0 - ns Peripheral Data Setup Time tPCR 10 - ns Data Bus Delay Time tCDR - 20 ns Data Bus Hold Time tHR 5 - ns WRITE TIMING 14 MHz @ 5V Parameter Symbol Min Max Unit Address Set-Up Time tACW 10 - ns Address Hold Time tCAW 0 - ns Data Bus Set-Up Time tDCW 10 - ns Data Bus Hold Time tHW 5 - ns Peripheral Data Delay Time tCPW - 20 ns PERIPHERAL INTERFACE TIMING 14 MHz @ 5V Parameter Symbol Min Max Unit PHI2 Low to CA2 Low Delay tCA2 - 20 ns PHI2 Low to CA2 High Delay tRS1 - 20 ns CA1 Active to CA2 High Delay tRS2 - 25 ns PHI2 High to CB2 Low Delay tCB2 - 70 ns Peripheral Data Valid to CB2 Low t 5 - ns Delay DC PHI2 High to CB2 High Delay tRS1 - 20 ns CB1 Active to CB2 High Delay tRS2 - 25 ns CA1, CA1, CB1, and CB2 t t - 10 ns Input Rise and Fall Time r, f Interrupt Input Pulse Width PWI - 70 ns Interrupt Response Time tRS3 - 20 ns Interrupt Clear Delay tIR - 25 ns The Western Design Center W65C21S 6 The Western Design Center, Inc. W65C21S Data Sheet t t CYC rc tC tfc PHI2 tACW tCAW RS0, RS1, CS0, CS1, CS2B RWB tDCW tHW D0-D7 DATA IN tCPW PA0-PA7 PB0-PB7 tCDR tCB2 tRS1 CB2 (PULSE OUT) tDC tr tf CB1 tRS2 CB2 (HANDSHAKE) Figure 5. Read Timing Waveforms The Western Design Center W65C21S 7 The Western Design Center, Inc. W65C21S Data Sheet Figure 6. Write Timing Waveforms The Western Design Center W65C21S 8 The Western Design Center, Inc. W65C21S Data Sheet PWI CA1,CA2 CB1,CB2 PHI2 tIR IRQAB, IRQBB IRQAB, IRQBB tRS3 Figure 7. Interrupt Timing Figure 8. Interrupt Clear Timing Table 1. Control Registers DATA DIRECTION REGISTER REGISTER SELECT PIN ACCESS CONTROL BIT RS1 RS0 CRA-2 CRB-2 REGISTER SELECTED 0 0 1 - Peripheral Interface A 0 0 0 - Data Direction Register A 0 1 - - Control Register A 1 0 - 1 Peripheral Interface B 1 0 - 0 Data Direction Register B 1 1 - - Control Register B Table 2 Register Addressing P P P PIN DDR DDR DATA N DATA PIN INPUT (OUTPUT MODE) INPUT (INPUT MODE) N INPUT Figure 10 Port B, CB2 Buffers Figure 9 Port A, CA2 Buffers The Western Design Center W65C21S 9 The Western Design Center, Inc.
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