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Design of a CMOS Current Conveyor-Based Field-Programmable Analog Array

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Design of a CMOS Current Conveyor-Based Field-Programmable Analog Array Design of a CMOS Current Conveyor-Based Field-Programmable Analog Array Vincent Charles Gaudet A Thesis submitted in confomity with the requirements for the degree of Master of Applied Science in the Graduate Department of Electrical and Cornputer Engineering University of Toronto O Copyright by Vincent Charles Gaudet 1997 395 Wellington Street 395, nie Wellington Ottawa ON KI A ON4 Ottawa ON KIA ON4 Canada Canada Your file Votre rdférence Our file Notre r6fdtence The author has granted a non- L'auteur a accordé une licence non exclusive licence allowing the exclusive permettant à la National Librw of Canada to Bibliothèque nationale du Canada de reproduce, loan, distribute or sel1 reproduire, prêter, distribuer ou copies of this thesis in microfom, vendre des copies de cette thèse sous paper or electronic formats. la forme de microfiche/film, de reproduction sur papier ou sur format électronique. The author retains ownership of the L'auteur conserve la propriété du copyright in this thesis. Neither the droit d'auteur qui protège cette thèse. thesis nor substantial extracts fiom it Ni la thèse ni des extraits substantiels may be printed or otherwise de celle-ci ne doivent être imprimés reproduced without the author's ou autrement reproduits sans son permission. autorisation. Vincent Charles Gaudet Master of Applied Science, 1997 Department of Electrical and Cornputer Engineering University of Toronto Abstract To date, al1 published CMOS field-programmable analog array (FPAA) designs have operated under lMHz bandwidths. This thesis develops circuit methods allowing the development of a CMOS FPAA operating at greater than lMHz frequencies. For this purpose the second- generation current conveyor (CCII) is used. IC test results of a O.8p-nCMOS chip containing four configurable analog blocks based on the CCII, as well as an interconnection network based on transmission gates, are presented. The test results show that bandwidths exceed IOMHz. The four CABS and interconnect occupy a core area of 1551.8 x 741.2pm2. The thesis also proposes an FPAA design based on current conveyors and similar to a commercial bipolar FPAA, but operating at higher bandwidths; as well, a novel voltage comparator based on the CClI is proposed. Many people and organizations have helped me on the road to where 1 am today. There is no space on this page to thank them all, but I do wish to mention a few. I wish to thank my supervisor Professor Glenn GuIak for his assistance and flood of great ideas. It has been a privilege and a pleasure to work with him and 1 am looking fonvard to collaborating with him in the future. Continued financial support from NSERC, Micronet, and ITRC, as well as fabrication support from CMC are much appreciated. 1 also want to thank al1 my friends and colleagues in LP392 and the EECG, and wish them well in Our chosen field. Included are Ali, Andy, Aris, Aron, Billy, Dave, Jarnil, Jason A., Jason P., Javad, Jeff, Jordan, Keith, Ken, Khalid, Marcus, Mark, Mazen, Nirmal, Qiang, Silas, Steve, Vaughn, Wai Ming, Warren, and Yaska. I wish to thank Christophe, Dean, Khoman, and Bryn for their technical advice and assistance, and Peter, Fred, and Jaro for being there when 1needed them. My gratitude goes out to Burton, John, Mary, Sehdev, and the rest of the Massey College community for my two enjoyable years there. Morn, Dad, 1'11 be on page 104 soon. Watch out! '"Those three men,' said he, 'have carried into space al1 the resources of art, science, and industry. With that, one can do anything; and you will see that, some day, they will corne out al1 right."' -Jules Verne in Frorn the Earth to the Moon This thesis is dedicated to the memory of Greg Hartman. Table of Contents ........................................................................................................... iv List of Tables..................... ......... .................................................................................. vii List of Figures ................................................................................................................. viii List of Symbols .................................. ............................................................................. xi Chapter 1: Introduction ............................................................................................... 11 Motivation ........................................................................................................... 1.2 Thesis Outline ..................................................................................................... Chapter 2: Field-Programmable Analog Array Background....e.................e..... a. 2.1 Description of Field-Programmable Analog Arrays ........................................... 2.1.1 A Conceptual FPAA ................................................................................... 2.1.2 FPAA CAD Methodology .......................................................................... 2.1.3 FPAA Mapping Example ........................................................................... 2.2 Previous FPAA Designs ...................................................................................... 2.2.1 Early FPAA Designs .................................................................................. 2.2.2 Lee and Gulak FPAA ................................................................................. 2.2.3 IMP Electrically Programmable Analog Circuit (EPAC) .......................... 2.2.4 Motorola MPAA020 .................................................................................. 2.2.5 Zetex Totally Reconfigurable Analog Circuit (TRAC) .............................. 2.2.6 Other Proposed FPAA Designs ................................................................... 2.3 FPAA Design Issues ............................................................................................ 2.3.1 FPAA Performance Quantification ............................................................ 2.3 -2 Continuous-Time vs. Discrete-Time.......................................................... 2.3.3 Operational Amplifiers in FPAA Designs .................................................. Chapter 3: Current Conveyor Background................. ....... ...................................O.... 3.1 The Second-Generation Current Conveyor ......................................................... 3.1.1 Theory ........................................................................................................ 3.1.3 Comparator ................................................................................................ 3.2 Reasons for Current Conveyor-Based FPAA ...................................................... 3.2.1 Area Requirement ...................................................................................... 3.2.2 Compensation ............................................................................................ 3.2.3 Constant Bandwidth ................................................................................... 3.3 Previous Current Conveyor FPAA ...................................................................... 3.4 Commercial Current Conveyors ......................................................................... Chapter 4: A CMOS Current Conveyor-Based Configurable Analog Block .......... 4.1 Configurable Analog Block ................................................................................ 4.1.1 Current Conveyor ....................................................................................... 4.1.2 Transconductor........................................................................................... 4.1.3 Programmable Capacitor Array ................................................................. 4.1.4 Buffer ......................................................................................................... 4.1.5 Bias Circuit ................................................................................................ 4.2 Interconnection Network .................................................................................... 4.2.1 Transmission Gate Response ..................................................................... 4.2.2 Transmission Gate Into X Node ................................................................. 4.2.3 Transmission Gate Into Y Node ................................................................. 4.3 Test Chip ............................................................................................................. 4.4 Test Results ......................................................................................................... 4.4.1 Amplifier .................................................................................................... 4.4.2 Integrator .................................................................................................... 4.4.3 Differentiator.............................................................................................. 4.4.4 Adder ........................................................................................................ 4.4.5 Low Voltage Testing .................................................................................. 4.4.6 Summary of Test Results ........................................................................... Chapter 5: Future Current Conveyor-Based FPAAs. ..................... ........................... 5.1 Current Conveyor Irnplementation of the Zetex TRAC ....................................... 5.1.2 Layout
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