SONET OC-48 Transceiver

CYS25G0101DX SONET OC-48 Transceiver SONET OC-48 Transceiver Features Functional Description ■ SONET OC-48 operation The CYS25G0101DX SONET OC-48 Transceiver is a communications building block for high speed SONET data ■ Bellcore and ITU jitter compliance communications. It provides complete parallel-to-serial and ■ 2.488 GBaud serial signaling rate serial-to-parallel conversion, clock generation, and clock and data recovery operations in a single chip optimized for full ■ Multiple selectable loopback or loop through modes SONET compliance. ■ Single 155.52 MHz reference clock Transmit Path ■ Transmit FIFO for flexible data interface clocking New data is accepted at the 16-bit parallel transmit interface at ■ 16-bit parallel-to-serial conversion in transmit path a rate of 155.52 MHz. This data is passed to a small integrated FIFO to enable flexible transfer of data between the SONET ■ Serial-to-16-bit parallel conversion in receive path processor and the transmit serializer. As each 16-bit word is read from the transmit FIFO, it is serialized and sent out to the high ■ Synchronous parallel interface speed differential line driver at a rate of 2.488 Gbits per second. ❐ LVPECL compliant ❐ HSTL compliant Receive Path ■ Internal transmit and receive phase-locked loops (PLLs) As serial data is received at the differential line receiver, it is passed to a clock and data recovery (CDR) PLL that extracts a ■ Differential CML serial input precision low jitter clock from the transitions in the data stream. ❐ 50 mV input sensitivity This bit rate clock is used to sample the data stream and receive ❐ 100internal termination and DC restoration the data. Every 16-bit times, a new word is presented at the ■ Differential CML serial output receive parallel interface along with a clock. ❐ Source matched for 50 transmission lines (100 differential Parallel Interface transmission lines) The parallel I/O interface supports high speed bus communica- ■ Direct interface to standard fiber optic modules tions using HSTL signaling levels to minimize both power ■ Less than 1.0W typical power consumption and board landscape. The HSTL outputs are capable of driving unterminated transmission lines of less than ■ 120-pin 14 mm × 14 mm TQFP 70 mm and terminated 50 transmission lines of more than twice that length. ■ Standby power saving mode for inactive loops The CYS25G0101DX Transceiver’s parallel HSTL I/O can also ■ 0.25 BiCMOS technology be configured to operate at LVPECL signaling levels. This is ■ Pb-free packages available done externally by changing VDDQ, VREF and creating a simple circuit at the termination of the transceiver’s parallel output interface. Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 38-02009 Rev. *O Revised October 24, 2013 CYS25G0101DX Logic Block Diagram (155.52 MHz) (155.52 MHz) (155.52 MHz) TXCLKI TXD[15:0] FIFO_ERR TXCLKO REFCLK RXCLK RXD[15:0] FIFO_RST 16 16 Input Output Register Register TX PLL X16 16 FIFO Shifter 16 Recovered TX Bit-Clock Bit-Clock Shifter RX CDR PLL Retimed Data Lock-to-Ref LOOPTIME DIAGLOOP LINELOOP Lock-to-Data/ LOOPA Clock Control Logic OUT PWRDN LOCKREF SD LFI RESET IN Document Number: 38-02009 Rev. *O Page 2 of 22 CYS25G0101DX Contents Clocking ............................................................................4 DC Specifications ........................................................... 10 Pin Configuration .............................................................5 DC Specifications ........................................................... 10 Pin Descriptions ...............................................................6 DC Specifications ........................................................... 11 CYS25G0101DX Operation ..............................................8 DC Specifications ........................................................... 11 CYS25G0101DX Transmit Data Path ...............................8 DC Specifications ........................................................... 12 Operating Modes .........................................................8 AC Test Loads and Waveforms ..................................... 12 Phase Align Buffer .......................................................8 AC Specifications ........................................................... 13 Transmit PLL Clock Multiplier ......................................8 AC Specifications ........................................................... 13 Serializer .....................................................................8 AC Specifications ........................................................... 14 Serial Output Driver .....................................................8 Jitter Specifications ....................................................... 14 CYS25G0101DX Receive Data Path ................................8 Jitter Waveforms ............................................................ 15 Serial Line Receivers ..................................................8 Switching Waveforms .................................................... 16 Lock to Data Control ....................................................8 Typical IO Terminations ................................................. 17 Clock Data Recovery ...................................................8 Ordering Information ...................................................... 19 External Filter ..............................................................8 Ordering Code Definitions ......................................... 19 Deserializer .................................................................9 Package Diagram ............................................................ 20 Loopback Timing Modes .............................................9 Document History Page ................................................. 21 Reset Modes ...............................................................9 Sales, Solutions, and Legal Information ...................... 22 Power Down Mode ......................................................9 Worldwide Sales and Design Support ....................... 22 LVPECL Compliance ...................................................9 Products .................................................................... 22 Maximum Ratings ...........................................................10 PSoC® Solutions ...................................................... 22 Power Up Requirements ...........................................10 Cypress Developer Community ................................. 22 Operating Range .............................................................10 Technical Support ..................................................... 22 Document Number: 38-02009 Rev. *O Page 3 of 22 CYS25G0101DX Clocking Multiple loopback and loop through modes are available for both diagnostic and normal operation. For systems containing The source clock for the transmit data path is selectable from redundant SONET rings that are maintained in standby, the either the recovered clock or an external BITS (Building CYS25G0101DX may also be dynamically powered down to Integrated Timing Source) reference clock. The low jitter of the conserve system power. CDR PLL enables loop timed operation of the transmit data path meeting all Bellcore and ITU jitter requirements. Figure 1. CYS25G0101DX System Connections CYS25G0101DX SONET Data 16 TXD[15:0] Processor TXCLKI Transmit Data FIFO_RST Interface FIFO_ERR 155.52 MHz 2 TXCLKO REFCLK BITS Time 16 Reference Host Bus Receive Data RXD[15:0] Interface Interface RXCLK IN+ RD+ Serial Data LOOPTIME IN– RD– Data & Clock DIAGLOOP SD Optical Optical Direction SD XCVR Fiber Links System or Telco Bus System or Telco Control LOOPA OUT– TD– Serial Data LINELOOP OUT+ TD+ RESET Status and PWRDN System Control LOCKREF LFI Document Number: 38-02009 Rev. *O Page 4 of 22 CYS25G0101DX Pin Configuration Figure 2. 120-pin TQFP pinout [1, 2] * Top View * * NC NC VCCQ VSSQ \NC VSSQ VSSQ \NC VSSQ NC RXCP2 RXCN2 RXCP1 RXCN1 VSSQ VCCQ VSSQ CM_SER IN+ IN– VCCQ \NC NC VCCQ VCCQ VSSQ VCCQ VSSQ NC VSSQ VCCQ NC NC OUT– OUT+ 99 98 97 96 95 94 93 92 91 99 98 97 96 95 94 93 92 91 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 LFI 1 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 90 NC RESET 2 89 VCCQ DIAGLOOP 3 88 VSSQ LINELOOP 4 87 REFCLK+ LOOPA 5 86 REFCLK– VSSN 6 85 NC VCCN 7 84 LOOPTIME VSSN 8 83 PWRDN VSSN 9 82 VSSN SD 10 81 VCCN LOCKREF 11 80 VSSN RXD[0] 12 79 TXCLKO RXD[1] 13 CYS25G0101DX 78 VSSN RXD[2] 14 77 VDDQ RXD[3] 15 76 TXD[0] VSSN 16 75 TXD[1] VDDQ 17 74 TXD[2] RXD[4] 18 73 TXD[3] RXD[5] 19 72 VCCQ RXD[6] 20 71 VSSQ RXD[7] 21 70 VCCN VSSN 22 69 VSSN VDDQ 23 68 TXD[4] RXCLK 24 67 TXD[5] VSSN 25 66 TXD[6] VDDQ 26 65 TXD[7] NC 27 64 TXD[8] NC 28 63 TXD[9] NC 29 62 TXD[10] NC 30 61 TXD[11] 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 NC NC [14] VS S N VREF VS S Q VCCQ VS S N VS S N VCC N VSSQ VCC N VC CQ VS S N VD DQ VDDQ TXCLKI RXD[8] RXD[9] TXD[15] TXD[14] TXD[13] TXD[12] RXD[12] RXD[13] RXD RXD[15] RXD[10] RXD[11] FIFO_RST FIFO_ERR Notes 1. No connect (NC) pins are left unconnected or floating. Connecting any of these pins to the positive or negative power supply causes improper operation or failure of the device. 2. Pins 113 and 119 are either no connect or VSSQ. Use VSSQ for compatibility with next generation of OC-48 SERDES devices. Pin 116 are either no connect or VCCQ. Use VCCQ for compatibility with next generation

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