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AMD A45/A50M/A55E Fusion Controller Hub Register Programming Requirements

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AMD A45/A50M/A55E Fusion Controller Hub Register Programming Requirements AMD A45/A50M/A55E Fusion Controller Hub Register Programming Requirements Technical Reference Manual Rev. 3.00 P/N: 47778_ A45_A50M_A55E _rpr_pub_3.00 2012 Advanced Micro Devices, Inc. Trademarks AMD, the AMD Arrow logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. PCI Express and PCIe are trademarks of the PCI-Special Interest Group (PCI-SIG). Windows is a registered trademark of Microsoft Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Disclaimer The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to this document including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD shall not be liable for any damage, loss, expense, or claim of loss of any kind or character (including without limitation direct, indirect, consequential, exemplary, punitive, special, incidental or reliance damages) arising from use of or reliance on this document. No license, whether express, implied, arising by estoppel, or otherwise, to any intellectual property rights are granted by this publication. Except for AMD product purchased pursuant to AMD's Standard Terms and Conditions of Sale, and then only as expressly set forth therein, AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Table of Contents 1 Introduction ................................................................................................................ 7 1.1 About This Manual ........................................................................................................................ 7 1.2 AMD Hudson-1 Block Diagram ................................................................................................... 8 1.3 How to Read the Information in this Document ........................................................................... 9 2 ACPI/SMBUS Controller (bus-0, dev-20, fun-0)................................................ 10 2.1 Revision ID ................................................................................................................................. 10 2.2 ACPI Memory Mapped I/O Enable ............................................................................................. 10 2.3 MMIO Programming for Legacy Devices .................................................................................. 10 2.4 Programming C-State Transition Message in FCH ..................................................................... 11 2.5 Mt C1e Enable ............................................................................................................................. 12 2.6 HPET MSI Setting ...................................................................................................................... 12 2.7 CPU PwrGood Setting ................................................................................................................ 12 2.8 SMAF Matching Setting ............................................................................................................. 13 2.9 Keyboard Reset Settings for Legacy Free Systems ..................................................................... 13 2.10 NB Power Good Control on System Reset ................................................................................. 13 2.11 HWM Sensor Clk ........................................................................................................................ 14 2.12 PCIe® Native Mode ..................................................................................................................... 14 2.13 PCIe® Wake Status and PME Wake Status ................................................................................. 14 3 LPC Controller (bus-0, dev-20, fun-3) ................................................................ 15 3.1 SPI Controller MMIO Base Address ........................................................................................... 15 3.2 Enabling SPI ROM Prefetch ....................................................................................................... 15 3.3 Enabling LPC DMA Function ..................................................................................................... 15 3.4 Spi Timing Enhancement ............................................................................................................ 16 3.5 Spi Prefetch Enhancement........................................................................................................... 16 4 UMI Settings - Indirect I/O Access ...................................................................... 17 4.1 Defining AB_REG_BAR ............................................................................................................ 17 4.2 Upstream DMA Access ............................................................................................................ 17 4.3 PCIB Prefetch Settings ................................................................................................................ 17 4.4 OHCI Prefetch Settings ............................................................................................................... 18 4.5 B-Link Client’s Credit Variable Settings for the Downstream Arbitration Equation ................. 18 4.6 Setting B-Link Prefetch Mode .................................................................................................... 18 4.7 Detection of Upstream Interrupts ................................................................................................ 18 4.8 Downstream Posted Transactions to Pass Non-Posted Transactions .......................................... 19 4.9 AB Int_Arbiter Enhancement ...................................................................................................... 19 4.10 Requester ID ................................................................................................................................ 19 4.11 A-Link L1 (ASPM) ..................................................................................................................... 20 4.12 A-Link L0s/L1 NAK Reduction.................................................................................................. 20 4.13 PLL Power Down in A-Link L1.................................................................................................. 20 4.14 AB Internal Clock Gating ........................................................................................................... 21 2012 Advanced Micro Devices, Inc. TOC AMD A45/A50/A55M Register Programming Requirements Page 3 4.15 Non-Posted Memory Write Support ............................................................................................ 21 4.16 SMI Ordering .............................................................................................................................. 21 4.17 Posted Pass Non-Posted Feature ................................................................................................. 22 4.18 UMI Gen2 Speed Change ........................................................................................................... 23 5 PCIe® General Purpose Ports .............................................................................. 24 5.1 GPP Lane Configuration ............................................................................................................. 24 5.2 GPP Port A/B/C/D Enable .......................................................................................................... 24 5.3 GPP Reset .................................................................................................................................... 25 5.4 PCIe® Ports De-emphasis Settings .............................................................................................. 25 5.5 Write Capability for PCIe® Read-Only Registers ....................................................................... 26 5.6 Serial Number Capability ............................................................................................................ 26 5.7 Multi-function Enable ................................................................................................................. 26 5.8 GPP Upstream Memory Write Arbitration Enhancement ........................................................... 26 5.9 GPP Memory Write Max Payload Improvement ........................................................................ 27 5.10 Multiple GPP Device Support ....................................................................................................
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