Single Sideband Modulation Using Tms32020 Digital Signal Processor

SINGLE SIDEBAND MODULATION USING TMS32020 DIGITAL SIGNAL PROCESSOR

by

RABINDER SINGH MOKHA

School of Electrical Engineering & Computer Science University of New South Wales Kensington, NSW, Australia.

A project report (18 credit points) submitted in partial fulfillment of the requirement for the degree of Master of Engineering Science

April, 1988 UNIVERSITY OF N.S.W. 2 1 MAR 1989

LIBRARY I hereby declare that this submission is my own work and that, to the best of my knowledge and belief, it contains no material previously published or written by another person nor material which to a substantial extent has been accepted for the award of any other degree or diploma of a university or other institute of higher learning, except where due acknowledgement is made in the text.

Signed Date ABSTRACT

In modern day communications, single sideband (SSB) modulation is the preferred means of transmission of speech signals, where its main attractions are low power and minimum bandwidth requirements. Theoretically, Weaver’s method of SSB generation is superior to the other methods available. Though Weaver’s method was first presented in 1956, the inability to produce two identical paths in analog, with components like modulators and filters, lead to the non-recognition of this method. In digital systems, where signal processing involves only arithmetic operations and the processing components comprise of numbers only, identical paths can very readily be obtained. With the availibility of high speed digital signal processors like the TMS320 family from Texas Instruments, such systems, operating on software, are possible. The work presented in the thesis involves the implementation of Weaver’s method for speech transmission, using the TMS32020 digital signal processor. For efficient implementation, the design procedures for the processing components were studied in detail. With the aid of hardware flag pins available on the processor, a technique for synchronizing the transmitter and receiver oscillator frequencies has been presented. Finite wordlength effects introduced in the digital system were also considered. Using interpolation, design for achieving higher sampling rates has been proposed. Digital implementation of other SSB generation methods was considered and the results compared with those from the Weaver’s method. With the availibility of next generation digital signal processors, the work presented in the thesis would open new possibilities for the advancements in SSB modulation. ACKNOWLEDGEMENTS

I would like to express my thanks to Dr.W.J.Dewar for his supervision, guidance, and encouragement throughtout the course of the thesis. Thanks are also extended to Dr.C.J.E.Phillips and Dr.E.H.Fooks for their useful hints and advise. I deeply appreciate the assistance given and the knowledge shared by Tom Millet and Joe Yiu, especially in the early stages of the thesis. Special thanks to Marek Szuszkiewicz for the healthy discussions and for making life much easier in the lab. I am grateful to my friends Amarjit and Ashwin for their constant support, good humour, and creating a cheerful environment. Finally, I must acknowledge my aunt without whose affection and support this work would never have eventuated. CONTENTS

Abstract

A cknowledgements

Abbreviations

CHAPTER 1 : INTRODUCTION 1

CHAPTER 2 : MODULATION TECHNIQUES 4 2.1 Introduction 2.2 Double sideband suppressed-carrier modulation 2.3 Amplitude modulation 2.4 SSB modulation

CHAPTER 3 : SSB MODULATION 12 3.1 Introduction 3.2 Frequency discrimination method 3.3 Phase shifting method 3.4 Weaver’s method 3.5 Difficulty with Weaver’s method

CHAPTER 4 : DIGITAL SSB SYSTEM 19 4.1 Introduction 4.2 Digital filters 4.3 Design of HR filters 4.4 Realization of digital filters 4.5 Recursive digital oscillator

CHAPTER 5 : FINITE WORDLENGTH EFFECTS 32 5.1 Introduction 5.2 Arithmetic in digital systems 5.3 Coefficient quantization 5.4 Signal quantization 5.5 Roundoff noise 5.6 Overflow and Scaling 5.7 Finite wordlength in digital filters 5.8 Limit cycle oscillations 5.9 Coefficient sensitivity and roundoff noise

CHAPTER 6 : TMS320 DIGITAL SIGNAL PROCESSOR 46 6.1 TMS320 family of Digital Signal Processors 6.2 TMS32020 DSP 6.3 Memory organization 6.4 Multiplication and addition 6.5 System control and speed utilization 6.6 Registers 6.7 Software Development System

CHAPTER 7 : IMPLEMENTATION 58 7.1 Supporting Equipment 7.2 Weaver’s method - Implementation 7.3 Synchronization 7.4 Performance 7.5 Multiplexed system 7.6 Interpolation and Decimation 7.7 Phase shifting method

CHAPTER 8 : CONCLUSION AND FUTURE WORK 81

REFERENCES 84

BIBLIOGRAPHY 88

APPENDICES 90 Appendix 1 Appendix 2 Appendix 3 Appendix 4 ABBREVIATIONS

A/D Analog to Digital

ADC Analog to Digital Converter

AM Amplitude Modulation

D/A Digital to Analog

DAC Digital to Analog Converter

DSB-SC Double Sideband Suppressed Carrier

DSP Digital Signal Processing

EVM Evaluation Module

FFT Fast Fourier Transform

FIR Finite Impulse Response

HR Infinite Impulse Response

LPF Lowpass Filter

LSB Lower Sideband

MIPS Million Instructions Per Second

PC Personal Computer

PCM Pulse Coded Modulation

RAM Random Access Memory

ROM Read Only Memory

S/H Sample and Hold

SNR Signal to Noise Ratio

SSB Single Sideband

SWDS Software Development System

TDL Tapped Delay Line

USB Upper Sideband -1 -

CHAPTER 1 : INTRODUCTION

Digital processing of communication signals is gaining prominence and has become a practical alternative to analog processing. As long as input and output signals are band limited, conventional analog communication circuits can be replaced by their equivalent digital signal processors with the addition of analog-to-digital (A/D) and digital-to-analog (D/A) converters. Digital signal processing (DSP) involves the representation, transmission, and manipulation of signals using numerical techniques and digital processors. Over the recent years, DSP has made a tremendous progress. With the availability of large-scale integrated (LSI) circuitry and low cost A/D and D/A circuits, DSP have become economically feasible. But a bigger breakthrough has been the coming of single-chip (VLSI devices) digital signal processors which are essentially high-speed microprocessors/microcomputers designed specifically to perform DSP algorithms. The main advantages which have been the basic motivation for the use of DSP instead of traditional analog processing are :

i. Low power, high speed digital signal processors with large storage capacities are now available. They are capable of performing arithmetic, storage and timing operations.

ii. Since digital realizations are independent of variations in external conditions like power supply, component tolerances and temperature, the digital processing characteristics (e.g. filtering and modulation) can be reproduced to the same accuracy.

iii. DSP is free from hardware problems and parasitic effects that restrict the analog realizations.

iv. Digital signal processors offer a flexibility in their ability to be programmable and thus vary the characteristics as required. For example, filter characteristics can be varied simply by changing the filter tap coefficients.

Because of the main advantages of stability, testability, reproducibility, accuracy, and flexibility, digital signal processors are becoming more prevalent in areas of general-purpose DSP, telecommunications, voice/speech, imaging and control. The work in this thesis investigates the feasibility of digital implementation of -2- various single sideband (SSB) generation methods on the TMS32020 digital signal processor from Texas Instruments. Until now, Weaver’s method of SSB generation has suffered severely from the limited accuracy of analog implementation of two identical paths. The digital implementation overcomes this shortcoming because two identical processing paths can be produced by having the same software and filter coefficients for the two. Besides the work presented in the thesis, a fair amount of time and effort was taken up by another two factors which are not apparent from the succeeding chapters. In the initial stages of the thesis, work involved in getting familiarized with a completely new and different set of assembler instructions & directives, and with the internal processor hardware architecture was demanding. This was necessary to make the best use of the TMS32020 instruction set and exploit the internal architecture efficiently. As explained later in Chapter 7, the processing time (or the sampling rate) plays a vital role in the feasibility of a digital system. Thus a fairly good knowledge of the processor software and hardware was important. Secondly, a TMS32020 Evaluation Module was assembled and tested to be used as a tool in software debugging. Different modulation techniques (including SSB) and a comparison between them is presented in Chapter 2. In Chapter 3, various SSB modulation methods have been presented. While Weaver’s method has been explained in detail, the other two modulation methods have been briefed. Chapter 4 reviews the digital realization of SSB signal generation using Weaver’s method. The basic components in a Weaver’s modulator are digital filters, frequency modulators, and oscillators. Design and implementation of each of these components has been presented. When an infinite number of bits are available for representing signals, the design characteristics can be implemented without any error. But in all practical digital systems, we have a finite number of bits to represent signals. This results in certain undesirable effects, such as the quantization noise, limit cycle oscillations, and overflow. The effects of finite word lengths and its limitations have been reviewed in Chapter 5. Chapter 6 gives a description of the architecture, memory organization, and special features of the TMS32020 digital signal processor used in this thesis. A brief note on the Software development system (SWDS) has also been added. The implementation and performance of the Weaver’s method of SSB -3- generation for voiceband signals in real time, is presented in Chapter 7. The topics of scaling filter coefficients to avoid overflow, noise variance, synchronization of the transmitter and receiver, have also been covered. The technique of interpolation (or decimation) for increasing (or decreasing) the sampling rate of a real-time digital process has been presented. Also included in the chapter are the observations made on the other SSB generation methods implemented on the TMS32020. Chapter 8 briefs the practical applications of the SSB modulation using digital techniques, followed by the conclusion and prospects for future work in this area. In addition to a list of references, a full bibliography has been included for details on the equipment and applications considered in the thesis.

The following have been included in the Appendix :

• Circuit diagrams for the variable gain amplifier and lowpass anti-aliasing filter, followed by a brief working and circuit for the A/D, D/A converter board used in the thesis.

• Listing of the FORTRAN programs used for digital filter design, scaling filter coefficients, and roundoff noise analysis.

• Listing of the TMS32020 assembly programs used for digital implementation of all the modulation systems considered in the thesis. -4-

CHAPTER 2 : MODULATION TECHNIQUES

2.1 Introduction

In any communication system, the transmission bandwidth and power requirement of the transmitter are two important parameters. It is highly desirable to achieve savings in bandwidth and power requirements. Hence, since the day in 1923 when single sideband (SSB) modulation was patented by J.R.Carson, it has been a preferred means of signal transmission, wherever feasible. This is because SSB modulation has certain advantages over other modulation methods, like double sideband-suppressed carrier (DSB-SC) modulation and amplitude modulation (AM). The main advantages are :

i. minimum bandwidth.

ii. lowest power requirements for equal signal to noise ratio (SNR).

iii. no carrier transmission required.

A brief description of different methods of modulation is presented in the following sections.

2.2 Double sideband suppressed carrier (DSB-SC) modulation

In DSB-SC modulation the amplitude Ac of the unmodulated carrier Ac cos (coct + 0C) is varied in direct proportion to the modulating (baseband) signal while the frequency fc and the phase 0C are kept constant. Assuming, without loss in generality that 0C = 0, the modulated carrier is m(t) cos coct (Fig.2.1a), where m(t) is the modulating signal. This type of modulation results in a shift of spectrum of m(t) to the carrier frequency where the modulated carrier spectrum has both an upper and a lower sideband (Fig.2.1c).

For m(t) <—> M(co)

m(t) cos coct <—> j [M(co + coc) + M(co - coc)] 2 1

Hence, the bandwidth of the modulated signal is twice that of the modulating signal m(t).

For example, if m(t) = cos comt, then the modulated signal -5-

m(t) cos (oct m(t) (DSB-SC)

cos coct (a) Modulator

m(t) cos coct = cos comt cos coct

1 [cos(coc + com)t + cos(coc - com)t] ... 2.2

From the above equation we see that the modulated signal has frequency components coc ± com but no carrier frequency coc component and thus the name DSB-SC modulation.

In order to demodulate, the incoming modulated signal is multiplied by cos coct and the product is fed to a lowpass filter (LPF) which passes the desired spectrum M(co) and suppresses the unwanted high-frequency spectrum (Fig.2.2).

m(t) cos coct cos coct = “ [m(t) + m(t) cos 2coct] 2 3 and m(t) cos coct coscoct <—> ~ M(co) + — [M(co + 2coc) + M(co - 2coc)] 2 4 ••• -6-

m(t)cos (Oct Lowpass 1/2 m(t) Filter

cos wct (a) Demodulator Lowpass Filter

(b) Reconstructed signal

Figure 2.2 : DSB-SC demodulation

2.3 Amplitude modulation (AM)

In a DSB-SC system, the receiver requires to generate a local carrier of exactly the right frequency and phase, thus needing a high cost sophisticated equipment. Such systems could be useful for point-to-point communication but not for broadcast systems. Hence for broadcast and similar systems, a large carrier signal is transmitted along with the DSB-SC signal, m(t) cos coct . This is known as the AM system and it eliminates the requirements of generating a local carrier signal at the receiver. The modulated signal is given by

= m(t)cos ®ct + A cos coct

= [A + m(t)] cos coct ... 2.5

It has the same spectrum as DSB-SC signal spectrum (Fig.2.1c) but with two additional impulses at ±coc.

^am(0 *—> \ [M(cu + coc) + M(co-coc)]

+ 7lA [5(G) + G)c) + 5(G) + G)c)] 2 ^

The AM signal can be demodulated using a non-coherent method requiring simpler and less expensive equipment. -7-

2.4 SSB modulation

AM method is wasteful of both transmitted power and transmission bandwidth, while the DSB-SC modulation method has lesser power requirements than the AM, but still uses the same bandwidth. Both DSB-SC modulation and AM retain the upper and lower sidebands of the message signal resulting in a transmission bandwidth that is twice the bandwidth of the message signal. However, due to their symmetry about the carrier frequency, the upper and lower sidebands have a unique relation with each other, because the spectrum of any real-valued signal x(t) must satisfy the symmetry condition

X(f) = X*(-f) ... 2.7

If we have the amplitude and phase spectrum of one sideband, the other can always be reconstructed. This means that only one sideband is necessary as far as transmission of information is concerned, and if the carrier and the other sidebands are suppressed at the transmitter, no information is lost. From this one can infer, that the communication channel needs to provide only the same bandwidth as the baseband signal. A modulation system where only one sideband is transmitted, is referred to as a single-sideband (SSB) system.

(a) DSB-SC signal

-COc (b) SSB signal with USB transmitted

(c) SSB signal with LSB transmitted

Figure 2.3 : SSB signal spectrum

The exact frequency-domain description of a SSB wave depends on which sideband is transmitted. Consider a modulating (baseband) signal m(t) with a spectrum M(co) that is limited to the band -B < f < B, as in Fig.2.1b. The spectrum of the -8-

DSB-SC wave as shown in Fig.2.1c has been redrawn in Fig.2.3a for convenience. The upper sideband (USB) is duplicated by the frequencies above fc and those below -fc; and when only the USB is transmitted, the resulting SSB wave s(t) has the spectrum as shown in Fig.2.3b. Similarly, the lower sideband (LSB) is duplicated by the frequencies below fc (for positive frequencies) and those above -fc (for negative frequencies). When only the LSB is transmitted, the spectrum of the corresponding SSB wave is as shown in Fig.2.3c.

The main function of a SSB modulation system is to shift the spectrum of the modulating signal, either with or without inversion, to a new location in the frequency domain. Also, the transmission bandwidth requirements of the SSB system are one-half that of an AM or DSB-SC modulation system. Thus the main advantage of using SSB modulation, as mentioned before, is the reduction in bandwidth requirements and the elimination of the high-power carrier signal.

For time-domain description of an SSB wave, s(t) may be expressed in the canonical form

s(t) = sc(t) cos coct - ss(t) sin coct ... 2.8 where sc(t) is the in-phase component of the SSB signal, and ss(t) is its quadrature component. The in-phase component sc(t), except for a scaling factor, may be obtained from s(t) by first multiplying s(t) by cos coct and then passing the product through a low pass filter. Similarly, the quadrature component ss(t) , may be obtained from s(t) by first multiplying s(t) by sin coct and then passing the product through an identical low pass filter. Hence, the Fourier transforms of sc(t) and ss(t) are related to that of the SSB signal s(t) as follows, respectively:

|s(f-fc) + S(f+fc),t -B < f < B Sc(f) - q ^ elsewhere ... 2.9

j[S(f-fc) - S(f+fc)], -B < f < B Ss(f) ~ o, elsewhere ..2.10 where -B < f < B defines the frequency band occupied by the message signal m(t).

0. f Since co = 27tf, both co and f have been used interchangably in the thesis. -9-

s(f-y l/2AcM(o) / \ _B 0 f---- » 2fc 2fc+B (a) SSB spectrum shifted by +fc

l/2AcM(o) S(f+fc) / \ b -2fc -B -2fc o f (b) SSB spectrum shifted by -fc

l/2AcM(o)

(c) Spectrum of in-phase component

(d) Spectrum of quadrature phase component

Figure 2.4

Consider now the case of an SSB wave that is obtained by transmitting only the upper sideband and the spectrum of such a modulated wave is shown in Fig.2.3b. The two frequency shifted spectra corresponding to S(f - fc) and S(f + fc), are represented in Fig.2.4a&b, respectively.

From Fig.2.4c, we may write

Sc(f) = j AcM(f) 211 where M(f) is the Fourier transform of the modulating signal m(t).

Therefore, the in-phase component sc(t) is defined by - 10-

AcM(t) sc(t) = j 2.12

From Fig.2.4d, we may write

_i~2 AcM(f), f >0 Ss(f) = 0, f = 0 f<0 12 AcM(f),

= ~ ^ Ac sgn(f) M(f)

.. 2.13

where sgn(f) is the signum function, and is defined as

+1 f>0 sgn(f) = 0 f=0 -1 f <0

However,

■ j sgn(f) M(f) = Mh(f) ..2.14 where Mh(f) is the Fourier transform of mh(t), and mh(t) itself, is the Hilbert transform of m(t). Substituting (2.14) in (2.13), gives

Ss(f) = yAcMh(f) ...2.15 which shows that the quadrature component ss(t) is defined by

ss(t) = ~ Ac mh(t) ..2.16

Substituting (2.12) and (2.16) in (2.8), yields the canonical representation of an SSB wave s(t) obtained by transmitting only the USB and is as follows

s(t) = j Ac m(t) cos (27tfct) - y.Ac mh(t) sin (2rcfct) ..2.17

Following a procedure similar to that described above, the canonical representation for an SSB wave s(t) obtained by transmitting only the LSB, can be -11 - found. It is as presented in Fig.2.3c, and has a form similar to (2.17) with the exception of the minus sign on the right-hand side of the equation being replaced by a plus sign. One should remember that the bandwidth saving in SSB modulation system is accompanied by a considerably high cost equipment complexity. In addition to equipment complexity, practical SSB systems have shown poor response at low- frequencies. - 12-

CHAPTER 3 : SSB MODULATION

3.1 Introduction

In the previous chapter, it was shown that SSB systems have considerable advantages over other modulation systems, especially when we have one-to-one communication. SSB systems have found wide applications for transmission of voice signals as they do not require any phase information. In this chapter we present the three methods used to generate SSB signals in the analog case. The first two, that are the frequency discrimination and the phasing method are commonly used . The third one, called the Weaver’s method, has been known for a long time but has not found much recognition in analog due to the difficulty of getting two identical filtering and modulation channels.

3.2 Frequency discrimination method

SSB DSB r Sideband m(t) signal Vjy signal filter mc(t)

Accos coct (a) Modulator

M(f)

-B 0 B f (b) Baseband signal spectrum

Bssb^

-f-B -f 0 f-----► fc fc+B (c) Ideal sideband filter

-f-B -fc 0 f —► fc fc+B (d) Transmitted sideband spectrum

Figure 3.1 : SSB modulation -13-

Until now frequency discrimination has been the most commonly used method of generating SSB signals. Basically, it consists of a frequency modulator and a filter which is designed to pass the desired sideband of the DSB-SC wave at the modulator output and reject the other sideband. A block diagram of this modulator, as shown in Fig.3.1a, appears very simple, but its practical implementation is exceedingly difficult.

Bandpass si(t) v2(t) Bandpass m(t) (X)M V'(t)r s2(t) filter V filter

Ajcos tOjt A2cosco2t

(a) Two-stage SSB modulator

Baseband y(t) *0®---- -<9)- filter

2 cos coct

(b) SSB demodulation

Figure 3.2 : Frequency discrimination method

The input signal (a speech signal, for example) is applied to a frequency modulator along with the first translating or carrier frequency. In doing so, the carrier frequency is balanced out and the two normal sidebands appear at the modulator output. The purpose of the filter is to pass the desired sideband (say, USB) and reject the other, as shown in Fig.3.1c,d. This bandpass filter must satisfy the two basic requirements. Firstly, the filter passband should occupy the same frequency range as the spectrum of the desired SSB signal. Then the width of the transition band of the filter, separating the passband from the stopband where the unwanted sideband of the filter input lies, should be twice the lowest frequency component of the modulating signal. Such conditions can only be satisfied by high selectivity filters having high Q-factors.

When the desired frequency location of the SSB signal is high as compared to the original location of the input signal (e.g. translating a speech signal), it becomes very difficult to obtain a filter that will pass one sideband and reject the other. In such a case, filter requirements can be eased by restoring to a multiple-modulation process. - 14-

This approach is illustrated in Fig.3.2a involving two stages of modulation. In many radio transmission systems, three or even more stages may be used.

To demodulate the SSB signal, the inverse of the modulation process is performed but with one modification, i.e. to recover the original signal the resultant DSB-SC signal is passed through a lowpass filter instead of a bandpass filter as in modulation (Fig.3.2b).

The main disadvantage of this method is that it requires high selectivity filters. Otherwise for multiple modulation and filtering process, it requires more stages, resulting in more circuitry and expenses.

3.3 Phase shifting method

This method consists of two separate but simultaneous modulation processes and subsequently combining the resulting modulation products of the two branches (Fig.3.3). In one of the branches, the input signal is applied to a wide-band 90° phase- shifter, which passes all frequencies of the input signal uniformly in amplitude, but delays the phase by 90°, thus producing the Hilbert transform of the input. Such a system can be directly derived from (2.17), which defines the canonical representation of SSB signals in the time domain, when only the USB is transmitted.

-o cos coct modulating SSB wave ° 90 wave m(t) phase shifter

Hilbert transformer

Figure 3.3 : Phase shifting method

In the two branches A and B, the modulating carrier signals are in phase quadrature to each other. In branch A, the input signal m(t) is modulated, producing a DSB-SC signal in which the reference phase sidebands are symmetrically spaced about - 15-

the carrier frequency. In branch B, the Hilbert transform mh(t) of the input signal m(t) is modulated by the carrier in quadrature phase. It again produces a DSB-SC signal, but the relative phases of the two modulators outputs are such that when they are either added or subtracted, one set of the sidebands will add in phase, generating the desired signal, while the other sideband will cancel itself out.

Again, the SSB signal can be demodulated to obtain the original baseband signal by using the same scheme as for Frequency discrimination method. As this is a balancing method and does not require any sharp cut-off filters, it is possible to generate the desired sideband in a single translational step. However, the degree to which the undesired sideband may be suppressed depends on accurate balancing and requires very careful control of the amplitudes and phases. Moreover, to obtain the Hilbert transform mh(t) of the input baseband signal m(t), we require hardware which keeps the amplitude constant but shifts the phase of all frequency components of m(t) by 90°. Practically, it is very hard to design such a network and there will always be an error in the approximation of the constant 90° phase difference between m(t) and mh(t). As a result, it is quite difficult to obtain suppressions of more than 35dB, using this method.

3.4 Weaver’s method

A block diagram of this method of SSB signal generation is as shown in Fig.3.4.

Lowpass ma. filter T

cos art m0(t) mi(t) SSB ©r wave sin coct

Lowpass mb, 3 * A filter vy

Figure 3.4 : Weaver’s method of SSB generation

As shown in Fig.3.5a, the input signal m^t) is confined to a bandwidth B with the lower band limit fL. The band center is fQ, i.e. - 16-

f0 = fL + B/2 ...3.1

k f0 fL+B

(a) Input signal spectrum

2fL

B/2 2fo 2fo 2fo -B/2 +B/2

(b) Spectrum from first frequency modulators

(c) Spectrum of output SSB signal

Figure 3.5

Expressing the input signal as a summation of sinusoidal terms,

mi(t) = X An cos (cont + (J)n) n=l 3.2

Observe that the center frequency of the input spectrum is the modulating or carrier frequency of the first pair of frequency modulators. The outputs of the first two frequency modulators are

mal = 2mi(t) cos coQt ... 3.3

mbl = 2mi(t) sin co0t, ... 3.4

where co0 = 2nf0 ... 3.5

The coefficient 2 has been added for mathematical convenience and could be considered as a property of the frequency modulators. - 17-

On substituting (3.2) into (3.3) and (3.4), and expanding, we get

N mal = £ An cos [(©n “ “o)1 + n ] + An C0S [(©n + COo)t +

N mbl = Z — An sin K«n - WG)t + n] + An sin [(®n + “o)1 +

fL

Therefore, the spectrum of the signals mal and mbl is as shown in Fig.3.5b. Thus we require a lowpass filter which passes the frequencies from zero to Bgps2. Since there should be no signal energy between Bgps2 and 2f0-Bgps2, it provides a wide transition region for the filter. Above 2f0-Bgps2 , the filter should have adequate attenuation to eliminate the high-frequency components from the frequency modulators. The outputs of such a filter are given by

N ma2 = £ An C0S t(©n ~ ©o)1 + W n=l ••• 3.9

N mb2 = Z An sin t(©n “ ©o)t +

The two filtered outputs are then applied to another pair of frequency modulators. But now, the translating frequency coc is the band center of the required SSB signal. The outputs of this second pair of modulators are expressed as

ma3 = ma2COSC0ct ...3.11

mb3 = mb2 sin coct ... 3.12

On substituting (3.9) and (3.10) into (3.11) and (3.12), and expanding, we get

N A ma3 = Z COS [(©c + ©n ~ ©o)l + W n=l 1 K + — cos [(C0c - con + C0o)t - <|)n] ... 3.13 - 18-

N An mb3 = Z COS [(®c + “n - ©0)t + <})n] n=l

--f COS [(C0c - con + (0o)t - <|>n] ...3.14

On adding (3.13) and (3.14), we get the required SSB output signal

mo = ma3 + mb3 ...3.15

N mo = Z An cos [(C0c + con - C0o)t +

The above relations have been derived by Weaver [1]. Fig.3.5c shows the spectrum of mQ. Observe that the frequency coc is the center of the single sideband and the frequency normally referred to as the carrier corresponds to (coc - coQ).

Thus we see that this method of SSB generation does not require either sharp cutoff filters or wideband 90° phase-shifting networks. Any error in the phasing or balancing results in an unwanted sideband which occupies the same band of frequencies as the desired sideband, except for being inverted, and does not appear at its normal position. This turns out to be a plus point for this system because our purpose of using SSB signals is to conserve channel bandwidth.

3.5 Difficulty with Weaver’s method

When the two modulated signals are added together (or subtracted), the unwanted sideband is cancelled out. In the analog case, the degree to which this cancellation takes place depends on how closely the rejected sideband undergoes identical transmission in the two branches. This is the main reason why the implementation of this type of SSB generation has been difficult until now (although the Weaver’s method has a strong point that cancellation takes place in the same channel, instead of in an adjacent channel as in the other methods, thus relaxing considerably the requirements on the degree of cancellation). As will be seen in Chapter 7 that the digital implementation overcomes this shortcoming, because the amount of suppression is solely related to the number of bits per word. A system implemented with a word length which is sufficient for a required signal to noise ratio, will also yield sufficient suppression of the unwanted sideband. - 19-

CHAPTER 4 : DIGITAL SSB SYSTEM

4.1 Introduction

In the previous chapter, the three different methods available for generating SSB signals were presented. We saw that 'Weaver’s method' of analog SSB generation overcomes certain disadvantages that are present in the other two approaches. In 1976, Kurth [2] reviewed the theoretical and practical aspects of analog SSB generation. He concluded with a comment that very soon an entire digital signal processor would be used for the generation of SSB signals. Though it has been more than 30 years since the Weaver’s method was proposed, but still it has not been used much in analog systems. Now, as more and more signal processing is being done digitally, Weaver’s method is being considered seriously for SSB systems. Darlington [3] has considered a scheme for digital modulation in which 12 voice-band signals are processed and transmitted simultaneously. Singh et al [4] considered the discretised version of Weaver’s modulator and a system of multiplexing 12 such channels together. The simulated results presented by them confirm the validity of the digital scheme for SSB modulation. Kurth [5] presents an alternate method for the digital generation of Frequency division multiplexing (FDM) signals by using a time division version of the Weaver’s modulator, where voice signals are digitized (PCM) at a 8kHz sample rate and the resulting pulse streams are interleaved in time. In this chapter, we look at in detail, the digital realization of generating SSB signals using Weaver’s method. The block diagram for the Weaver’s modulator in the analog case was presented in Fig.3.4. In the digital version, the basic method stays the same, except that the operations (or processing of the signals) are done digitally. The modulator consists of three basic components, a digital filter, a frequency translator or modulator, and a digital oscillator. As will be seen in Chapters 6 & 7, digital frequency modulation can be done by a single instruction 'MPY' on the TMS32020.

4.2 Digital filters

4.2.1 Z-transform : We have a brief look at the z-transform, for it is the most natural technique of considering digital filters. The two sided or bilateral z-transform of a causal sequence x(n), is defined as -20-

X(z) = £ x(n)Z-n n = -oo •• • 4.1 where z is a complex variable.

The complex function of (4.1) is defined only for those values of z for which the power series converges. Since we will be dealing only with causal sequences, we define 'one-sided' or unilateral z-transform,

X(z) = £x(n)Z~n iS) ... 4.2 where we consider x(n) = 0 for n < 0 Thez-transform of a given sequence can be considered as a unique representation of that sequence in the complex z-plane. On evaluating the z-transform on a circle of unit radius, i.e. z = e^03, then from (4.2) we have

X(z I z=ei«>) = X(ei“) = ixnje-i™1 n=0 ... 4.3

Note, that the relation in (4.3) is the Fourier transform of the given sequence. The unit circle in the z-plane plays an important role in the system stability considerations. One of the important properties of z-transform is that z-1 may be interpreted as a unit delay operation, that is, if a sequence xa(n) has z-transform Xa(z), then the sequence xa(n-nQ) has the z-transform z-n°Xa(z) for all nQ . This is quite useful while converting between a difference equation representation of a sequence and its z- transform. As an example,

Y(z) = X(z) + a1 z-1 Y(z) ...4.4 is the z-transform of the difference equation

y(n) = x(n) + aj y(n-l) ... 4.5

oo where Y(z) = £y(n)z_n o

X(z) = £x(n)z"n o

4.2.2 Basic theory of Digital filters : The theory of digital filters is based on the mathematics of difference equations. The digital output signal is a combination of the -21 -

present and past inputs, and the past outputs, i.e.

Yn = a0 xn + xn_! + ... + aM xn_M

+ bi yn-i+ b2 yn-2 + - + bN yn_N ... 4.6

M M = L^-i + Lbiyn-i i=0 i=l ... 4.7

Expressing (4.6) in the z domain, we obtain

Y(z) = (ao + ax z_1 +... + aM z~M) X(z)

-2 -Nn + (bi z 1 + b2 z z + ... + b^ z 1N) Y(z) ... 4.8

M ’ N Z ai Z_1 X(z) + LbiZ-1 Y(z) i=° i=t ... 4.9

Therefore, the transfer function

Y(z) ao + ax z 1 + ... + aMz M H(z) X(z) 1 — bx z_1 - ... - bNz-N

M -i X ai Z i=0 N ,-i 1 - S t>i Z i=l ...4.10

If all the bj's are zero, then the present output value is a function of only a finite number of past and present input values. Such a filter has a finite-duration impulse response and is known as an FIR filter. Whereas, if some of the b/s are non-zero, then the present output value is a function of both, the past output values as well as the present & past input values. Such a filter has an infinite-duration impulse response and is known as an HR filter.

These are the two main types of linear digital filters. Since neither of the the two types is absolute, the choice between an FIR or an HR filter depends on the requirements of the application. Each of them has its own advantages and disadvantages. An FIR filter has certain advantages, viz: it can be designed to have exactly linear phase, is always stable, is free from limit-cycle oscillations and can be made to have lesser roundoff noise. On the other hand, its main drawback is that to achieve given filter characteristics, the length of the filter required may be quite large which means an increase in the computation time. For high order filters this can be -22- reduced by implementing with Fast fourier transform (FFT) algorithms [6]. The major advantage of an HR filter achieving the given characteristics, is that it requires far fewer coefficients and delay elements as compared to an FIR filter. In terms of software, it means lesser memory storage requirements or in hardware means lesser hardware resulting in lower costs. Moreover, the execution time would be reduced. But an HR filter cannot have linear phase and also limit-cycle oscillations can result due to quantization and roundoff. An HR filter can tend to be unstable too but that can be avoided by proper designing. In an application where linear phase is required, FIR filter will have to used. Using this property of linear phase, digital Hilbert transformers can be designed with FIR filters [7]. This will be considered in Chapter 7 while implementing the Phasing method of SSB generation. In the present application of SSB modulation of voiceband signals, the phase information is not critical as human ear is not intelligible to these phase distortions. Thus we can safely choose HR filters for our thesis as it saves computation time as well as program and data memory.

4.3 Design of HR filters

Designing a filter is basically a problem of finding filter coefficients such that the filter’s response approximates the desired characteristics. While discussing the various digital design techniques in this chapter, infinite precision filter coefficients have been assumed, i.e. the wordlength of the actual implementation has been neglected. The problem of finite wordlengths and there effects will be discussed in Chapter 5. Digital filters may be designed directly in the z-plane by squared magnitude function specifications or time domain method and need not be referenced to the analog theory. These techniques are described in detail in [6 ch4.13]. There are three main methods for designing HR filters in the s-plane first, and then transforming them to the z-plane : i. Matched z-transformation ii. Impulse invariant method iii. Bilinear transformation

Since Bilinear transformation has been used in this thesis, it will explained in detail while a brief note on the other two methods is presented. -23 -

4.3.1 Matched z-transformation : Using this technique the poles and zeros in the s- plane are mapped directly to the poles and zeros in the z-plane. A pole (or zero) at s = -a in the s-plane maps to a pole (or zero) at z = e~aT in the z-plane, i.e.

s + a —> l-z-1e-aT ...4.11 where T = 1 /fs is the sampling period.

The case, when the original transform function in the s-plane has a j-axis zero beyond fs/2 results in aliasing of the original analog response, in the digital response. This can cause severe distortion of the digital response and hence this method is not normally used.

4.3.2 Impulse Invariant method : In this method, the transformation applied is such that the impulse response of a digital filter, is the sampled version of the impulse

z-plane Figure 4.1 : Mapping in Impulse invariant method response of a known analog filter. If h(t) is the impulse response of the known analog filter, then the corresponding digital impulse response h(nT) is the sampled version of h(t). Thus the z-transform is given by

H(z) = £h(nT)z-n n=0

Knowing h(t), H(z) can be found for the required HR digital filter. This method has a disadvantage that strips of width 2rc/T in the s-plane are mapped onto the entire z-plane as shown in Fig 4.1. -24 -

4.3.3 Bilinear transformation : The bilinear transformation is defined by

z - 1 s —> z + 1 ...4.12

Fig 4.2 shows the mapping of s-plane into the z-plane. As seen in the figure, the entire jco axis in the s-plane is mapped onto the unit circle in the z-plane, with the origin of the s-plane corresponding to the pt.(+l,0) in the z-plane and jco = co mapping onto the pt.(-l,0).

Bilinear Transform

s-plane z-plane Figure 4.2 : Mapping in Bilinear transformation method

This eliminates the frequency aliasing errors present in other methods. The left half s-plane maps inside the unit circle in the z-plane and the right half is mapped outside the z-plane unit circle. The relationship between analog frequency, coA and digital frequency, coD is non-linear and is given by

codT coA = tan— ...4.13

Though bilinear transformation cannot be used to transform digital differentiators but still it is well suited for the design of lowpass, highpass, bandpass and bandstop filters, for which the frequency warping effect may be compensated. The compensation applied is illustrated in Fig 4.3.

First, the cricital frequencies for the digital filter are determined. Applying the frequency warping relationship (4.13), the corresponding analog frequencies are determined. Then the appropriate analog filter transfer function is obtained by conventional means. Finally, applying the bilinear transform (4.12) to this analog filter, -25 -

ft = 2 /T ion (ojT /?)

Analog

Figure 4.3 : Frequency warping compensation t the desired digital filter results. A FORTRAN program, 'BILINEAR', based on this method is attached in Appendix 3.

4.3.4 Optimization methods : Certain optimization procedures have been developed and are used to minimize a measure of the error (Lp norm, mean square etc.) in the desired frequency response. When the error criterion becomes smaller than a specified quantity or if the number of iterations reaches a specified maximum, the iterative procedure stops. These techniques have been described in [6 ch4.14] ,[8] ,[9].

4.4 Realization of Digital filters

Depending on the class of the filter i.e. FIR or HR, there are different structural forms available for the realization of digital filters. From (4.6), the most direct form of structure can be obtained for a general case. For the case of HR filters, some of the bk's are non zero, and thus the corresponding feedback loop would be present. But for FIR filters all bk's are zero and we have a structure as in Fig.4.4b and is known as a tapped delay line (TDL). For

t Ref [6] -26-

x(n) ------*1 !------*1 y(n) -i

x(n-l) !-- bl , - a> i y(n-l) i 1 i r -i -1

r b2 t x(n-2) ' l -c 32 1' ’ y(n-2)

x(n-N+l) UN-1 dN-l y(n-N+l) [ i -1 -i

x(n-N) 1-r bN aN i^ y(n-N)

Figure 4.4 : (a) Direct-form I HR filter (b) Direct-form FIR filter higher order HR filters, direct form structure is not used as its senstivity and roundoff noise are very high. Instead, HR filters are implemented using the parallel and cascade forms.

4.4.1 Parallel form : The parallel form is obtained by partial fraction expansion of the transfer function H(z) (4.10), i.e.

M-N W? Y0i + Yliz H(z) L Qz- i=0 i=t 1-aHz_1-c^iZ- ... 4.14

If M

4.4.2 Cascade form : The cascade form is obtained by factoring the transfer function H(z) (4.10) into first and second order terms, i.e. -27-

c

1 1 k ' Yoi Pi(n)

I k 1 k x(n) y(n)

ail 1 k

1 1 1 k

°-2\ \ 1 ------—------f

Y02 P2(n) 1 k i k >

al2 f ^

<*22 \ f

Figure 4.5 : Parallel form HR filter

™ Poi + PnZ-' + PaZ-2 (Z) l\ 1 - oc^ z_1 - o^j z~2 ...4.15

The transfer function H(z) (4.15) can be realized in either form I or form II as shown in Fig.4.6a&b, respectively. Unlike the parallel form, there are three degrees of freedom available when realizing a filter in the cascade form. Firstly, we can choose between form I and form II. Then, the sequential ordering of the sections can be specified. Finally, there are a number of combinations in which the poles and zeros can be paired together. We will see later in Section 5.7.3 that the choice of above factors could mean a difference in the output noise variance.

4.5 Digital oscillators

In SSB applications, the degree to which the unwanted sidebands are suppressed depends very much on the qualities of the cosine and sine function generators. The functions generated should be of the same amplitude and exactly 90° out of phase. The two basic approaches of designing digital oscillators are the recursive digital filter method and the Read Only Memory (ROM) look-up method. -28-

SECTION 1 SECTION 2

SECTION 1 SECTION 2

(b)

Figure 4.6 : (a) Cascade form I HR filter (Fourth order)

(b) Cascade form II HR filter (Fourth order)

4.5.1 Recursive digital oscillator : This method has been well explained by Jackson [7 chl3.3] and is briefly described here. As in the present application, we require a quadrature oscillator with two sinusoidal outputs of the same amplitude and frequency, but with a phase difference of 90° . A second-order recursive filter with poles on the unit circle, is 'marginally' stable. Ideally, it would produce a sinusoidal output, if the initial conditions are non-zero. The angle cocT of the unit-circle poles determines the frequency coc of the sinusoid.

Consider two causal impulse responses of the form -29-

h^n) = CoscocnTu(n)

h2(n) = Sin cocnT u(n) ...4.16 where u(n) is the unit step function. The corresponding system functions are

1 - (CoscocT) z"1 HjCz) = 1-2 (CoscocT) z-1 + z-2

(SincocT) z_1 H2(z) = 1-2 (CoscocT) z_1 + z~2 ...4.17

Figure 4.7 shows a two-output recursive structure with the above system functions. To start the oscillations, the z-1

cos coc nT Preset to 1

sin coc nT

cos OJj sin to T

Preset to 0

Figure 4.7 : Block diagram - Recursive digital filter oscillator registers can be preset to initial conditions of 1 and 0, respectively, resulting in the desired quadrature sinusoidal outputs h^n) & h2(n) for n > 1.

Under finite word-length conditions, the above oscillator would produce quantization noise. Quantization of the coefficients (CoscocT) and (SincocT) causes a deviation in the output frequency and amplitude, respectively. Due to the rounding of the output products from the (CoscocT) multiplier, roundoff noise is produced in the recursive loop. This causes a severe effect as the amplitude and phase of the output signals wander slowly over time. Due to the last effect, this method is not very popular.

4.5.2 ROM lookup table : Using high-speed digital processors like the TMS32020, -30- low distortion sinusoidal functions can be produced over a wide range of frequencies. This method has been described in [10].

Figure 4.8 : Direct lookup table t

The sine (or cosine) values for N, uniformly spaced angles around the unit- circle, are stored in a table. By stepping through this table, a sine (or cosine) wave can be generated. Whenever 360° is exceeded, we wrap around at the end of the table. Using the 'index' as the angle parameter and 'DELTA' as the step size, a sequence is generated :

S[mod(k x 'DELTA',N)] for k=l,2,3,...

The 'mod' operator provides the wrap around at the end of the table. This algorithm is illustrated in Fig.4.8, for N=8 and DELTA=0.6.

A longer lookup table would result in better approximation and resolution of the sinusoid generated.

The frequency of the sine wave is given by

'DELTA' TT r ------Hz txN where t, the sampling interval is in seconds. To satisfy the Nyquist criterion, we must have atleast two samples per sinusoid period i.e. 'DELTA' < N/2. This method is simple in concept and easy to implement t Ref [10] -31 - and thus was used in this thesis. For the present application a table of 128 uniformly spaced values has been constructed. The harmonic distortion produced by this method can be decreased by using an interpolation scheme [10]. But in doing so, the execution time would be increased considerably. Thus depending on the requirements of the application, we can trade-off between speed, accuracy, and the size of the ROM table. -32-

CHAPTER 5 : FINITE WORD LENGTH EFFECTS

5.1 Introduction

Theoretically, both the coefficients and the variables of a digital filter are considered to have infinite precision. So once the equivalent transfer function has been found by the design procedure discussed earlier, a set of design characteristics can be implemented on a digital filter. In practice however, all digital systems have only a finite number of bits to represent signals, with some kind of error being incurred as a result of the quantization process. The specific sources of quantization error in the implementation and operation of a digital filter are as follows :

i. The filter coefficients (multiplying constants) are quantized to a finite number of bits.

ii. The input signal samples are quantized to a finite number of levels (2b), where b is the number of bits.

iii. The results of arithmetic operations (like multiplication and addition) within the filter must usually be rounded or truncated to a specific number of bits. The accuracy of a digital filter is also affected by the exact filter structure, the type of quantization used to reduce the wordlength to a desired size and the type of arithmetic used in the filter algorithm. Each of the above mentioned effects have been discussed in this chapter.

5.2 Arithmetic in Digital systems

There are a number of different arithmetic types that could be used in digital systems. The most common ones are fixed point and floating point arithmetic. In fixed point representation, the position of the binary point is fixed, where all bits to the right of the point represent the fractional part and all bits to the left represent the integer part. We have a choice of using either l’s-compliment, 2’s-compliment, or sign-magnitude representation. Floating point arithmetic has an advantage that due to its large dynamic range, it does not require 'scaling'. But on the other hand it requires a lot more processing time and thus is not a practical choice for the present thesis. -33-

The TMS32020 digital signal processor uses 2’s-compliment fixed point arithmetic for number representation. It has single cycle instructions to perform addition, subtraction, or multiplication of fixed point numbers. Thus throughout the thesis, 2’s-compliment fixed point arithmetic has been assumed. We define the representation of numbers as a Q-format. For example, we say that a number has a Q12 format when there are 12 bits (representing the fractional part) to the right of the binary point. For more details on number representations in digital systems see any standard textbooks on digital arithmetic (for instance, [11 ch9], [6 ch5]).

5.3 Coefficient quantization

The parameters considered for digital filter designs are usually assumed to have infinite precision. However, for practical realizations these parameters (coefficients) must be quantized to a finite number of bits. With the quantization of filter coefficients to finite wordlengths, there are a finite number of positions on the z-plane which the poles and zeros may occupy.

Figure 5.1 : Grid pattern

As an example, consider a second order filter with transfer function H(z) = 1/(1 + az-1 + bz~2), where for complex poles p and p*, a = -2Re(p) and b = I p 12. Thus quantization of 'a' defines the uniformly spaced positions for real part of the poles and quantization of 'b' quantizes the radius of the poles with non-uniform spacing. As a result, the realizable pole positions lie on a grid as shown in Fig.5.1. The grid pattern and pole positions would depend upon the filter structure. It would be desirable to realize a given filter using a structure which has the densest grid -34 - near the ideal pole positions. Jackson [71 proposed a 'normal' (or coupled) form realization in which the possible pole positions form a uniform grid of vertical and horizontal lines. For an ideal filter with frequency response A(oo), the quantization of its coefficients oq , would cause A(co) to deviate. The coefficient sensitivity factor 5A/doq would give a good measure of such a deviation. One solution to the sensitivity problem is to select filter structures which are relatively insensitive to coefficient variations. High order filters, implemented with fixed-point arithmetic, are generally not realized in direct form because they have very high coefficient sensitivity. The sensitivity of the filter coefficients is directly related to the order of the denominator polynomial. Thus the cascade and parallel forms of first second order sections are preferred. After selecting the appropriate filter structure for given specifications, we need to quantize the filter coefficients in an efficient manner. Various computer aided methods, which minimize some error criterion, have been proposed [12],[13],[14].

5.4 Signal quantization

At the input of the system, the analog signal is converted into digital form using an analog to digital converter (ADC). The sampled analog signal is quantized to a finite number of levels (2b where b is the number of bits). If s(n) is the sampled input analog signal and Sq(n) is the equivalent quantized output of ADC, then the difference signal e(n) = s(n) + Sq(n) is called the quantization noise.

(a) Rounding (b) Truncation Figure 5.2 : Probability Distribution

The multiplication of a b-bit input sample by a b-bit filter coefficient results in a product which is 2b-bits long. This multiplication result has to be quantized back to b- bits else the number of bits required to represent the signal will increase indefinitely with further multiplications. Either rounding or truncation can be used to quantize the -35- signal s(n) or the multiplication result. In rounding, the nearest b-bit to the original unquantized value is taken. If Q = 2-b is the quantization step used for digital representation of a signal, then except for overflow and underflow conditions, the error signal e(n) satisfies the equation

-Q/2 < e(n) < Q/2

Truncation is achieved by representing the signal by the highest quantization level that is lesser than the signal itself. The error signal e(n) is given by

-Q < e(n) < 0

The probability distribution for rounding and truncation error are presented in Fig.5.2a & b, respectively. The variance of error for both types of quantizations is Q /12, but the mean value for roundoff error is zero, while it is Q/2 for truncation. There is also a third type of quantization known as the sign-magnitude truncation. For positive signals, it is similar to the normal truncation, but the negative signals are represented by the nearest quantization level that is greater than the signal. Thus the probability distribution for positive signals, is the same as in Fig.5.2a and its mirror image for negative signals. For such truncations, the mean value of error is zero but the variance is Q2/3, which is 4 times that for either of the first two types.

5.5 Roundoff noise

Since the ADC output and multiplication results in the filter need to be quantized, each can be considered as a noise source. A model for fixed point roundoff noise is shown in Fig.5.3. e

s------*(x)------* si Figure 5.3 : Roundoff noise model where e - roundoff/truncation error source s - original unquantized number (signal) sq - quantized number and 's' is either the filter input or a 2b-bits product of multiplication. -36-

Though the error sources due to multiplication product quantization are similar to input signal quantization, they differ in two respects : i) the data to be quantized is already in digital form, and ii) the rounding/truncation of the data takes place a number of times within the filter, and not just once at its input. Because of ii), the noise due to multiplication product quantization is much greater than input signal quantization. Assume that if the signals being rounded have sufficient amplitude and spectral content, then the roundoff errors from sample to sample are uncorrelated. Each roundoff noise source may be modelled as a random variable with probability distribution as shown in Fig.5.2b, with variance Q2/12. The advantage of making above assumptions is that the noise injected at each error source is then 'white', with power spectral density (psd) N0, and the output noise power spectrum can be computed by super-positioning of the noise spectra due to seperate error sources. The experimental validity of these assumptions has been confirmed by Jackson [15]. Let kj be the number of error sources at the j* summation node to the filter output. The scaled function has been considered because we would need to scale the signals within the filter to avoid overflow. This in turn would change the output noise level. The psd and variance of the total output roundoff noise may be calculated by simple superpositioning (adding) of the noise contributions from all noise sources. Thus the output noise spectrum is given by

Ne(co) = a02£kj I G'j(co) 12 ...5.1 where G09 is the variance of the noise from each rounding operation and kj = 1 , if rounding is performed after summation and not before.

The noise variance or total average power is then

J Ne(co) dco ... 5.2

Mitra et al [15A] have given a simple method for computing the output roundoff noise in digital filters. A FORTRAN program 'NOISE' based on this method is attached in Appendix 3. This program gives a theoretical insight into output roundoff noise for cascade and parallel forms of digital filters. Remember that in case of truncation, the quantization noise is the same as that for rounding but with a non-zero mean. The output roundoff noise depends on the type of filter structure used, the 'mode' of arithmetic employed and the number of bits used to represent the data within the -37- filter.

5.6 Overflow and Scaling

For a given filter structure and quantization step size, the output roundoff noise is fixed. This could tempt us in thinking that by increasing the signal levels at the nodes, signal-to-noise ratio (SNR) of the filter could be improved. But for fixed point arithmetic addition, this could cause the result to exceed the available dynamic range (i.e. overflow). Overflow means severe non-linearity or distortion in the system and should thus be avoided. At times, even large amplitude self sustained oscillations could result [16]. The digital filters should be so designed that under normal operating conditions, probability of an overflow is extremely small. Since summation nodes are the only places where overflow can occur, scaling factors are required to be inserted at the branches feeding into these nodes. In case of summation of more than two numbers, the magnitude of the total sum should be within dynamic range limitations, irrespective of the order in which the numbers are added, even if an overflow occurs in one of the partial sums. This condition also holds for the case where one of the inputs to the summation node has overflowed due to multiplication by a coefficient of magnitude greater than one. In general, to avoid performing additional multiplications, scaling factors are incorporated into the existing filter coefficients. Rabiner et al [6] and Jackson [15],[17] have presented the theory for selecting scale factors to avoid overflow while maintaining the largest possible signal-to-roundoff noise ratio in the filter. Using the same notation, this theory has been summarised here. The input and output to the filter are denoted by x(n) and y(n) respectively. The output from the i111 summation node is v^n). The impulse response from the filter input to the output of the i* summation node is fj(n). The impulse response of the ith summation node is g}(n). The transfer functions X(Z), Y(Z), F^Z) and G^Z) are the z-transforms of x(n), y(n), fj(n) and gi(n), respectively. The scaling procedure described by Jackson [15],[17] and Rabiner et al [6] requires the knowledge of the class of input signals (i.e. bounded energy or bounded spectrum). We define Lp norm (p > 1) of a Fourier transform A(d03) as -38-

II Allp A^05) dco ... 5.3

From the above definition we see that Lj norm is the mean absolute value of A(e^co) while L2 norm is the rms value. It can be shown that when the integral is finite

11A11 p — max _n < w < n A(ejco) 5.4

Hence the LM norm of ACe^) is the peak value of IA^03) I over all co . In general, it can be shown that [15]

I Vi(n) I < 11 Fj 11 p* 11X11 q ...5.5

with ~ — = 1 p, q > 1 p q

If we let Fj(co) = 1 then 11 Fj 11 = 1 for all p > 1 which gives

| Vi(n) I = I x(n) I < 11X11 q = 11 Vj 11 q, q > 1 ...5.6

Rewritting Eq.5.5, we get

11 Vi 11 ! < 11 Fi 11 p- I I X I I q , ... 5.7

Thus from above equations, we can imply that the mean absolute value of V^e3"), 11 Vi 11 i is bounded by 11 Fj 11 p 11X11 q , which in turn provides a bound on I Vj(n) I. If the Lq norm of the input is known then a scaling criterion for Fi(dco) can be found. For example, if IIX llq < 1, (q > 1) then it is required that the scaled F^e-^) must satisfy the condition

l|Fi"psl* p=^r ...5.8

The most significant cases are :

i. p = oo, q = 1 : This corresponds to an input sinusoidal signal and a bounded peak spectrum level of F^05).

ii. p = 2, q = 2 : This corresponds to bounding the energy of both the input and the transfer function F^e^). -39-

iii. p = l, q = «» : This corresponds to knowing the peak magnitude of the input spectrum and bounding the L1 norm of F^e105).

Relations (5.5) and (5.7) do not hold for random input signals because there Fourier transforms are undefined. Thus to derive a bound on the variance of the output signal, the power spectral density and autocorrelation functions of the random signal are used [11].

For the case p=l, q = when the input power density spectrum is white

... 5.9

where gv. is the variance of vj(n)

Gx is the variance of x(n).

To ensure that Gv. < Gx , the scaled transfer function must be bounded, i.e.

11F 'i 112 - F Still, this does not guarantee the complete absence of overflow and the probability of overflow can be made arbitrarily small by appropriate scaling. The psd of the output noise after scaling is given by

Ne(co) = Oq £K'j I G'j(co) 12 5iq

where dashes indicate scaled quantities.

5.7 Finite wordlength in Digital filters

The application of the results obtained in the preceding sections are presented here for the different forms of filter structure.

5.7.1 Direct form : Consider a transfer function of the form

-1 —M OCn + OCi Z + * ‘ * + OL,. Z H(z) = ~——;------^ M ■ i+ p,z_1+• • •+pmz_M ...5.11

The direct form configuration with scaling is implemented in Fig.5.4. The sensitivity of the transfer function H(z) to the denominator coefficients is given by

0FT(e]CO) 3pi ...5.12

As pointed out by Kaiser [18], the use of the direct form is to be avoided because of higher sensitivity of the roots of higher-order polynomials to small -40-

u(n) y(n)

Figure 5.4 : Direct-form with scaling deviations (i.e. quantization errors) in the polynomial coefficients. Moreover, direct form has higher output roundoff noise than other filter forms.

5.7.2 Parallel form : The parallel form structure is obtained by partial fraction expansion of the transfer function H(z), and is given by

-l Yio + Yiiz H(z) = Yo+Z -2 i+1 1 +Pilz 1 + Pi2z ...5.13

To satisfy the dynamic range constraints discussed in Section 5.6, scaling factors q must be inserted at the input of each section. Also the output multipliers y0i and yn must be oppositely scaled to maintain the original gain through each section, i.e.

y'ji = Yji/Cj j = o,i where q = 1 / 11 Fj 11 p The scaled transfer function becomes

Yio + Yiiz 1 H'(z) = Yo + Sci 1 + PiiZ_1 + Pa z~2 ...5.14

Once the scaling factors have been found, the design is fixed and the output roundoff noise may be calculated using the methods described in Section 5.4.

In the parallel form, the zeros of the filter are not realized by individual first- or second-order terms, but by adding all the parallel section transforms together. This means that all the numerator coefficients y^ affect every zero, which in turn creates a -41 -

x(n) y(n)

Figure 5.5 : Parallel form with scaling highly sensitive situation. Thus the parallel form is not recommended for filters with demanding attenuation requirements.

5.7.3 Cascade form : From the above cases, it is clear that under coefficient quantization the cascade form is more robust than other forms. The cascade form structure is obtained by factorizing H(z) into first- and second-order polynomials and is given by

m ai0 + an z 1 + ai2 z 2 H(z) = n f=i 1 + Piiz 1 + p,2z-2 ... 5.15

The scaled signal flowgraphs for the two commonly used ways of realizing (5.15) are shown in Fig.5.6a,b. These structures have been termed as forms I & II, respectively, by Jackson [15],[17]. Note the differences in the scaling structure between the two forms. Unlike the parallel form, we have a number of design flexibilities while realizing a filter in the cascade form. Firstly, there is the choice between forms I & II. Then there are many -42-

u(n) ——

a'2, (a)

(b)

Figure 5.6 : Cascade form filter with scaling (a) Form I (b) Form II combinations in which the numerator and denominator factors can be paired together in second-order sections. Finally there is a freedom over the sequential ordering of the sections. The choice of the above three factors could result in a significant difference in the output noise variance. Hence we briefly to derive the rules to obtain the combination which minimizes the roundoff noise. To obtain a good pairing of numerator and denominator factors, it would be reasonable to minimise some norm of the individual section. A simple rule to minimize -43 -

Im(z)

Rc(z)

Figure 5.7 : Pole-zero pairing

the individual norms of each section, i.e. minimize 11 oq/pi 11 «*,, has been developed by Jackson [17].

Accordingly, as shown in Fig.5.7, the poles closest to the unit circle are paired with the zeros nearest to them. Then pair the next closest poles to the unit circle with the remaining zeros nearest to them and so on.

ll Ny Hr r= 1 r = °o

P=2 INCREASING pj DECREASING pj

INCREASING pj INCREASING pj

Table 5.1 : General rules for ordering cascade form sections

Next, the paired sections need to be sequentially ordered. The sections preceeding a given one, determine the scaling for that section involving an Lp norm and the sections following it filter the roundoff noise produced by that section. The norm is more sensitive to the maxima of its argument than the L2 norm (which is the rms value), and thus a good, but not optimum ordering would be one that minimizes the arguments of the LM norm. The paired sections should be ordered according to their relative 'peakedness' . For p = <», we want the most peaked section to be placed towards the end of the cascade and thus the sections are ordered from least-peaked to most- -44-

peaked. The preferable rules for ordering of paired sections are summarized in Table 5.1.

Jackson [17] defined 'peakedness' as

Oj

Pi oo peak of section response Oj rms of section response Pi z ...5.16 Jackson [17] presents a computer simulation to support the validity of his analysis. Lee [19] used a 'minimax noise' principle as a tool for pairing numerator and denominator sections and then ordering them to minimize roundoff noise under a sinusoidal input (i.e. scaling). The variance, or total average power, of the output roundoff noise is given by (from 5.8)

2 m Ne(co) = IG'j(co) I j=l

Consider the Lr norm of Ne(co) (see Section 5.4). Ny(co) is the peak of the noise power spectrum while the norm corresponds to the variance of the output noise. We can minimise either the peak of the noise spectrum or the variance of the noise.

Q2 M II N„ IL = niZ j=i2VIGj ...5.17

G'j(co) is dependent on the Lp scaling criterion used.

The two main cases are (p= °° , r=l) and (p=2, r= °°). Jackson [17] derived expressions for 11 Ne 11 r; r=l, °o for forms I & II as a function of the Lp scaling norms. From these expressions Jackson concluded that form II is to be preferred for the case (p= oo , r=l) and vica versa for (p=2, r= ©o). For the other combinations (p= , r=l) and

(p=2, r= oo) there is not much difference between the two forms. The zeros are roots of only first- or second-order polynomials and are thus less sensitive than the roots of higher-order polynomials.

5.8 Limit cycle oscillations

While considering the roundoff noise in digital filters it was assumed that the signal amplitude is much greater than a single quantization step size. Further we -45- assumed that the roundoff noise sequence is uncorrelated with itself as well as the input. But for many cases the above assumption does not hold, for example, when the input is a low level signal or a periodic signal. For such a case , the roundoff noise cannot be assumed to be white. The correlated nature of these errors gives rise to limit cycle phenomena. A limit cycle of length L exists if the output sequence satisfies the relationship

Yn+L = Yn ...5.18 where L is the smallest integer for which the equation holds. Such a sequence could result from a zero, constant, or a periodic input sequence. For the case of periodic input signal, the length is an integer multiple of the input sequence length. There are two factors which could result in limit cycles. The first type of limit cycle results from rounding or truncation of multiplier outputs and occurs more often. Jackson [20] covered his study over first and second order limit cycles in second order digital filter sections using fixed point arithmetic. Jackson observed that, in the case of first and second filters, limit cycles can occur only if rounding results in poles on the unit circle. The second is due to overflow of the finite length registers during addition with two’s compliment arithmetic. This behaviour was first observed by Jackson and the conditions for the existence of such oscillations were derived by Ebert et al [16] To eliminate the occurence of the overflow limit cycles, they proposed the use of a saturating non-linearity in the two’s compliment adders. The overflow due to addition has been taken care of by proper scaling of the filter coefficients (see Section 5.6). Kao [21] mentioned a method by which zero input limit cycles could be eliminated. According to it, if the input signal stays below a given level for a certain period of time, then the threshold detector circuit installed should reset the register to zero. This was implemented in the thesis by means of software on the TMS32020. The macro 'THRES' is listed in Appendix 4.

5.9 Coefficient sensitivity and roundoff noise

Fettweis [22],[23] stated that there is a close relation between coefficient sensitivity and roundoff noise and derived an expression for the roundoff noise to signal ratio in terms of the coefficient sensitivity. The theory has been briefly summarized here.

Consider a fixed point digital filter with transfer function H(co) and with N scaled coefficients Cj. Let F ^(co) be the scaled transfer function from the filter input to -46- the multiplier input and G'^co) be the scaled transfer function from the multiplier output to the filter output. Then the sensitivity of the scaled transfer function H(co) with respect to the scaled coefficient q is given by

8H(co) F 'i(co). G'i(co) 5q ...5.19

The above relation can be explained by considering the rounding operations after multiplication as fluctuations in the multiplier coefficients. Thus all methods of reducing the amplitude changes at the filter output due to coefficient variation also reduces the roundoff noise at the same output. As mentioned in [24], other factors like ordering and pairing of sections (for cascade form) also affect roundoff noise (see Section 5.7).

A number of alternate recursive filter structures have been proposed [25],[26],[27] which have low roundoff noise and low sensitivity. Bhattacharya et al [28] achieve this by combining poles and zeros such that the most sensitive section has the largest possible scale factor and so on. Acha et al [28] have presented a low-noise realization which is also free from overflow oscillations. -46-

CHAPTER 6 : TMS320 DIGITAL SIGNAL PROCESSOR

This chapter gives a description of the TMS320 digital signal processing (DSP) family. Since TMS32020 was used in the thesis, its architecture and memory organization have been described. The special features, of the TMS32020, used in the thesis have been elaborated in more detail.

6.1 TMS320 family of Digital Signal Processors

The TMS320 family of processors contains the first MOS microprocessor capable of executing five million instructions per second (MIPS) and thus can support a wide range of DSP applications requiring high speed and extensive computations. Besides a set of general purpose instructions, many special instructions have been incorporated to enhance the speed of execution of DSP algorithms.

1ST GENERATION 2ND GENERATION a 3R0 GENERATION

^»^TMS32020 .TMS320C15-S TMS32X17-25 ffgg TMS320C10-25 TMS320C15/E15 TMS32010-25 TMS320C17/E17 TMS32010 TMS320C10 TMS32011

TMS32010-14'

TIME WAiH.otJgTCDoecDwmi.ttm

| * 3fitn NMOS 2fjm CMOS 1um CMOS

Figure 6.1 : TMS320 family growth

High speed and flexibility are a result of a modified Harvard architecture utilized by the TMS320 family. In strict Harvard architecture, the program and data memories are placed in two separate address spaces, allowing fetch and execution to be completely overlapped. The TMS320 family’s modification to the architecture permits the transfer between program and data spaces. It increases the flexibility of the processor and eliminates the need for a separate coefficient ROM because the -47 -

coefficients stored in program memory can be read into the RAM.

The above features are common to all TMS320 family processors. Additionally, special features of each processor enables to choose a particular device depending on the cost/performance trade-offs for a given application. The growth of the TMS320 family in terms of performance and software compatibility is shown in Fig.6.1.

TMS32010 NMOS 200 .9 16-bit integer 144 4K 3rd party TMS32010-14 NMOS 320 .9 16-bit integer 144 4K 3rd party TMS32010-25 NMOS 160 .9 16-bit integer 144 4K 3rd party TMS32011 NMOS 200 .9 16-bit integer 144 1.5K 3rd party TMS320C10 CMOS 200 .165 16-bit integer 144 4K 3rd party TMS320C10-25 CMOS 160 .2 16-bit integer 144 4K 3rd party TMS320E15 CMOS 200 .3 16-bit integer 256 4K 3rd party TMS320C15 CMOS 200 .225 16-bit integer 256 4K 3rd party TMS320C15-25 CMOS 160 .25 16-bit integer 256 4K 3rd party TMS320E17 CMOS 200 .325 16-bit integer 256 4K 3rd party TMS320C17 CMOS 200 .25 16-bit integer 256 4K 3rd party TMS320C17-25 CMOS 160 .275 16-bit integer 256 4K 3rd party

TMS32020 16-bit integer TMS320C2S , . 16-bit integer ■mm.

* Floating-Point/Integer f External DMA ** Unlimited t Internal/External DMA

Table 6.1 : TMS320 family comparison

A summary of the comparison between different members of the TMS320 family is presented in Table 6.1. On comparison we see that with each generation, tendency has been to reduce cycle time (i.e., achieve higher speed), and increase the memory capacity considerably. The typical applications of the TMS320 family have been summarized in Table 6.2.[10]

Special features of the TMS32020, like the single-cycle multiply/accumulate instructions, 32-bit arithmetic and five auxiliary registers with their own arithmetic units, makes it very useful for digital signal processing applications. Moreover, its -48-

GENERAL-PURPOSE DIGITAL SIGNAL GRAPHICS/IMAGING INSTRUMENTATION TELECOMMUNICATIONS PROCESSING

• Digital filtering • 3-D rotations • Spectrum analysis • Echo cancellation • Correlation • Robot-vision • Function generation • ADPCM transcoders • Hilbert transforms • Image transmission/ • Pattern matching • Digital PBXs • Windowing compression • Seismic processing • Line repeaters • Fast Fourier transforms • Pattern recognition • Channel multiplexing • Adaptive filtering • Image enhancement • 1200-19200 BPS modems • Waveform generation • DTMF • FAX VOICE/SPEECH CONTROL MILITARY • Cellular telephones

• Voice mail • Disk control • Secure communications • Speaker phones • Vocoding • Servo control • Radar/sonar processing • Digital speech interpolation (DSI) • Recognition • Robot control * Image processing • X.25 packet switching • Enhancement • Laser printer control * Navigation • Voice/data compression

Table 6.2 : Typical applications of the TMS320 family

flexibility enables it to be configured for a wide range of system requirements.

6.2 TMS32020 DSP

The TMS 32020, along with TMS320C25, is a second generation member of the TMS320 family. The architecture of TMS32020 is based upon that of the TMS32010. The increased memory, expanded and improved instruction set, and additional hardware enhanced the TMS32020’s performance two to three fold over that of TMS32010. Most of the instructions can be executed in a single machine cycle, and this increases the software throughput. With the TMS32020, emphasis has been on improving overall system speed, communications, and processor flexibility. Some of the major features of the TMS32020 are as follows :

• 544 words of on-chip data RAM, with an option of configuring 256 words as either data or program memory. ^

• 128K words of memory space (64K words of program memory and 64K words of data memory. ^

• Global data memory interface. '

• Wait state for communicating with slower off-chip memories. 1

• Upward-software compatibility with the TMS32010. -49-

• On-chip timer. ^

• Single-cycle multiply/accumulate instructions. ^

• Repeat instruction for streamlining program space and execution time.

• Serial port for multiprocessing or interfacing to serial analog to digital converters etc. *

• 16-bit parallel interface.

• Block moves for data/program memory management.

• 0 to 16 bits scaling shifter.

• Five auxiliary registers, each with its own arithmetic unit. ^

• Instruction set support for floating-point operations. ^

• Three external maskable interrupts. ^

All the features marked ^ are also the advantages of the TMS 32020 over the TMS32010. Besides the TMS32020, the TMS 32010 Evaluation Module is also available in the School. The choice between the two processors depends on the cost/performance tradeoff. The TMS32020 is the natural choice because the cost difference between the two is marginal whereas the advantages and special features of the TMS32020 outcast TMS32010 completely. The block diagram of the TMS32020, shown in Fig.6.2, illustrates the principal blocks and data paths within the processor and also the interface pins. A summary of the internal hardware is presented in Table 6.3. A detailed description of the architecture and internal hardware are available in [29]. Here, only the special features (in software and hardware) exploited in the thesis have been presented.

6.3 Memory organization

The 544 words of the on-chip data RAM are divided into three separate blocks B0, Bl, and B2. Out of these, 288 words (i.e., blocks B1 and B2) are always data memory while the rest of 256 words (block B0) could be configured either as data memory or program memory, depending on the requirements. This special feature of block B0 provides a flexibility on the limited on-chip data RAM available. Using the -50-

I *8 o o / PROGRAM BU8 w

ROe) R/W4----- 8TO(10) 8TRB4----- 8TK1C) READY----- ► r> i RPTCW BR«---- \MUX/ FRW ___XF8------HOLD----- ► H0LDA4----- —FBR I Pc(ie) | 13558---- -♦OX ao—♦ ♦-^ -CLKX "RB---- ► rex Tacm— iw i* DRROe): i C' Sf(2-0)f\\____/3 Wxffi DXR(16U ▼ ▼ TtMoe) PRCX16) A16-A08- IMR(8) QREQ(8)

Die-0047^*-j|J PR0GAAM BU6

DATA BUS

/# /i« /ie /ie 1 r |8HFTER<0-ie)| TRiW) \MUX/ AROQ8) lOPWl ARK 16) MULTFUBt AR208) f ARP<3) h/3- /« 7 L8B AR3<10) FROM IR PRO 2) /* AR4(16) i r IahbO) \ I 8HFTER(-6.0A4) I AHALX18) > 432

-4—^ \MUX/

^Fie yMUX>

BLOCK 82 / (32 x 16) 32

DATA RAM DATA/PROG lAccHde) ACCLdeH BLOCK B1 RAM (256 x 18) (258 x 18) BLOCK BO 32

l 8HFTER8(0.U) I

/mux\

r DATA BUB -X NOTE: ACCH= Accumulator high DRR = Serial port data receive register IR Instruction register ACCL= Accumulator low DXR = Serial port data transmit register PR Product register ARAU= Auxiliary register arithmetic unit GREG= Global memory allocation register PRD Period register for timer ARB = Auxiliary register pointer buffer IFR = Interrupt flag register TIM Timer ARP = Auxiliary register pointer IMR = Interrupt mask register TR Temporary register DP = Data memory page pointer RPTC = Repeat instruction counter ST0.ST1 Status registers

Figure 6.2 : Block diagram of TMS32020 digital signal processor -51 -

UNIT SYMBOL FUNCTION PROCESSING ELEMENTS Arithmetic Logic Unit ALU A 32-bit two's-complement arithmetic logic unit having two 32-bit input ports and one 32-bit output port feeding the accumulator. Central Arithmetic Logic CALU The grouping of the ALU, multiplier, accumulator, and scaling shifter. Unit Multiplier MUL A 16 x 16-bit parallel multiplier. Period Register PRD A 16-bit memory-mapped register for reloading the timer. Program Counter PC A 16-bit program counter for addressing program memory, and for addressing data memory when using the block move (BLKD and BLKP) and multiply/accumulate (MAC and MACD) instructions. Random Access Memory RAM (BO) A RAM block with 256 x 16 locations configured either as data or program (data or program) memory. Random Access Memory RAM (B1) A data RAM block, organized as 256 x 16 locations. (data only) Random Access Memory RAM (B2) A data RAM block, organized as 32 x 16 locations. (data only) Auxiliary Register ARAU A 16-bit unsigned arithmetic unit for performing operations on auxiliary Arithmetic Unit register data. Repeat Counter RPTC An 8-bit counter to control the repeated execution of a single instruction. Shifters SFL, SFR Shifters SFL (left) and SFR (right) are located at the ALU input, the accu­ mulator output, and the product register output. Also an in-place shifter within the accumulator. Timer TIM A 16-bit memory-mapped timer (counter) for timing control. Accumulator ACCH(31 -16) A 32-bit accumulator split in two halves: ACCH (accumulator high) and ACCL(1 5-0) ACCL (accumulator low). Used for storage of ALU output. Auxiliary Register File AR0.AR1, A register file containing 5 16-bit auxiliary registers (AR0-AR4), used for AR2.AR3, addressing data memory, for temporary storage, or for integer arithmetic AR4(1 5-0) processing through the ARAU. Auxiliary Register Pointer ARP(2-0) A 3-bit register for selecting one of the five auxiliary registers.

Table 6=3 : Internal hardware

on-chip program RAM makes the processor run at full speed without the need to go to the wait states. It also cuts down the system costs by not requiring extra high-speed external program memory. Moreover, certain instructions (e.g. MACD) require that the program memory value must reside in block BO, with block BO configured as program memory.

A number of TMS 32020 instructions which utilize the data and program memory effectively for data and program block move, and data move operations are summarized as below :

i. The BLKD instruction moves a block within data memory. The BLKP instruction moves a block from program memory to data memory. Both instructions can operate on both on- and off-chip memory. -52-

ii. DMOV copies a word from the currently addressed data memory location to the next higher location. This instruction is very useful for digital filtering as it implements the z-1 delay operation.

iii. The LTD instruction loads the T-register with a new data, accumulates the previous product and copies the data to the next higher location. It is again useful for digital filtering.

iv. The MACD instruction performs the multiplication, accumulates the product, and copies the data to the next higher location. It performs the MAC and DMOV instructions together.

6.4 Multiplication and addition

The finite wordlength effects in digital systems are directly related to the number of bits available for representing data and also for arithmetic operations. The TMS32020 has a two’s compliment 16 by 16-bit hardware multiplier, which is capable of computing a 32-bit product in a single machine cycle. This 32-bit product is held in the Product register (PR) or else it could be shifted over to the 32-bit accumulator. Using the MAC or MACD instructions, we can add together two or more product results in the accumulator. The final result after addition can then be reduced to a 16-bit number while storing. Rounding (or truncation) after summation introduces lesser error as compared to the rounding (or truncation) before summation. While multiplying two fractional numbers in Q-format, one has to shift the product to bring it back to the same Q-format as before. Consider, that the two numbers multiplied are Q15 numbers. The product would then be a Q30 number. Therefore, by shifting this product to the left by one bit and storing the higher 16-bits using SACH instruction we get a Q15 number again. The shift can either be specified through product shift mode (PM) field of the status register ST1 or in the instruction itself.

6.5 System control and speed utilization

6.5.1 Timer and synchronization : The TMS32020 has the feature of generating an internal timer interrupt. The timer is controlled by the on-chip timer (TIM) and the period (PRD) registers which can be programmed through software. The TIM register holds the current count and is decremented by one every fourth CLKOUT1 cycle (i.e., every 80 nsec or at 5 MHz frequency). A timer interrupt (TINT) is generated when the timer decrements to zero. The PRD register holds the initial count down value and -53 - reloads it in the TIM register within the same cycle that it reaches zero. Internal timer is an extremely useful feature when an exact sampling frequency is required and was used throughout the thesis. Earlier, when a timer was not available (like on the TMS32010), one had to depend on external interrupt or on the execution time of the program itself for timing. This certainly was not recommendable as exact sampling frequency does play a major role in digital signal processing.

6.5.2 Repeat instruction : Using the repeat (RPT or RPTK) instruction, a single instruction can be executed upto 256 times. The repeat counter (RPTC) is loaded with a value one less than the number of times the next instruction is to be executed. During the repeat instruction, all interrupts are masked automatically because RPTC cannot be saved. The repeat feature is very useful with the block moves, table read/writes and multiply/accumulate instructions. Normally each of these instructions require three cycles but they can be pipelined with a repeat instruction to effectively become single­ cycle. Thus for certain multi-cycle instructions, repeat instruction could save a lot of execution time.

15 14 13 12 11 10 9, 8 7 6 5 4 3 2 1 0 I RESERVED

Figure 6.3 : Interrupt Mask Register (IMR)

6.5.3 Interrupts : The TMS32020 has three external interrupts (INT2 - INTO), while the internal interrupts are generated by the timer (TINT), the serial port (RINT and XINT), the TRAP interrupt and the reset (RS). The internal and external interrupts are maskable, except for reset, through Interrupt Mask Register (IMR) (Fig.6.3).

INTERRUPT MEMORY NAME LOCATION PRIORITY FUNCTION

0 1 (highest) External reset signal

TnTO 2 2 External user interrupt #0 TNT1 4 3 External user interrupt #1 TNT2 6 4 External user interrupt #2 8-23 Reserved locations TINT 24 5 Internal timer interrupt RINT 26 6 Serial port receive interrupt XINT 28 7 (lowest) Serial port transmit interrupt TRAP 30 N/A TRAP instruction address

Table 6.4 : Interrupt locations and priorities -54-

When an interrupt occurs, the program counter goes to a predefined Vector location to pick up the address for the Interrupt Subroutine (ISR). These Vector locations along with the priorities are shown in Table 6.4.

6.6 Registers

6.6.1 Status Registers : The status of various conditions and modes of the machine while executing a program are stored in the two status registers, STO and ST1 (Fig.6.4).

15 14 13 12 11 10 9 6 7 6 5 4 3 2 1 0 ARP lovbvMl 1 kr np »-i

15 14 13 12 11 10 9 e 7 e 5 4 3 2 1 0 ARB ICNFlTC |SXM| 1 1 1 1 1 I XF | F0 |TXM| PM

Figure 6.4 : Status Register organization

For details on each of the individual status bits refer to TMS32020 User’s guide

[29 pp 5-6]. The feature that the status registers can be stored into- or loaded from- data memory allows the machine status to be saved and restored for subroutines and interrupts.

REGISTER ADDRESS NAME LOCATION DEFINITION

DRR(1 5-0) 0 Serial port data receive register DXR(15-0) 1 Serial port data transmit register TIM(1 5-0) 2 Timer register PRD(1 5-0) 3 Period register IMR (5-0) 4 Interrupt mask register GRLG( /-O) 5 Global memory allocation register

Table 6.5 : Memory-Mapped Registers

6.6.2 Memory-Mapped Registers : There are six data memory mapped registers which can be accessed like any other memory location. The TIM and IMR registers have already been explained. The DRR and DXR are used for communicating with serial devices, e.g. serial A/D converters. In the thesis, parallel A/D and D/A converters were used because they are much faster than serial converters and thus the DRR and DXR registers were not required. The global memory allocation register (GREG) specifies certain data memory as global which is useful for -55- multiprocessor applications.

6.6.3 Auxiliary Registers : The five auxiliary registers (AR4-AR0) could be used for indirect addressing of data memory or temporary loading (or storage) of data. The feature of the auxiliary registers to be used as counters or pointers is also supported by the instruction set. At times this results in a saving of the program memory storing variables and also a reduction in the execution time of a process. A particular AR can be selected by programming a 3-bit Auxiliary Register Pointer (ARP).

6.6.4 Program Counter and Stack : A 16-bit Program Counter can address internal and external program memory to fetch instructions for executing. A four-location hardware program counter stack available on the TMS32020 to be used during subroutines, interrupts, and certain special instructions. The contents of the program counter can be pushed onto- or read from- the top of the program counter stack using PUSH and POP instructions respectively.

6.7 Software Development System (SWDS)

The TMS32020 SWDS is a Personal Computer (PC) resident software development tool which has been designed to function in IBM-PC/AT and TI-PC environment, including their compatibles. The SWDS can plug into any full-size slot available on a machine. The SWDS takes up 64K bytes of PC memory. It is equipped with 24K words (48K bytes) of 25nsec static RAM which allows the TMS32020 to operate at 20 MHz crystal frequency. The TMS32020 SWDS can accept a clock from an external crytal, provided it has been specified in the Debug Monitor initialization (INIT) command. There is also a provision of providing a clock from a target system, to which the SWDS is connected. While in the PC’s directory containing the SWDS software, the system can be activated by entering 'TMS' . 'TMS' is a batch file for setting up parameters and invoking 'SWDS' program. The Debug Monitor screen is displayed with a command line at the bottom. The HELP command can be used to list categories which explain much of the SWDS and Debug Monitor operations. The INIT command is used to configure the SWDS RAM space and select the clock source for the system. Unless it is necessary to change these parameters, the INIT command need not be executed again. From the Debug Monitor environment, the EDIT command executes the text editor program and is used to edit a source file. The TMS320 Macro Assembler -56- available translates a TMS 32020 assembly language source code into executable object code. The Macro Assembler supports the macro calls and definitions along with conditional assembly.

6.7.1 Debugger : After assembling the source file, we can load, execute and halt the object code file either from the Debug Monitor command environment or by first entering the Debugger (DEBUG command) and then issuing the commands from there. On entering the debugger, the screen format is changed to one optimized for debugging algorithms with different windows displayed on the screen. The upper window displays the machine status including the contents of all the registers and the status bits. By selecting the window, contents of any register can be changed. The reverse assembly window displays the program. While single-stepping or executing a program, this window will follow the program counter. The window can be scrolled up and down or even moved to another part of the program. By selecting the data/program memory window, any part of the data or program memory can be displayed and/or modified.

While in the debugger, the following commands are available :

i. L load a new object code program from disk and reset processor state

ii. B to modify, enable or disable any of the 8 breakpoints

iii. R run a program without breakpoints

iv. E run a program with breakpoints

v. G run to a specified address

vi. S to show a file

vii. Q return to Debug Monitor

Any of the above commands could have been invoked even by their equivalent commands in the Debug Monitor. The format of the screen while in the debugger is very beneficial for single­ stepping, executing or running a program. For example, one can keep track of the changes occuring to the machine status and the contents of the data memory. Moreover, changes to any of the windows can be made on the screen itself. -57-

6.7.2 Simulator : A Simulator, which is an alternative debugging tool, is available in the School for the TMS320C25. It is a software program which can be used to simulate operations of the TMS320 (DSP). The simulator for the TMS32020 is also available but the one for TMS320C25 was found to be more convenient. The simulator uses the object code produced by the Macro Assembler. While executing a program, the internal registers and memory of the simulated TMS320 are modified as each instruction is interpreted by the host computer.

6.7.3 Evaluation Module (EVM) : The EVM is a cheaper standalone single-board system having all the tools necessary for TMS32020 and provides in-circuit emulation. An EVM circuit was designed in our School by Mr. C.Hollier as part of his post­ graduate studies in 1986. In the beginning, much time was spent in assembling and testing the EVM board to be used as a tool in software debugging system. Most of processor commands for the EVM are the same as those for the SWDS from Texas Instruments. For single-stepping there is a TRACE command instead of the STEP command as on the SWDS. The EVM cannot execute the DOS commands but still it is a good low cost system. At a later stage, the EVM board was found to have a few bugs in hardware and software and could not execute some of the instructions it was designed for. The board could not perform a memory transfer operation required for implementing a program. j As the board stands, it needs several improvements and would require to be a part of another thesis project. Hence for major part of the thesis the TMS320C25 simulator and the SWDS were used for debugging.

NB : All figures and tables in Chapter 6 have been taken from [10],[29],[42]. -58-

CHAPTER 7 : IMPLEMENTATION

In this chapter the digital implementation of Weaver’s method of SSB modulation will be described. Its performance under standard, as well as real voiceband signals will be discussed. Then a method of improving the sampling rate of the system has been presented. In the end, the possibility of digital implementation of other SSB generation methods has been considered, along with the results obtained for the same.

7.1 Supporting Equipment

The facilities available in the School enabled all the programs to be written in the assembly language for the TMS32020. Using the TMS32020 Software Development System (SWDS), one can assemble a given program, load it and debug using reverse assembler. As explained in Chapter 6, SWDS is a Personal Computer (PC) resident software tool which also provides software development support for the TMS 32020 digital signal processor. For implementing a complete SSB modulation/demodulation system, two PC’s are required, each with its own SWDS, where one is used as a transmitter and the other as a receiver. To be able to operate on the real time analog signals, external circuitry to each of the SWDS was connected. In each case, an analog signal is converted to its digital equivalent using an ADC and fed to the SWDS for processing (i.e. SSB modulation or demodulation) and the processed signal is converted back to analog using aDAC. After the programs for realizing a particular type of SSB system had been written and assembled on each of the SWDS microprocessors, next step was be to test if they were being implemented satisfactorily. It was realized that before applying the actual voiceband signal it was worthwhile to test the system using sinusoids of single frequency or sweeping over a band of frequencies, obtained from a signal generator. This gave an indication of the behaviour of the transmitter and receiver separately and then together. After getting the satisfactory results, speech signals were fed to check the performance of the SSB system as a whole under real load conditions. While testing with the signal generator, no external circuit except the analog to digital (A/D) and digital to analog (D/A) converters are required. But the voiceband signals need to be bandlimited and in certain cases even require amplification. Thus lowpass filters and variable amplifiers were also added in. -59-

implements \\y /

(Block diagram of software implementation)

Figure 7.1 : SSB modulation system

The block diagram of the system used to implement the SSB modulation is presented in Fig.7.1. The signal generator could be used either as a single frequency generator or a sweep generator. The A/D and D/A converters connected external to the PC have been described, along with the circuit diagram, in Appendix 1. To check if the output SSB signal is a single frequency sinusoid and of the right frequency, a cathode ray oscilloscope (CRO) was connected at the DAC output. Instead of a CRO, a spectrum analyzer was connected while checking the suppression levels of the unwanted sideband signals. Results of both the CRO and spectrum analyzer have been presented in the thesis. The spectrum analyzer output could even be plotted on a X-Y plotter. An effort was made to link a plotter, using a programmable controller, to the spectrum analyzer but due to compatibility problems between the two, it was not possible. Instead, analysis was done by taking photographs of the spectrum analyzer display. -60-

7.2 Weaver’s method - Implementation As shown in Fig.7.1, the basic building blocks in Weaver’s method consist of frequency modulators, digital oscillators, and lowpass filters.

7.2.1 Digital oscillator & modulator : The sine and cosine functions of the required frequency were generated using the ROM lookup table method described in Section 4.5.2. The human voiceband signal occupies the spectrum from about 300 Hz to 3300 Hz, giving a mid-band frequency fo of 1800 Hz with 1500 Hz band on each of its side. Thus from Fig.3.5, we have fL = 300Hz ; fH = 3300Hz B = fH — fL = 3000Hz

fpi + ^ f0 = —----k = 1800Hz u 2 The intermediate carrier frequency of the first pair of modulators is 1800 Hz. While executing the program, the values of sine and cosine functions are read from the lookup table. Using the 'MPY' instruction the input sample in each of the two branches are multiplied by their respectively read values from the table. The frequency of the second pair of modulators is the carrier frequency of the SSB signal to be transmitted. Practically, the carrier frequency is expected to be in the RF range. As will be seen later, the maximum sampling frequency fs that could be achieved in the experiments was approximately 25 kHz, thus restricting the maximum carrier frequency permissible to 12.5 kHz (i.e. fs/2). While carrying out the experiments, a carrier frequency of 10 kHz was chosen. Later, in Section 7.6, a method of achieving higher sampling and carrier frequencies has been looked at.

7.2.2 Digital filters : Specifications for the identical digital digital LPF’s after the first set of modulations have been summarized by Freeny et al [30] and have been briefly presented here. The baseband requirements of the channel are specified in Fig.7.2. As shown, the interchannel cross-talk attenuation is expected to be atleast 55dB while the inband gain variation allowed is ±0.5dB, with some more relaxed tolerances at the band edges. When the above baseband requirements are translated appropriately and applied to the signal format handled by the Weaver’s lowpass filters, the result are shown in Fig.7.3. From Fig.7.3b, it is clear that for the LPF, the cutoff frequency is 1500 Hz and the transition band available is 2fL (i.e. 600 Hz). To faithfully suppress the unwanted -61-

0.5 -- 0-- -0.5

-1.5 Response r 55 dB (dB) Crosstalk Attenuation

300 ■V 3.3k 3.9k Frequency (Hz)

Figure 7.2 : Baseband channel requirements

signals, LPF is required to have an attenuation of atleast 55dB at 2100 Hz. Depending on the requirements of the application, there are a number of factors to be considered while designing a digital filter.

The first decision is to select between an FIR and an IIR filter. In the present application, we have the modulation and demodulation of speech signals. Since phase information is not important for the intelligibility of speech, the choice of an IIR filter is favoured. An FIR filter would be chosen when phase information of the signals is required. But in applications where the signal phase is not necessary, as in the present case for speech signals, IIR filters are a better choice. To make the whole SSB system feasible at the desired sampling rate, it is important to meet the specifications of Fig.7.3. As compared to an FIR filter, a much lesser order IIR filter would meet the same specifications.

Wave digital filters (WDF) could also have been used for the purpose. When implemented in fixed point arithmetic WDF are reported to have similar roundoff noise but worst coefficient sensitivity as compared to the cascade and parallel forms [31]. Their roundoff noise and sensitivity improves with floating point representation. But for reasons explained in Section 5.2 floating point arithmetic is not recommended on TMS 32020. Moreover, for most designs the element values are very small and for fixed point implementation only a few of the bits could be used to represent coefficients, resulting in poor precision. Thus we may conclude that wave digital filters would prove unsuitable for implementation on the present system.

After deciding that an IIR filter is to be implemented, one has the option of choosing the filter structure. The choice is between direct, cascade and parallel form -62-

-1.5 -- 55 dB Response Crosstalk (dB) Attenuation

1.5k 2.1k Frequency (Hz)

Figure 7.3 : Lowpass filter specifications

structures described in Chapter 4. Direct form could be eliminated as its coefficient sensitivity and roundoff noise are very high. For the parallel form, very often the magnitude of some of the scaled filter coefficients exceeds unity and thus further scaling has to be applied to avoid overflow. This results in higher coefficient quantization and roundoff noise. Also the parallel form structure has higher coefficient sensitivity in the stopband [24]. Thus the cascade form structure, with second order sections, was appropriate for the application. Moreover, they are easy to implement and design, and are being widely used.

Next, form I or II cascade structure could be selected. The choice depends on the trade-off between program execution time and program memory occupancy. For the SSB system, ample program memory was available, and thus the choice was to optimize execution time. Of the two forms, form I requires lesser execution time for the same application and was thus selected. The bilinear transformation technique, explained in Section 4.3.3, was used to design the filter. For the bilinear method, an analog filter type is required on which the design is to be modelled. Frequency response of eighth order Bessel, Chebychev and Elliptical filters, with maximum passband ripple of ±0.5 dB were plotted. Elliptical filter, with the sharpest characteristics in the transition region, was chosen for the thesis.

Using the standard filter design equations [32], it was predicted that the requirements of Fig.7.3 would be satisfied by an eighth-order elliptical filter with 0.5dB passband ripple. Poles and zeros for different orders of analog elliptical filter are available in various textbooks on filter designs [32],[33]. These poles and zeros along with filter order and sampling rate were inputted to the program 'BILINEAR', listed in -63-

Appendix 3, which outputs the required digital filter coefficients for a cascade structure. In turn, these coefficients were inputted to an IEEE program 'DFILTER' which gave a theoretical magnitude and phase response of the filter under consideration. The frequency response of eighth-order digital HR filter as simulated by 'DFILTER' program is attached in Appendix 2.

Section 1 8.85 Section 2 3.52 Section 3 8.77 Section 4 1.41

Table 7.1 : Peakedness

7.2.3 Scaling : The 'SCALE' program, listed in Appendix 3, was used to find the scaling factor and the scaled numerator coefficients. The L^ scaling criterion was used, while considering a sinusoidal input. The scaling depends on the section ordering and pole zero pairing. The four second order sections were ordered so as to minimize the output noise variance (i.e. from least to most 'peaked'). The peakedness P/s as defined in Section 5.7.3 and shown in Table 7.1 were obtained from the 'SCALE' program. The ordering of the four sections was section 4 first, followed by sections 2,3 and 1 in that order. The scaled filter coefficients in Q12 format (described in Section 5.2) and in the re-arranged order were entered as data into the 'SSB1' assembly program (Appendix 4).

7.3 Synchronization

It is important that the frequencies of the crystal oscillators used at the transmitter and receiver SWDS be the same. In the thesis, it was expected that the digital oscillators in the transmitter and receiver processors generate exactly the same frequencies. The digital oscillator frequency generated through software is determined by the sampling frequency, which in turn is obtained from an internal timer. The timer is controlled by the processor clock, or to say, the crystal oscillator. Using the program 'TIMING' listed in Appendix 4, it was checked with a frequency meter that the two processors produced a square wave which were within 1 Hz of each other. Moreover, in the thesis a synchronization technique has been used which is independent of any difference in the two crystal frequencies. Here the XF and BIO pins -64-

Figure 7.4 : Synchronization technique available on each of the processors were used. The transmitter waits for a ready signal from the receiver before transmitting the signal. The XF pin of the transmitter is connected to the BIO pin of the receiver and vica versa. The BIO pin is polled by the BIOZ instruction, and if low, the branch is taken. When the receiver is ready, it pulls its XF pin low and the BIO pin at the receiver follows. The transmitter then transmits the signal. By pulling its own XF pin low, the transmitter lets the receiver know that the signal has been transmitted. In turn the BIO pin at the receiver goes low. The receiver then receives the signal and acknowledges the same by pulling its XF pin high. The transmitter would receive the acknowledgement and then carry on with the rest of the processing until it is ready to transmit again. Using this technique of synchronization the sampling frequency of the receiver is controlled by the transmitter and not its own internal timer. Since the transmitter and receiver have the same sampling frequency, their digital oscillator frequencies would be exactly the same too. From the features available on the TMS 32020 processor, the above method of synchronization proved to be the most efficient. On a different processor or a different system, some other method (e.g. sending a diminished carrier) could possibly be a better way of synchronization.

7.4 Performance

7.4.1 Digital oscillator : Before the whole SSB modulation system was implemented, the program for digital sine & cosine function generators and lowpass filter were tested separately. The output, after DAC, of the program for digital sine function (of 1.8 kHz) generator is shown in Fig.7.5.

7.4.2 Digital lowpass filter : The frequency response of the digital lowpass eighth- order elliptical filter, as recorded from the 'LPF8' program, was plotted and has been included in Appendix 2. For all the programs a sampling rate of 25 kHz was selected. -65-

Frcq = 1.8 kHz

Figure 7.5 : Sine wave generated

7.4.3 Noise variance : The theoretical noise variance for the lowpass filter with cascade structure was calculated by the 'NOISE' program listed in Appendix 3. The results for all possible orderings of the four sections were obtained and it was found that the ordering 4,3,1,2 had the least noise variance. The results prove that the 'Peakedness' gives a fair idea into the ordering of sections but still may not give the best ordering.

7.4.4 SSB system : After obtaining satisfactory results for the individual building blocks, the SSB modulation system was implemented. A listing of the program 'TXER' has been included in the Appendix 4.

7.4.4.1 Signal generator input : To check the performance, the input frequencies were swept over the whole voice band spectrum, i.e. 300 Hz to 3300 Hz. Here, outputs for two different input frequencies (800 & 2600 Hz) have been presented. Firstly, consider the 800 Hz input sinusoidal signal,

mj(t) = cosoont where con - 27tfn ; fn = 800 Hz

The output of first modulation, (modulation frequency = 1800 Hz), in both the branches A and B (Fig.3.4) has two components each. From (3.6) & (3.7), they are at 1000 Hz and 2600 Hz but with different phases in each branch. Using a lowpass filter with cutoff at 1500 Hz, the signal at 1000 Hz is passed while the 2600 Hz signal is -66-

Scale - x : 2 kHz/div y : 10 dB/div

SSB output freq = 11.0 kHz Figure 7.6 : SSB modulator output spectrum

Scale - x : 2 kHz/div y : 10 dB/div

SSB output freq = 9.2 kHz Figure 7.7 : SSB modulator output spectrum -67-

adequately attenuated. This filtered signal in each branch, is then applied to their respective second modulator with a carrier frequency of 10 kHz. The modulator outputs have two components each at 9.0 kHz & 11.0 kHz. The phases of the signals in the two branches are such that on adding or subtracting the outputs of the two branches, we get the upper or lower sideband respectively. In the present case, the two outputs were subtracted to get the LSB at 11.0 kHz. The USB output which would be at 9.0 kHz gets cancelled out on subtraction. The SSB modulated output as visualized on the spectrum analyzer is shown in Fig.7.6. From Fig.7.6, it can be seen that as expected from (3.1) to (3.16), the output is a single frequency sinusoidal signal at 11.0 kHz. The unwanted USB output at 9.0 kHz has been effectively rejected and is 50 dB below the wanted signal. The noise level is atleast 40 dB below the desired signal.

CRO Personal SSB Demodulated ‘or’ computer signal output Spectrum (SWDS) analyzer

implements /

( Block diagram of software implementation )

Figure 7.8 : SSB demodulation system

Next, instead of 800 Hz an input of 2600 Hz is applied. Using (3.1) to (3.16), we find that the output USB and LSB signals would be at 10.8 kHz and 9.2 kHz -68-

Input signal —

Recovered signal —=►

Scale - x : 1 ms/div

Freq = 800 Hz

(a) Recovered signal

Scale - x : 500 Hz/div y : 10 dB/div Recovered freq = 800 Hz (b) Demodulator output spectrum

Figure 7.9 -69-

Input signal

Recovered signal

Scale - x : 2ms/div

Freq = 2.6 kHz

(a) Recovered signal

y: 10 dB/div Recovered freq = 2.6 kHz (b) Demodulator output spectrum

Figure 7.10 -70-

respectively. On subtracting, the LSB (i.e. 9.2 kHz) component is obtained. The results have been presented in Fig 7.7. Again we observe that the output of the transmitter is as expected i.e. the unwanted sideband is almost 50 dB down and the noise level is atleast 40dB below the desired signal.

The next step was to implement the SSB demodulator. A block diagram is as shown in Fig 7.8.

The demodulator is simply implementing the modulator in the reverse order. The programs for digital oscillator and lowpass filter had been tested earlier for the modulator program and were need not tested again. The listing of the program, 'RXER', for complete SSB demodulation is attached in Appendix 4. The performance of the demodulator or the receiver was checked by inputting to it the transmitter output SSB signal. For an input of 11.0 kHz sinusoidal signal, the demodulated output should be similar signal at 800 Hz while the unwanted sideband (USB in this case) be suitably rejected.

The results are presented in Fig.7.9. Similarly, for a 9.2 kHz input, the output should be a single frequency at 2600 Hz and unwanted signal at 1000 Hz be suitably rejected. Results are as in Fig.7.10. Again the unwanted sideband has been attenuated by about 50dB and the noise level is atleast 40dB below the desired signal.

Transmitter Channel

CRO ‘or’ Channel Spectrum analyzer Personal Variable computer gain Headphones (SWDS) amplifier

Receiver

Figure 7.11 : Complete SSB modulation-demodulation system (a) Modulator output

Scale - x : 2 kHz/div y : 10 dB/div

(b) Demodulated output

Figure 7.12 : Speech signal spectrum -72-

After getting satisfactory results for the modulator and demodulator under single frequency signals from the voice band spectrum, the system to implement SSB modulation-demodulation for voice signal is constructed as in Fig.7.11.

7.4.4.2 Voiceband signal input : Initially, continuous voice signal was obtained from a microphone source. Since the voltage level of the microphone output is normally in fractions of milli-Volts, it was amplified to the Volts level using a pre-amplifier with variable gain (circuit has been included in Appendix 1). The amplified signal was then applied to an analog LPF. Later, a cassette player was made available and so the voice signal at the earphone output was applied directly to the LPF. This LPF with a cutoff at 3500Hz was required to remove the effect of aliasing which could be introduced by higher frequency components, at the time of sampling for ADC. Anti-aliasing filter selected was a sixth-order elliptical filter (Appendix 1). The ADC and DAC circuits have been described in Appendix 1. They act as a link for the PC with the outside world. The SSB analog signal at the transmitter output was then transmitted across the channel to the receiver. The channel here was a few metres of a pair of conducting wires and was assumed to be an ideal one with no distortion. At the receiver input, a bandpass filter (BPF) which passes a band of 4 kHz, centred at the channel carrier frequency could be included. Such a filter would prove useful for applications where FDM of a number of signals, over a groupband for example, is being carried out. But the BPF was not required for the present application of one voiceband signal. After demodulation, the original transmitted signal was recovered. Using a variable gain amplifier, the recovered signal was appropriately amplified and applied either to a set of headphones for hearing or else to a CRO (or spectrum analyzer) for detailed analysis. The recovered voice (or speech) as heard over the headphones was of very high quality. It was clear of audio frequency noise, was intelligible and of the right frequency. The results and performance were also demonstrated satisfactorily to the thesis supervisor and fellow research students. The modulator and demodulator output frequency spectrums are shown in Fig.7.12 (a) and (b), respectively. The unwanted sideband was suitably suppressed by more than 45dB and the noise level was also about 45dB below the wanted signal. While designing, suppressions exceeding 55dB had been predicted. The results obtained -73-

were not exactly the same as those predicted. While carrying out the noise analysis, it was simulated that the quantization and roundoff noise would be about 8-9dB. Thus a degradation of approximately lOdB in the design values obtained above, was expected. Only one problem with the overflow was encountered. To avoid overflow within the SSB modulator and demodulator, proper scaling of the filter coefficients had to be done. In addition the ADC used at the transmitter input could accept a maximum of ± 5Volts signal. Thus if the input level exceeded these limits, ADC would produce noise which in turn would be reproduced over the headphones at the output. To avoid such a situation, the input signal level was carefully manned so as not to overdrive the ADC.

7.5 Multiplexed system

In the thesis, a system having a single channel, with a carrier frequency of 10 kHz has been considered. But in most practical applications the voiceband signals are stacked into adjacent 4 kHz channels. For telephony applications, 12 such 4 kHz channels are assembled in the groupband spectrum, occupying the interval 60 to 108 kHz. This generates the need to increase the sampling rate at the transmitter and consequently reduce it at the receiver. A frequency-multiplexed SSB system, where the complicated filtering functions are performed at the low sampling rate and simpler functions at the high sampling rate required for the grouping together various channels into a frequency-multiplexed format has been considered by Freeny et al [30],[34].

7.6 Interpolation and Decimation

The process of taking a given sequence, x(n), and creating a new sequence, y(n), whose samples occur L times as fast is known as digital interpolation. Decimation refers to the inverse process of sample rate reduction by an integer factor M. Both these processes have been described in several books and papers. A brief description of the two from [7],[35],[36] has been given here. The process of interpolation, for a signal x(n), is illustrated in Fig.7.13, with an original sampling rate of fs. To increase the sampling rate of the signal x(n) by an integer factor L, L-l zero-valued samples have to be inserted between each pair of samples of x(n). This creates a signal w(n) with sampling rate fs = Lfs. As shown in Fig. 7.13b, components of the signal w(n) are periodic with period equal to the original sampling frequency fs. In order to retain only the baseband frequencies and eliminate periodic components, the signal w(n) is lowpass filtered by sblH(f)sbl, operating at the new rate fs. The resulting signal y(n) with sampling rate fs is the desired interpolated signal with spectrum given in Fig. 7.13b. -74-

r • I i Increase i x(n) ! sampling w(n) Lowpass ! y(n) 1 rate by filter 1 1 L “

fs L. 1 (a)

x(eiW,) x(n) 'r Y

f f-

w(n)

0 11 — \ L

y(n) ■' ‘V

(Tn^Nfl/ (b) Figure 7.13 : (a) Interpolation Process (b) Waveform and frequency response at various stages

The process of decimating a signal x(n) by an integer factor M is illustrated in Fig 7.14, where the original sampling rate is fs and the final rate is fs = fs/M. To prevent aliasing at the lower sampling rate fs, the original signal x(n) has to be lowpass filtered giving the signal w(n). After filtering, one of every M samples of w(n) is extracted, and the remaining M-l samples are discarded. This forms a new sequence y(n), which is the desired decimated signal. The Fourier transforms of x(n), w(n), and y(n) are depicted in Fig. 7.14b.

For both the interpolation and decimation processes, the lowpass filter is chosen to be a linear-phase filter. The choice of such a filter is based on the following reasons :

i. In interpolation, L-l of the delayed input samples are zero and thus need not be multiplied by filter coefficients. -75-

r Decrease x(n) Lowpass w(n) sampling i y(n) 1 filter rate by 1 1 1 1 M f 1 s L . L . J f./M (a)

Figure 7.14 : (a) Decimation process (b) Frequency response at various stages

ii. In decimation, M-l of the output samples are discarded and thus need not be computed for a non recursive filter.

iii. The even symmetry of h(n) for a linear phase FIR filter means a saving in multiplication of a factor of almost one-half. We have considered only single-stage technique for changing the sampling rate of a signal. However, for large changes in sampling rate, it is generally more efficient to gradually change the sampling rate over a series of stages. This results in less severe requirements on the lowpass filters at each stage. Crochiere et al [35] presented optimum design methods for multistage interpolators and decimators. Nelson et al [37] and Bellanger et al [38] have also implemented sampling rate changes using several stages but had only factors of 2 at each stage. For the present SSB application, the change in sampling rate by a factor of 2 or 3 were considered and thus did not require multiple stages. -76-

Recursive Interpolation lowpass FIR filter filter

cos C0ot Baseband input output sin co0t

Recursive Interpolation lowpass FIR filter filter

Low High sample rate sample rate

(a)

Decimation Recursive HR lowpass filter filter

.+ Baseband '+ output

Decimation Recursive FIR lowpass filter filter Low High sample rate sample rate

(b)

Figure 7.15 : Weaver’s method of SSB generation with (a) interpolation at the transmitter. (b) decimation at the receiver. -77-

If required, a change in sampling rate by a non-integer, but rational, factor L/M can also be achieved by cascading the operations of interpolation and decimation in that order. The interpolation process must precede decimation so as to retain the desired frequency band in the final output. The two lowpass filters would operate in cascade and at the same sampling rate. Thus the overall process can be more efficiently implemented by eliminating the lowpass filter with a wider bandwidth.

7.6.1 Implementing Interpolation : As mentioned earlier, for the FDM hierarchy of long distance telephony, 12 voiceband signals are stacked, using SSB modulation, into 4-kHz segments of the 60 to 108 kHz groupband. Since the highest frequency in the groupband is 108 kHz, a sampling rate of atleast twice this frequency would be required for the digital groupband signal. But as explained by Freeny et al [30], the blank space below 60 kHz can be made use of. On converting a digital signal to analog form, we get the desired analog signal as well as its images or sidebands symmetrically spaced about multiples of the sampling frequency. Thus the mirror image of what is required can be created in the region below 60 kHz and the correct signal can be selected using a bandpass filter. Theoretically, any sampling rate between 108 and 120 kHz would serve, though one near the extreme edges would require very narrow transition bands for the filter. Since the standard PCM rate for telephony systems is 8 kHz, a sampling rate of 112 kHz (an integer multiple of 8 kHz) would be chosen. After having a look at the length of the SSB modulation program and the processor execution speed, it was decided that a sampling rate of 112 kHz was not possible for the present system. It would be achievable by the next generation of digital signal processors, with reduced execution times and improved instruction sets. However, to check the performance of an interpolator & decimator and also to lay a basis for future, a system whose sampling frequency was increased from 8 kHz to 24 kHz, has been considered. Fig.7.15a depicts an efficient approach for SSB generation using interpolation. Likewise, at the receiver, a decimator which reduced the sampling rate from 24 kHz to 8 kHz was included in the SSB demodulation. This is shown in Fig. 7.15b. Assembly programs for SSB modulation with interpolation and SSB demodulation with decimation, 'INPOL' and ’DECIM' respectively, are listed in Appendix 4. The above programs performed satisfactorily in conjunction; for voice signal inputted to the transmitter was faithfully reproduced at the receiver output. -78-

7.7 Phase shifting method

After a detailed look at the filter specifications for the Frequency discrimination method, it was found that under the present sampling rates feasible it would not be possible implement such filters in software. Hence only the Phase shifting method was considered. The block diagram of an SSB modulator based on Phasing method, also known as the Hartley modulator [3], is as shown in Fig.3.3. Except for wideband 90° phase shifter, the other main components of Phasing method, i.e. the digital oscillator and product modulator have already been discussed earlier in the chapter. The underlying technique for the Phasing method was explained in Section 3.7. A wideband 90° phase shifting network could be implemented by using digital Hilbert transformer [39]. Rabiner et al [40] has presented new optimum design techniques and design data on digital Hilbert transformers.

7.7.1 Digital Hilbert transformer : The basic theory and operations of a digital Hilbert transformer have been discussed by Rabiner et al [54]. Consider a real-valued signal x(n) with Fourier transform X(d“). Let x(n) be the Hilbert transform of x(n) with all frequency components delayed by 90° . Then the complex valued analytic signal is given by

x(n) = x(n)+jx(n) ...7.1 with Fourier transform X(eiw), as

X(ej“) = 2X(ej“) 0 < CO < 7t

= 0 K < CO < 2k ... 7.2

From (7.1), the Fourier transform of x(n) is

X^™) = X(ej“)+jX(ei“) ... 7.3 and from (7.2), we have

X(e)“) = 2X(ei“) 0 < CO < 7t ... 7.4

X(ei“) + jX(ei">) = 0 K < CO < 27t ... 7.5

From these relationships, it can be shown that the frequency response of an ideal Hilbert transformer would be -79-

Hd(ei“) = _j 0 < CO < 71 = +j k < co < 2n ... 7.6 If a linear phase term is also added, then (7.6) becomes

Hd(e^) = —j e jayr 0 < co < 7t = +j e-j(co-27C)T 7C < CO < 27C ... 7.7

where x is the delay in samples. It can be shown [38], that in order to obtain a causal approximation to the ideal Hilbert transformer with no phase distortion, an FIR filter with odd symmetry would be required.

7.7.2 Implementing : Generation of a pure sideband depends on the modulator circuit tolerances. The critical parameters determining the suppression of the undesired sideband are : (i) amplitude mismatch, (ii) phase mismatch between phase-shifted and unshifted baseband channels, and (iii) phase tolerances of inphase and out of phase carrier signal components. In order to obtain 50 dB suppression of unwanted sideband, both phase quadratures (carrier and sideband) must be maintained within 0.35° and 0.6° respectively and the baseband amplitude imbalance must be less than 0.2% [39]. Using digital Hilbert transformer, such tolerances are achievable. In our present application, the sampling frequency fs of 25 kHz was selected. Hence, a digital Hilbert transformer which has a flat amplitude response and shifts all frequencies from 0 to fs by 90° would be required. We define, fL and fH as the lower and upper cutoff frequencies respectively. As explained in [40], fullband approximations, i.e. fL = 0 and fH = fs/2 are not possible. Thus we would have transition bands at the lower and upper edges and would be defined by fL and fs - fH. For optimum Hilbert transformers, it is assumed that the lower and upper transition widths are equal. Design data for such wideband Hilbert transformers is available in [40] and was used for the present designs. It has also been shown that for an odd-length filter, half the coefficients are zero valued and thus would reduce the multiplication computation time by half. The choice of filter transition width as 0.0lfs (i.e. 250 Hz), and a small ripple of 0.095, would require a Hilbert transformer of order 55. The impulse, frequency, and phase response of this filter are listed in Appendix 2. The impulse response has an odd symmetry about fs/4.

A listing of the programs for the Phasing method of SSB generation, -80-

Scale - x : 1 kHz/div y : 10 dB/div

Figure 7.16 : Recovered voice spectrum

'PHAS-TX' and 'PHAS-RX', are listed in Appendix 4. The block diagram of the whole SSB modulator remains the same as that for Weaver’s method (Fig.7.1), except that here the software is different. For the voice signal at the transmitter input, the recovered signal at the receiver output was as in Fig.7.16. The quality of the voice recovered was not satisfactory, as the noise level was high (only 25dB below the desired signal). In addition, the recovered voice spectrum was located incorrectly and was shifted in frequency by over 1kHz. As is clear from Fig.7.16, that the recovered voice occupies the frequency spectrum from 1kHz to 4.5kHz instead of 0 to 3.5kHz. Thus the results produced by Phase shifting method implemented digitally on TMS32020 were unsatisfactory. Testing the implementation of Phasing method was taken up only as an additional work. Due to the time constraints, detailed analysis of this method could not be carried out. The reasons for poor performance of this method when implemented digitally, could not be investigated and are still open for further research work. -81 -

CHAPTER 8 : CONCLUSION AND FUTURE WORK

To date, various techniques for design and implementation of SSB modulation/demodulation as a digital system have been presented. Due to its simplicity in implementation and other advantages mentioned in Chapter 3, the Weaver’s method of SSB modulation has always been considered as an alternative to traditional SSB modulation methods (see Chapter 3) in digital signal processing. This has been discussed in a number of papers [2],[4],[5],[34],[41],[44].

The aim of the present thesis was to study the practical feasibility of SSB modulation as a digital system. Using the TMS32020 DSP, it was found that the techniques for digital SSB modulation developed in theory could be implemented in practice. The promising results obtained for the Weaver’s method lay down the bases for further work in this field, where multiple-SSB channel banks could be realized in communication systems using the next generation digital signal processors.

As seen during the thesis, the maximum sampling frequency possible on the TMS32020 is restricted by the processor cycle-time and the number of instructions required for the digital processing application. For the SSB modulation by Weaver’s method, the maximum frequency that could be achieved was about 25 kHz. This limits the carrier frequency of SSB modulated signal to 12.5 kHz. In many applications a much higher sampling frequency is desired.

SSB modulation has been dominant in the telephone systems. Thus a major application of digital SSB modulation is the generation of the digital groupband signal, that is, twelve 4-kHz voice channels (multiplexed in the 60 to 108 kHz band), from the set of digital baseband signals. This function is useful because of the interface between existing analog FDM transmission systems and new digital systems.

It has been found [34] that in order to generate a groupband signal, a sampling frequency of 112 kHz is required for each of the groupband channels. Such high sampling frequencies can be achieved by the interpolation technique [30],[34]. Using interpolation in Weaver’s method on the TMS32020, the sampling frequency of the SSB signal could be doubled, while maintaining the quality of the signal reproduced. Due to the processor restraints mentioned earlier, higher interpolation factors could not be achieved.

Another scheme by which processing time could be reduced, is to use multiprocessors at the transmitter and receiver. For example, in the Weaver’s method, -82- the digital modulation and filtering in each of the two branches (see Fig.3.4) could be performed on separate digital signal processors, each with its own local memory and a shared global memory. This would reduce the processing time to half of that achievable with only one processor. The above scheme requires four processors, two each at the transmitter and receiver. Due to the non-availability of four TMS32020 DSP for the thesis, multiprocessing could not be performed and could be a part of future work in this area. Using multiple processors and global memory, the cost of the digital system increases and the choice would depend on the cost/speed tradeoff.

The third generation DSP in the TMS320 family, TMS320C30 is already in the pre-production stage. From the information available [42], the TMS320C30 has a 60- nsec cycle time which is more than three times lesser than the 200-nsec cycle time available on the present TMS32020. This means that for the SSB generation programs implemented on the TMS32020, the TMS320C30 would do the same job in one-third of the time taken by TMS32020. Using interpolation with TMS320C30, a sampling frequency of 112 kHz, as required for the groupband signals would be achievable. There is a possibility that with the improved general-purpose instruction set (e.g. single-cycle floating point multiply/accumulate) and addressing modes, the need for interpolation might not be necessary.

From the results obtained in the thesis, it was found that though the design specifications laid for unwanted signal and noise suppression were to be 55dB below the wanted signal, only 40-45db suppressions could be obtained. The lOdB deterioration in the signal was due to the noise introduced by scaling and rounding in 16-bit fixed-point arithmetic. The TMS320C30 is a floating-point DSP with 32-bit wordlength memory, ALU, and data bus. The feature of floating-point arithmetic means that to avoid overflow, it would not be necessary to scale the input signal, coefficients, or the results of arithmetic operations. An increase, from 16 to 32, in the number of bits available to represent signals and coefficients, would lead to a considerable decrease in the roundoff noise and other effects due to finite wordlengths (e.g. coefficient sensitivity). Thus high performance for real-time digital signal processing applications like SSB generation would be achievable. Also WDF implementation would then become possible.

Besides Texas Instruments, many other manufacturers have produced digital signal processing chips which are comparable, in terms of features and performance, to the TMS 32020. Looking ahead, it appears that the TMS320C30 would be the most powerful DSP available with the best features combined from all other digital signal processing chips. On comparison, the WE DSP32 and WE DSP 16 processors from -83-

AT&T [43] appears to be the next in line to the TMS320C30 in terms of speed and performance.

Though a lot of work is available in theory, very little has been carried out (or reported) on the practical implementation of digital signal processing systems, especially using the new generation digital signal processors like the TMS32020. While the present thesis is a step towards one of the new openings in digital signal processing, the areas of generating high frequency SSB signals and multiplexing a number of voice channels in the groupband are still open for further research. -84-

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[9] R.L.RABINER, N.Y.GRAHAM, and H.D.HERMS, "Linear Programming Design of IIR Digital Filter with Arbitrary Magnitude Function", IEEE Trans, on Acoustics, Speech and Signal Processing, ASSP-22, No.2, pp 117-123, Apr 1974.

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[11] A.V.OPPENHEIM and R.W.SCHAFER, Digital Signal Processing, Prentice-Hall Inc., Englewood Cliffs, NJ 1975

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[13] C.CHARALAMBOUS and M.BEST, "Optimization of Recursive Digital Filters with Finite Wordlength”, IEEE Trans, on Acoustics, Speech and Signal Processing, ASSP- 22, pp 424-431, Dec 1974.

[14] M.SUK and S.MITRA, "Computer Aided Design of Digital Filters with Finite Wordlengths", IEEE Trans. Audio and Electroacoustics, AU-20, No.5, pp 353-363, Dec 1972. -85-

[15] L.B.JACKSON, "On the Interaction of Roundoff Noise and Dynamic Range in Digital Filters", The B.S.T.J., Vol. 49, pp 159-183, May 1967.

[15 A] S.K.MITRA, K.HIRANO, and H.SAKAGUCHI, "A Simple Method of Computing the Input Quantization and Multiplication Roundoff errors in Digital Filters", IEEE Trans, on Acoustics, Speech and Signal Processing, ASSP-22, No.5, pp 326-329, Oct 1974.

[16] P.M.EBERT, J.E.MAZO, and M.G.TAYLOR, "Overflow Oscillations in Digital Filters", The B.S.T.J., pp 2999-3021, Nov 1969.

[17] L.B.JACKSON, "Roundoff Noise Analysis for Fixed Point Digital Filters realized in Cascade or Parallel form", IEEE Trans. Audio and Electroacoustics, AU-18, No.2, pp 107-122, June 1970.

[18] J.F.KAISER, "Some Practical Considerations in the Realization of Linear Digital Filters", Proc. Third Annual Allerton Conf. on Circuit & System Theory, Monticello, Illinois, pp 621-33, Oct 1965.

[19] W.S.LEE, "Optimization of Digital Filters for Low Roundoff Noise ", IEEE Trans, on Circuits and Systems, CAS-21, No.3, pp 424-431, May 1974.

[20] L.B.JACKSON, "An Analysis of Limit Cycles due to Multiplication Rounding in Recursive Digital Filters", Proc. Seventh Allerton Conf. on Circuits & Systems Theory, pp 69-78, 1969.

[21] C.Y.KAO, "An Exploratory TDM-FDM SSB Generator", National Electronics Conference Proc., Vol. 27, pp 47-50, 1972.

[22] A.FETTWEIS, "On the connection between Multiplier Wordlength limitations and Roundoff Noise in Digital Filters”, IEEE Trans, on Circuit Theory, Vol. 19, No.5, pp 486-491, Sep 1972.

[23] A.FETTWEIS, "Roundoff Noise and Attenuation Sensitivity in Digital Filters with Fixed Point Arithmetic", IEEE Trans, on Circuit Theory, Vol. 20, pp 174-5, Mar 1973.

[24] F.BONZANIGO, "Comments on Roundoff Noise and Attenuation Sensitivity in Digital Filters with Fixed-Point Arithmetic", IEEE Trans, on Circuit Theory, Vol. 21, pp 809-810, Nov 1974.

[25] M.BHATTACHARYA, R.C.AGGARWAL, and S.C.DUTTA ROY, "On realization of Lowpass and Highpass Recursive Filter with Low Sensitivity and Low Roundoff Noise", IEEE Trans, on Circuits and Systems, CAS-33, No.4, pp 425-428, Apr 1986.

[26] S.NISHIMURA, K.HIRANO, and R.PAL, "A New class of very Low Sensitivity and Low Roundoff Noise Recursive Digital Filter Structures", IEEE Trans, on Circuits and Systems, CAS-28, pp 1152-1158, Dec 1981. -86-

[27] L.BHUYAN and B.N.CHATTERJI, "Very Low Sensitivity Recursive Digital Filter Structures", Electron. Lett., Vol 17, pp 348-350, May 1981.

[28] J.I.ACHA and J.PAYAN, "Low-Noise Structures for Narrow-Band Recursive Digital Filters without Overflow Oscillations", IEEE Trans, on Circuits and Systems, CAS- 34, No.l, pp 96-99, Jan 1987.

[29] TMS32020 User’s Guide, Texas Instruments Incorporated, 1986.

[30] S.L.FREENY, R.B.KIEBURTZ, K.V.MINA, and S.K.TEWKSBURY, "Systems Analysis of a TDM-FDM Translator/Digital A-Type Channel Bank", IEEE Trans, on Comm. Tech., Vol. COM-19, No.6, Dec 1971.

[31] A.FETTWEIS, "Pseudopassivity, Sensitivity, and Stability of Wave Digital Filters", IEEE Trans, on Circuit Theory, CT-19, No.6, pp 668-673, Nov 1972.

[32] L.C.LUDEMAN, Fundamentals of Digital Signal Processing, Harper and Row, Publishers, Inc., 1985.

[33] F.J.TAYLOR, Digital Filter Design Handbook, Marcel Dekker, Inc. NY 1983.

[34] S.L.FREENY, "TDM/FDM Translation as an Application of Digital Signal Processing", IEEE Communications Magazine, pp 5-15, Jan 1980.

[35] R.E.CROCHIERE and L.R.RABINER, "Optimum FIR Digital Filter Implementations for Decimation, Interpolation, and Narrow-band Filtering", IEEE Trans, on Acoustics, Speech and Signal Processing, ASSP-23, No.5, pp 444-456, Oct 1975.

[36] R.W.SCHAFER and L.R.RABINER, "A Digital Signal Processing Approach to Interpolation", Proc. of the IEEE, Vol. 61, No.6, pp 692-702, June 1973.

[37] G.A.NELSON, L.L.PFEIFER, and R.C.WOOD, "High-speed Octave Band Digital Filtering”, IEEE Trans. Audio and Electroacoustics, AU-20, pp 58-65, Mar 1972.

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[39] S.UDALOV, "Independent Sideband Modulation!Demodulation using Digitally Implemented Hilbert Transforms", IEEE 1982 National Telesystems Conference NTC ’82, pp D3.5.1-D3.5.5.

[40] L.R.RABINER and R.W.SCHAFER, "On the Behaviour of Minimax FIR Digital Hilbert Transformers”, The B.S.T.J., Vol. 53, No.2, pp 363-389, Feb 1974.

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[42] Texas Instruments TMS320C30 DSP, Preview Bulletin, 1987.

[43] J.R.BODDIE, R.N.GADENZ, R.N.KERSHAW, W.P.HAYS, and J.TOW, "The DSP32 Digital Signal Processor and its Application Development Tools", AT&T Technical Journal, Vol. 65, Issue 5, pp 89-104, Sep/Oct 1986.

[44] E. A. AKCHURIN, "Digital Demodulation of Single Sideband Signals", Telecommunications and Radio Engineering, Vol. 39, No.7, pp 25-30, July 1984. -88-

BIBLIOGRAPHY

C. M.RADER and B.GOLD, "Effects of Parameter Quantization on the Poles of a Digital Filter", Proc. of the IEE, Vol. 55, pp 688-9, May 1967.

M.H.ACKROYD, Digital Filters, Butterworth & Co. (Pub.) Ltd. 1973.

D. CHILDERS and A.DURLING, Digital Filtering and Signal Processing, West Publishing Company, USA 1975.

A.V.OPPENHEIM, Applications of Digital Signal Processing, Prentice-Hall Inc., Englewood Cliffs, NJ 1978.

S.HAYKIN, Communication Systems, John Wiley & Sons Inc. 1978.

H.G.MARTINEZ and T.W.PARKS, "A Class of Infinite-Duration Impulse Response Digital Filters for Sampling Rate Reduction", IEEE Trans, on Acoustics, Speech and Signal Processing, ASSP-27, No.2, Apr 1979.

J. K.AGGARWAL (edited by), Digital Signal Processing, Western Perodicals Company, California 1979.

K. S.SHANMUGAN, Digital and Analog Communication Systems, John Wiley & Sons Inc. 1979.

K. WAKAB AY ASHI, T.AOYAMA, K.MURANO, and F.AMANO, "TDM-FDM Transmultiplexer using a Digital Signal Processor", IEEE Trans, on Communications, Vol. COM-30, No.7, pp 1552-1559, July 1982.

Y.HAGIWARA, Y.KITA, T.MIYAMOTO, Y.TOBA, H.HARA, and T.AKAZAWA "A Single Chip Digital Signal Processor and its Application to Real-Time Speech Analysis", IEEE Trans, on Acoustics, Speech and Signal Processing, ASSP-31, No.l, pp 339-346, Feb 1983.

P.STRZELECKI, "Digital Filtering", Systems International, Vol. 11 (11), pp 116-117, Nov 1983.

S.MAGAR, E.CAUDEL, D.ESSIG, and C.ERSKINE "Digital Signal Processor Borrows from Microprocessor to step up Performance”, Electronic Design, pp 175-184, Feb 21, 1985. -89-

5. MAGAR, S.J.ROBERTSON, and W.GASS, "Interface Arrangement suits Digital Signal Processor to Multiprocessing", Electronic Design, pp 189-198, Mar 7, 1985.

C. ERSKINE and S.MAGAR, "Chip’s Hardware, Software Speeds up Processing in Laboratory Instrumentation”, Electronic Design, pp 215-220, Apr 4, 1985.

A.M.LUGOWSKI, "A Phase Method Generation of Square-law SSB Signals", IEEE Trans, on Communications, Vol. COM-34, No.7, pp 711-713, July 1986.

"The Texas Instruments TMS320C25 Digital Signal Microcomputer”, IEEE MICRO, Vol. 6, No.6, pp 24-25, Dec 1986.

D. R.CAMPBELL and S.R.McGEOCH, "The TMS32010 Digital Signal Processor - An Educational Viewpoint", Int. J. Elect. Enging. Educ., Vol. 23, pp 21-31, 1986.

R.A.ROBERTS and C.T.MULLIS, Digital Signal Processing, Addision-Wesley Publishing Company Inc. 1987. -90-

APPENDIX 1

A/D and D/A converter

The analog signal is fed alternately to the two sample-and-hold (S/H) chips U1 and U2. The two S/H’s operate in a way that when one is sampling, the other is in the hold state and vica versa. The maximum amplitude input to U1 and U2 is ± 5V. An A/D converted sample can be read into the processor, through the parallel port, by initiating the 'IN' instruction in software. It also triggers an A/D conversion of a new analog sample. Using U7 and the R/W line, the A/D converter chip can be selected. The switch U3 selects the S/H chip in the hold state and the analog signal held is fed to the A/D converter through amplifier U4. When the A/D conversion is completed, the BUSY line of U6 goes low. In turn, U8 generates a pulse which changes the state of lines Ch and Qx of U5. As a result, the S/H chip which was in the hold state changes to the sample state and vica versa for the other S/H. The digital output of an A/D converter is in Offset binary and has to be converted to 2’s compliment form for TMS32020. The clock available from the TMS32020 is 20 MHz and has to be brought down to 10 MHz using U5, as required by the A/D converter. For digital to analog conversion, the 12-bit 2’s compliment number is first converted to Offset binary form and fed to the D/A converter (U12) through the latches U10 and Ull. The analog signal is then lowpass filtered (cutoff 150 kHz) to remove spurious high frequency variations in the converted signal. 91

o -At- convertei

D/A

and

A/D

<+- O- 92

E? 2? V> £ !<> e*

—w—w— -93-

APPENDIX 2 filte:

lowpass

digital

of

response

Frequency lo* | |HCr.3 | | - 94 -

: Frequency response 103 I IHCnJ | | 95- o < 2 4-1

oo > oo o t-H aS C <5 — 1

^ i h

- je 00 C3 E Cu 'req fs = 25 kHz £ cr o hCn3 - 97 - -98-

APPENDIX 3

” BILINEAR "

* TO COMPUTE COEFF’S OF A DIGITAL FILTER * GIVEN THE ZEROS OR COEFF’S OF ANALOG FILTER ★ Input to the program 1. FILTER ORDER (N) * CUT OFF FREQ.(FC) * SAMPLING FREQ. (FS) * 2. Kn (XKN) * 3. COEFF= 1 or ZEROS= 2 ★ 4. COEFF PARTS Bl,B2 * or REAL & IMAG. parts

DIMENSION XB1(20),XB2(20),B1(20),B2 (20) WRITE(6, *)'FILTER ORDER(< 20), CUTOFF FREQ, SAMPLING FREQ ?' READ (5, *) N, FC, FS PI=3.141592654 OMl=TAN(FC*PI/FS) NHF=N/2 WRITE(6,*) 'Kn ?' READ (5, *) XKN 10 WRITE(6,*) 'ENTER COEFF=l or ZEROS=2 ?' READ(5,*)IOPTN IF(IOPTN.EQ.l) GO TO 20 IF(IOPTN.NE.2) GO TO 10 20 DO 30 1=1,NHF WRITE(6,*) 'ENTER COEFFS or ZEROS FOR SECTION=',I READ(5,*)XB1(I),XB2(I) 30 CONTINUE DO 70 J=1,NHF IF(IOPTN.EQ.l) GO TO 40 IF(IOPTN.EQ.2) GO TO 50 GO TO 10 40 YB1=XB1(J) YB2=XB2(J) GO TO 60 50 YB1=—XB1(J) *2 YB2=(XB1(J)**2)+(XB2(J)**2) * Denormalize in the S-plane 60 YBl=YBl*OMl YB2=Z2B*(0M1**2) XKN=XKN*(OMl**2) * TRANSFER FROM S-plane to Z-plane TEMP=1+YB1+YB2 -99-

YBl=(-2+(2*YB2))/TEMP YB2= (1-YB1+Z2B)/TEMP XKN=XKN/TEMP * Get values in Q15 format B1(J)=-YBl*32768 B2(J)=-YB2*32768 WRITE (6,*)'SECTION = ',J WRITE(6,*) 'Bl= ’,Bl(J),’B2= ',B2(J) 7 0 CONTINUE XNHF=NHF XKN=XKN**(1.0/XNHF) A0=XKN*32768 A2=A0 Al=A0*2 WRITE (6, 80) AO, A1, A2 80 FORMAT ('A0= ',F8.1,' Al= ',F8.1,' A2= ',F8.1) END -100 -

" NOISE "

C PROGRAM ROUNDOFF C ROUND OFF NOISE ANALYSIS C THE PROGRAM CALCULATES THE ROUNDOFF NOISE FOR C CASCADE AND PARALLEL FORM STRUCTURES DIMENSION IH(2,2) ,U(5) ,V(5) ,W(5) ,F(5) ,G(5) ,XM(5) ,XN(5) DIMENSION XK(5),XS(5),XO(5),D(5),E(5),IT(5),R(5,5) COMMON /Fl/F/Gl/G/P1/PI/XRl/XR/Ul/U/Vl/V/Wl/W/Hl/IH COMMON /II3/I3/GSFACT/SFACT/D1/D/E1/E/R1/R/NN1/N IH (If 1) =1 IH(1,2)=3 IH(2,1)=3 IH(2,2)—2 SFACT=1 PI=3.141592654 WRITE(6,*) 'ROUNDOFF NOISE ANALYSIS' WRITE(6,*) 'NO. OF BITS= ?' READ( 5, *) BO WRITE(6,*) 'ROUNDOFF AFTER: MULT.= 1, ADDITION= 2 ?' READ(5, *) IROUND WRITE(6, *) '1D=1,1P=2,2D=3 ?' READ(5,*) IFORM GO TO (30,150,30),IFORM C 2ND ORDER SECTION: (U*Z~2+V*Z+W)/(Z~2+F*Z+G) 30 GOTO (200,210,220),IFORM 40 WRITE(6,*) 'NO. OF SECTIONS= ?' READ(5,*) N N0=N IF (IFORM .NE. 1) GO TO 50 WRITE(6,*) 'INPUT SCALE FACT= ?' READ(5,*) SFACT 50 B=2**(B0-1) DO 60 1=1,N WRITE(6,*) 'U',I,' V',I,' W ?' READ(5,*) U(N-I+2),V(N-I+2),W(N-I+2) U(N-I+2)=AINT(U(N-I+2)*B+0.5)/B V(N-I+2)=AINT(V(N-I+2)*B+0.5)/B W(N-I+2)=AINT(W(N-I+2)*B+0.5)/B WRITE(6,*) 'F',I,' G',I,' ?' READ(5,*) F(N-I+2),G(N-I+2) F(N-I+2)=AINT(F(N-I+2)*B+0.5)/B G(N-I+2)=AINT(G(N-I+2)*B+0.5)/B WRITE (6,*) WRITE(6,*) U(N—1+2),'*Z**2+',V(N-I+2),'*Z+',W(N-I+2) WRITE (6,*) '------' WRITE(6,*) ' Z**2+',F(N-I+2),'*Z +',G(N-I+2) WRITE(6,*) -101 -

XM (N-I+2) =U (N-I+2) XN (N-I+2) =V (N-I+2) XO(N-I+2)=W(N-I+2) 60 CONTINUE WRITE(6, *) 'INPUTSCALE FACT=' , SFACT WRITE(6,*) 'ROUNDING AFTER' GO TO (70,80),IROUND 70 WRITE(6,*)'MULTIPLICATION' GO TO 90 80 WRITE(6,*)'DOUBLE PRECISION SUMMATION' 90 Q=0 N=N0 GO TO (240,270),IROUND 100 13=0 110 CALL SI WRITE(6,*) ' QUANTIZATION NOISE=',XR*(SFACT**2) R1=XR 13=1 DO 130 12=1,NO IF (IFORM.NE.3) GO TO 120 U(N+l)=1 V (N+l)=0 W (N+l)=0 120 CALL SI N=N—1 Q=Q+XR*XK(NO-12+2) 130 CONTINUE IF (IFORM.EQ.3) GO TO 140 Q=Q+1 140 WRITE(6,*)'ROUNDOFF NOISE VARIANCE = ',10*ALOG(Q),'DB' WRITE(6,*)'TOTAL NOISE =',10*ALOG(Q+Rl*(SFACT**2)),'DB' GO TO 320 Q=Q+3 GO TO 140 150 WRITE(6,*) 'IP PARALLEL FORM' WRITE (6,*) 'NO. OF 2ND ORDER SECTIONS ?' READ(5,*) N WRITE(6,*) 'A= ?' READ(5,*) A XS(1)=A B=2**(B0-1) A=AINT(A*B+0.5) /B DO 160 1=2,N+l WRITE (6, *) 'D(',I,')','E (',I,') ?' READ(5,*) D (I),E (I) D(I)=AINT(D(I)*B+0.5)/B E(I)=AINT(E(I)*B+0.5)/B WRITE (6, *) ' F (' ,1, ') ' ,'G(',I, ') ?' -102-

READ(5,*) F(I),G(I) F(I)=AINT(F(I)*B+0.5)/B G(I)=AINT(G(I)*B+0.5)/B WRITE (6, *) XS (I) , '* (' ,D (I) , '*Z + ',E(I) WRITE(6, *) '------' WRITE (6, *) ' (Z~2 + ' , F (I) , ' *Z +',G(I),')' 160 CONTINUE GO TO (161,163),IROUND 161 DO 162 1=2,N+l XK(I)=3 162 CONTINUE XK(1)=1 GO TO 165 163 DO 164 1=1,N+l XK(I)=1 164 CONTINUE 165 IT(1)=1 DO 170 J=2,N+l IT (J) =2 170 CONTINUE XR=0 Rl=0 WRITE (6, *) A DO 180 1=2,N+l WRITE(6,*)' + (',D(I) ,'*Z+',E(I), ')/(Z**2+',F (I), '*Z+',G(I),') ' 180 CONTINUE DO 190 1=1,N+l J=I XR=XR+ (XS (I) **2) *R(I, J) R1=R1+R (I, J) *XK (I) 190 CONTINUE WRITE(6,*) 'INPUT QUANTISATION NOISE=',XR IF (IROUND.EQ.l) GO TO 230 WRITE(6,*) 'ROUNDOFF NOISE VAR.= ',10*ALOG(Rl+1),'DB' WRITE(6,*) 'TOTAL NOISE=',10*ALOG(XR+Rl+1),'DB' GO TO 320 200 WRITE(6,*) 'ID CASCADE FORM' 210 GO TO 40 220 WRITE(6,*) '2D CASCADE FORM' GO TO 40 230 WRITE(6,*) 'ROUNDOFF NOISE VAR.= ',10*ALOG(Rl+N+1),'DB' WRITE(6,*) 'TOTAL NOISE= ',10*ALOG(Rl+XR+N+1),'DB' WRITE(6,*) GO TO 320 240 IF (IFORM.EQ.3) GO TO 255 XK(N+l)=3 DO 250 1=2,N XK(N-I+2)=5 250 CONTINUE GO TO 100 -103-

255 DO 260 1=1,N XK(N—1+2)=5 260 CONTINUE GO TO 100 270 DO 280 1=1,N XK(N—1+2)=1 280 CONTINUE GO TO 100 DO 310 1=1,NO U (N0-I+2) =XM (N0-I+2) V (NO-I+2) =XN (NO-I+2) W(NO-I+2)=XO(NO-I+2) 310 CONTINUE GO TO 90 320 NOT=l STOP END

SUBROUTINE SI DIMENSION D(5) ,E(5) ,F(5) ,G(5) ,IH(2,2) ,R(5,5) ,IT(5) DIMENSION U (5) ,V(5) ,W(5) , Y(5) ,Z (5) COMMON /Fl/F/Gl/G/P1/PI/XRl/XR/Ul/U/Vl/V/Wl/W/Hl/IH COMMON /NN1/N/II3/I3/GSFACT/SFACT/D1/D/E1/E/R1/R DO 510 J=2,N+l Z (J) =—F (J) /2.0 Y (J) = (G (J) - (F (J) *F (J) ) / 4.0) **2 510 CONTINUE DO 740 J=2,N+l Tl=l T2=0 DO 730 1=2,N+l IF (I.NE.J) GO TO 520 XV=1 X=0 GO TO 530 520 XV=Z(J)**2-Y(J)**2+F(I)*Z(J)+G(I) XX=Y(J)*(2*Z(J)+F(I)) 530 XU=U(I) * (Z (J) **2-Y(J) **2) +V (I) *Z (J)+W(I) XW=Y(J) * (2*U (I) *Z (J)+V(I) ) Tl=Tl*((XU**2+XW**2)/(XV**2+XX**2))**2 IF (XU.NE.0) GO TO 575 IF (XW) 540,550,560 540 TXW=—1 GO TO 570 550 TXW=0 GO TO 570 560 TXW=1 570 XXO=(PI/2.0)*TXW GO TO 620 - 104-

575 IF(XU) 580,590,600 580 TXU=—1 GO TO 610 590 TXU=0 GO TO 610 600 TXU=1 610 XXO=ATAN(XW/XU)+(TXU—1)*PI/2.0 620 IF (XV.NE.0) GO TO 670 IF(XX) 630,640,650 630 TXX=—1 GO TO 660 640 TXX=0 GO TO 660 650 TXX=1 660 T=(PI/2.0)*TXX GO TO 720 670 IF(XV) 680,690,700 680 TXV=-1 GO TO 710 690 TXV=0 GO TO 710 700 TXV=1 710 T=ATAN(XX/XV)+(TXV—1.0)*Pl/2.0 720 T2=T2+XXO+T 730 CONTINUE D (J)=(T1*SIN(T2) ) /Y (J) E(J)=Tl*COS(T2)-D(J)*Z(J) 740 CONTINUE IF (I3.EQ.1) GO TO 760 WRITE(6,*) 'PARTIAL FRACTION EXPANSION' DO 750 J=2,N+l WRITE(6,*) '(',D(J)*SFACT,'*Z+',E(J)*SFACT,')' WRITE(6,*) '------WRITE(6,*) '(Z~2 + ',F(J),'*Z +',G(J),')' WRITE(6, *) 750 CONTINUE 760 A=1 DO 770 1=2,N+l A=A*U(I) 770 CONTINUE XR=0 K=N+1 IT(1)=1 DO 780 J=2,N+l IT (J) =2 780 CONTINUE DO 810 J=1,K I=J IX=IH(IT(I),IT(J)) - 105 -

IF (IX.NE.l) GO TO 790 R(I, J)=A**2 GO TO 800 790 IF (IX.NE.2) GO TO 800 XL= (D (I) *D (J) +E (I) *E (J) )* (1.0-G(I)*G(J) ) XL=XL—(E(I)*D(J)-D(I)*E(J)*G(I))*F(J) XL=XL- (D (I) *E (J) -E (I) *D (J) *G (J) ) *F (I) P=(1-G(I)*G(J))**2+G(J)*F(J)**2+G(J)*F(I)**2 P=P-(1+G(I)*G(J)) *F(I)*F(J) R(I, J)=XL/P 800 XR=XR+R(I,J) 810 CONTINUE DO 860 1=1,K-l DO 860 J=I+1,K IX=IH (IT (I) ,IT(J) ) IF (IX.NE.l) GO TO 820 R(I, J)=A**2 GO TO 850 820 IF (IX.NE.2) GO TO 830 XL= (D (I) *D (J) +E (I) *E (J) ) * (1-G (I) *G (J) ) XL=XL—(E(I)*D(J)-D(I)*E(J)*G(I))*F(J) XL=XL-(D(I)*E(J)-E(I)*D(J)*G(J))*F(I) P=(1.0-G(I)*G(J))**2+G(J)*(F(J))**2+G(J)*(F(I))**2 P=P- (1+G (I) *G (J) ) *F (I) *F (J) R(I, J)=XL/P GO TO 850 830 IF(IX.EQ.3) GO TO 840 840 R(I,J)=0 850 XR=XR+2*R(I,J) 860 CONTINUE RETURN END -106 -

"SCALE "

C THIS PROGRAM CALCULATES THE ‘PEAKEDNESS’ AND C SCALING FACTORS FOR DIGITAL FILTERS C HAVING CASCADE OR PARALLEL STRUCTURE

DIMENSION A(20) ,B (20) ,C(20) ,D (20) ,E (20) ,F (20) DIMENSION KO(20), P(20), Q (2 0) PI=3.14159 W=5.00000E-03 IX=100 WRITE(6,*) 'NO. OF BITS =?' READ(5, *) NO XP=2.0**(N0-1) WRITE(6, *) 'P=2**(NO. OF BITS - 1) = ',XP WRITE(6, *) 'STRUCTURE (CASCADE,PARELLEL)' WRITE(6,*) '1D=1,2D=2,1P=3 ?' READ(5,*) 10 WRITE(6,*) 'LP SCALING CRITERION(L.INF=1,L2=2) ?' READ(5,*) L WRITE(6,*) 'NO. OF SECTIONS ?' READ(5,*) N WRITE(6,*)'ARE NUM. COEFFS. SAME FOR EACH SECTION:Y=1,N=2?' READ(5,*) ISAME ICNT1=0 IF (IO.EQ.3) GO TO 140 DO 30 1=1,N WRITE(6,*) WRITE(6,*) ' C (',I,')*Z**2 + D (',I,' *Z + E(',I,')' WRITE (6,*) '------' WRITE(6,*) ' Z**2 + A(',I,')*Z + B(',I,')' WRITE(6,*) WRITE(6,*) 'A(',I,') B(',I,') ?' READ (5, *) A (I) , B (I) A (I) =AINT (A (I) *XP+0.5) /XP B (I) =AINT (B (I) *XP+0.5) /XP ICNT1=ICNT1+1 IF (ICNT1.NE.1) GO TO 20 10 WRI TE (6, *) 'C(',I,') D (' , I, ' ) E (' , I, ' ) ?' READ (5, *) C(I),D(I),E(I) WRITE (6,*) 'A(' ,1, ')=' ,A(I) ,'B(',I, ')=' ,B(I) GO TO 30 20 IF (ISAME.NE.l) GO TO 10 C(I)=C(1) D(I)=D(1) E (I) =E (1) 30 CONTINUE WRITE(6,*) 'IF PEAKEDNESS RESULTS REQD. ENTER 1' - 107 -

READ(5,*) M IF (M.NE.l) GO TO 65 WRITE(6, *) 'PEAKEDNESS' DO 60 K=1,N DO 50 J=0,IX XL0=0.0 V=0.0 XO=l.0 XJ=J X=2.0*PI*XJ*W XA=C(K)*COS(2*X) + D(K)*COS(X) + E(K) XB=C(K) *SIN(2*X) + D(K)*SIN(X) XC=COS(2*X) + A(K)*COS(X) + B(K) XD=SIN(2*X) + A(K)*SIN(X) XO=((XA*XA+XB*XB)/(XC*XC+XD*XD)) **2 IF(XO.LT.XLO) GO TO 40 XL0=0.0 40 V=V+XO*XO 5 0 CONTINUE XL2=(V*W/0.5)**2.0 P(K)=XL0/XL2 WRITE (6, * ) 'P (' ,K, ' )=' ,P (K) 60 CONTINUE 65 WRITE(6,*) 'ORDER OF SECTIONS (from JACKSONS RULE)' DO 70 K=1,N WRITE (6, *) 'KO(' ,K, ' )=?' READ(5,*) KO(K) 70 CONTINUE

WRITE (6, *) WRITE(6,*)'SCALING FACTORS, F(K)' WRITE(6,*)'SCALING FACTORS ARE INCORPORATED INTO' WRITE(6,*) 'NUMERATOR COEFFICIENTS, HENCE SCALED NUM. ' WRITE(6,*)'COEFFS. ARE PRINTED OUT' DO 71 J=0,IX Q(J)=1.0 71 CONTINUE DO 130 K=1, N Q0=0.0 Q1=0.0 Q2=0.0 DO 90 J=1,IX XJ=J X=2.0*PI*XJ*W IF(IO.EQ.2) GO TO 76 IF(K.EQ.l) GO TO 74 XA=C(KO(K—1))*COS(2.0*X)+D(KO(K-l))*COS(X)+E(KO (K-l)) XB=C(KO(K-l))*SIN(2.0*X)+D(KO(K-l))*SIN(X) 72 XC=COS(2.0*X)+A(KO(K))*COS(X)+B(KO(K)) - 108 -

XD=SIN (2.0*X) +A (KO (K) ) *SIN (X) Z= ( (XA*XA+XB*XB) / (XC*XC+XD*XD) ) **2 IF(K.EQ.l) GO TO 78 Z=Z*F(KO(K-l)) GO TO 78 7 4 XC=COS(2.0*X)+A (KO(1))*COS(X)+B(KO(1)) XD=SIN(2.0*X) + A(KO(l) ) *SIN(X) Z=1.0/((XC*XC+XD*XD)**2) GO TO 78 7 6 XA=C (KO (K) ) *COS (2.0*X) +D (KO (K) ) *COS (X) +E (KO (K) ) XB=C (KO (K) ) *SIN (2.0*X) +D (KO (K) ) *SIN (X) GO TO 72 78 Q(J)=Q(J)*Z IF(Q(J).LT.QO) GO TO 80 Q0=Q(J) 80 Q1=Q1+Q(J)*Q(J) 90 CONTINUE F(KO(K))=1.0/Q0 Q2=(Ql*W/0.5)**2.0 IF (L.EQ.l) GO TO 100 F(KO(K))=1.0/Q2 100 IF(IO.EQ.2) GO TO 120 WRITE(6,*) 'SCALING FACTOR #' , K WRITE (6, *) 'F (' ,K, ' )=' ,F(KO(K) ) WRITE(6,*) IF(K.EQ.l) GO TO 130 C (KO (K—1) ) =C (KO (K—1) ) *F (KO (K) ) D(KO(K—1))=D(KO(K—1))*F(KO(K)) E(KO(K—1))=E(KO(K—1))*F(KO(K)) WRITE(6,*)'SCALED NUMERATOR COEFFICIENTS' WRITE(6,*)'C(',KO(K—1)C(KO(K-l)) WRITE(6,*)'D(',KO(K—1),')=',D(KO(K-l)) WRITE(6,*)'E(',KO(K—1),')=',E(KO(K-l)) GO TO 130 120 C(KO(K))=C(KO(K))*F(KO(K)) D (KO (K) ) =D (KO (K) ) *F (KO (K) ) E (KO (K) ) =E (KO (K) ) *F (KO (K) ) WRITE(6,*)'SECTION NO. #' , K WRITE (6,*) 'F(' ,KO(K) , ' ) =' ,F(KO(K) ) WRITE(6,*)'SCALED NUMERATOR COEFFICIENTS' WRITE (6, *) 'C(' ,KO(K) , ' )=' , C (KO (K) ) WRITE (6,*) ' D (' , KO (K) , ')=' ,D (KO (K) ) WRITE (6, *) ' E (' , KO (K) E (KO (K) ) 130 CONTINUE IF(IO.EQ.l) GO TO 200 GO TO 240

C PARALLEL FORM 140 WRITE (6,*)' C(1)*Z + D(l) WRITE (6, *) 'CO +------+...... ' WRITE(6,*)' Z*Z + A(1)*Z B(l)' - 109 -

DO 150 K=1,N WRITE (6,*)'A(',K, ') ,B(',K,') ?' READ (5,*) A (K) , B (K) A (K) =AINT (A (K) *XP+0.5) /XP B (K) =AINT (B (K) *XP+0.5) /XP WRITE (6,*) 'C (' ,K, ' ) ,D(',K,') ?' READ (5,*) C (K) , D (K) WRITE(6,*)'ROUNDED DENOM. COEFF S.' WRITE(6,*)'A(',K, ')=',A(K),'B(',K, ')=',B(K) 150 CONTINUE WRITE(6,*)'SCALING FACTORS,F(K)' WRI TE (6, *) ' C(1)*Z + D (1) ' WRITE (6, *) ' A + F (1) * ------+ . WRITE(6,*) ' Z*Z + A(1)*Z + B(l)' DO 190 K=1,N Q0=0.0 Q1=0.0 Q2=0.0 DO 170 J=1,IX XJ=J X=2.0*PI*XJ*W XC=COS(2.0*X)+A(K)*COS(X)+B(K) XD=SIN (2.0*X) +A (K) *SIN (X) QA=(1.0/(XC**2+XD**2.0))**2.0 IF(QA.LT.Q0) GO TO 160 Q0=QA 160 Q1=Q1+QA*QA 170 CONTINUE F(K)=l.0/Q0 Q2= (Q1*W/0.5) **2.0 IF(L.EQ.l) GO TO 180 F (K)=l. 0/Q2 180 C(K)=C(K) /F (K) D (K) =D (K) /F (K) WRITE(6,*) WRITE (6,*) ' SCALE (' ,K, ')=' ,F(K) WRITE (6,*) 'C(' ,K, ')=' ,C(K) , 'D(' ,K, ' )=' , D (K) 190 CONTINUE GO TO 240 200 Q0=0.0 Q1=0.0 Q2=0.0 DO 220 J=0,IX XJ=J X=2.0*PI*XJ*W XA=C(KO(N))*COS(2.0*X)+D(KO(N))*COS(X)+E(KO(N)) XB=C(KO(N))*SIN(2.0*X)+D(KO(N))*SIN(X) Z=(XA*XA+XB*XB)**2 Q(J)=Q(J)*Z*F (KO(N)) IF(Q(J).LT.Q0) GO TO 210 - 110 -

Q0=Q(J) 210 Q1=Q1+Q(J)*Q(J) 220 CONTINUE F(KO(N))=1.0/Q0 IF(L.EQ.l) GO TO 230 Q2=Q1*W/0.5 F(KO(N) ) = (1.0/Q2) **2 IF(L.EQ.O) GO TO 230 F (KO (N) ) = (F (KO (N) ) ) **2 230 WRITE (6, *)'SCALING FACTOR #',N+1 WRITE (6, *) 'F(' , N+l, ')=' , F (KO (N) ) WRITE(6,*)'SCALED NUMERATOR COEFFS.' C (KO (N) ) =C (KO (N) ) *F (KO (N) ) D (KO (N) ) =D (KO (N) ) *F (KO (N) ) E (KO (N) ) =E (KO (N) ) *F (KO (N) ) WRITE (6, *) ' C (' , KO (N) , ' ) =' , C (KO (N) ) WRITE (6, *) 'D (' , KO(N) , ' ) =' ,D(KO (N) ) WRITE(6,*)'E(',KO(N)E(KO(N)) 240 STOP END - Ill -

APPENDIX 4

" C-E.ASM "

* LOCATIONS FOR LOWPASS 8th ORDER HR FILTER TAP COEFFICIENTS * CASCADE STRUCTURE

C1B1 EQU C1B2+1 CA2 EQU C1B1+1 CA1 EQU CA2+1 CAO EQU CA1+1 C2B2 EQU CAO+1 C2B1 EQU C2B2+1 C3B2 EQU C2B1+1 C3B1 EQU C3B2+1 C4B2 EQU C3B1+1 C4B1 EQU C4B2+1

" FREQ-E.ASM "

* LOCATIONS FOR FIRST SINUSOIDAL * DELTA 1 to be defined in the main program

OFSTC1 EQU DELTA1+1 * offset from first cos table addr OFSTS1 EQU OFSTC1+1 * offset from first sin table addr COSVLl EQU OFSTS1+1 * cos value read from table SINVLl EQU COSVL1+1 * sin value read from table TEMPI EQU SINVL1+1 * LOCATIONS FOR SECOND SINUSOIDAL DELTA2 EQU TEMP1+1 OFSTC2 EQU DELTA2+1 OFSTS2 EQU OFSTC2+1 COSVL2 EQU OFSTS2+1 SINVL2 EQU COSVL2+1 TEMP 2 EQU SINVL2+1 MASK EQU TEMP2+1 * init. to >7FFF for 128 pt. table FIRST EQU MASK+1 * init. to start of table addr. SPRA EQU FIRST+1 * seperation between cos & sin in ★ * the table - 112-

" COS-D.ASM "

* ROM LOOK-UP TABLE FOR SINE & COSINE WAVE GENERATION * ALL DATA IS IN Q15 FORMAT

DATA 32767 * cos of angle 0.00000 rad DATA 32729 ★ 0.04909 rad DATA 32610 ★ 0.09817 rad DATA 32413 ★ 0.14726 rad DATA 32138 * 0.19635 rad DATA 31786 * 0.24544 rad DATA 31357 ★ 0.29452 rad DATA 30853 * 0.34361 rad DATA 30274 * 0.39270 rad DATA 29622 * 0.44179 rad DATA 28899 * 0.49087 rad DATA 28106 * 0.53996 rad DATA 27246 * 0.58905 rad DATA 26320 * 0.63814 rad DATA 25330 * 0.68722 rad DATA 24279 ★ 0.73631 rad DATA 23170 * 0.78540 rad DATA 22006 ★ 0.83449 rad DATA 20788 ★ 0.88357 rad DATA 19520 ★ 0.93266 rad DATA 18205 ★ 0.98175 rad DATA 16846 * 1.03084 rad DATA 15447 * 1.07992 rad DATA 14010 ★ 1.12901 rad DATA 12540 * 1.17810 rad DATA 11039 ★ 1.22718 rad DATA 9512 * 1.27627 rad DATA 7962 * 1.32536 rad DATA 6393 ★ 1.37445 rad DATA 4808 ★ 1.42353 rad DATA 3212 * 1.47262 rad DATA 1608 ★ 1.52171 rad DATA 0 ★ 1.57080 rad DATA -1608 ★ 1.61988 rad DATA -3212 * 1.66897 rad DATA -4808 * 1.71806 rad DATA -6393 ★ 1.76715 rad DATA -7962 ★ 1.81623 rad DATA -9512 * 1.86532 rad DATA -11039 * 1.91441 rad DATA -12540 * 1.96350 rad DATA -14010 * 2.01258 rad DATA -15447 * 2.06167 rad DATA -16846 ★ 2.11076 rad -113-

DATA -18205 * 2.15984 rad DATA -19520 * 2.20893 rad DATA -20788 * 2.25802 rad DATA -22006 * 2.30711 rad DATA -23170 * 2.35619 rad DATA -24279 ★ 2.40528 rad DATA -25330 ★ 2.45437 rad DATA -26320 * 2.50346 rad DATA -27246 ★ 2.55254 rad DATA -28106 * 2.60163 rad DATA -28899 * 2.65072 rad DATA -29622 ★ 2.69981 rad DATA -30274 * 2.74889 rad DATA -30853 * 2.79798 rad DATA -31357 ★ 2.84707 rad DATA -31786 ★ 2.89616 rad DATA -32138 ★ 2.94524 rad DATA -32413 * 2.99433 rad DATA -32610 ★ 3.04342 rad DATA -32729 ★ 3.09251 rad DATA -32768 ★ 3.14159 rad DATA -32729 * 3.19068 rad DATA -32610 ★ 3.23977 rad DATA -32413 ★ 3.28885 rad DATA -32138 ★ 3.33794 rad DATA -31786 ★ 3.38703 rad DATA -31357 ★ 3.43612 rad DATA -30853 * 3.48520 rad DATA -30274 * 3.53429 rad DATA -29622 * 3.58338 rad DATA -28899 * 3.63247 rad DATA -28106 ★ 3.68155 rad DATA -27246 * 3.73064 rad DATA -26320 ★ 3.77973 rad DATA -25330 * 3.82882 rad DATA -24279 ★ 3.87790 rad DATA -23170 * 3.92699 rad DATA -22006 ★ 3.97608 rad DATA -20788 ★ 4.02517 rad DATA -19520 * 4.07425 rad DATA -18205 ★ 4.12334 rad DATA -16846 ★ 4.17243 rad DATA -15447 * 4.22152 rad DATA -14010 * 4.27060 rad DATA -12540 ★ 4.31969 rad DATA -11039 * 4.36878 rad DATA -9512 ★ 4.41786 rad DATA -7962 ★ 4.46695 rad DATA -6393 ★ 4.51604 rad DATA -4808 ★ 4.56513 rad DATA -3212 * 4.61421 rad - 114 -

DATA -1608 ★ 4.66330 rad DATA 0 ★ 4.71239 rad DATA 1608 * 4.76148 rad DATA 3212 ★ 4.81056 rad DATA 4808 * 4.85965 rad DATA 6393 * 4.90874 rad DATA 7962 * 4.95783 rad DATA 9512 ★ 5.00691 rad DATA 11039 * 5.05600 rad DATA 12540 ★ 5.10509 rad DATA 14010 ★ 5.15418 rad DATA 15447 * 5.20326 rad DATA 16846 ★ 5.25235 rad DATA 18205 * 5.30144 rad DATA 19520 * 5.35052 rad DATA 20788 * 5.39961 rad DATA 22006 ★ 5.44870 rad DATA 23170 * 5.49779 rad DATA 24279 * 5.54687 rad DATA 25330 * 5.59596 rad DATA 26320 * 5.64505 rad DATA 27246 * 5.69414 rad DATA 28106 * 5.74322 rad DATA 28899 ★ 5.79231 rad DATA 29622 ★ 5.84140 rad DATA 30274 * 5.89049 rad DATA 30853 ★ 5.93957 rad DATA 31357 ★ 5.98866 rad DATA 31786 ★ 6.03775 rad DATA 32138 ★ 6.08684 rad DATA 32413 ★ 6.13592 rad DATA 32610 ★ 6.18501 rad - 115-

MACRO "FIL "

* THIS MACRO PERFORMS FILTERING FOR EACH 2 nd ORDER SECTION

* INPUT TO MACRO "FIL" ARE LOCATIONS FOR : * 1. present input sample * 2. coefficient b2 * 3. coefficient a2

FIL $MACRO VX0,CB2, CA2 $VAR VXl,VX2, VYl,VY2, $ASG VXO.V+1 TO VX1.V $ASG VX1.V+1 TO VX2 .V $ASG VX2 . V+l TO VYl. V $ASG VYl.V+l TO VY2 .V $ASG CB2.V+1 TO CB1.V $ASG VA2.V+l TO VAl. V $ASG VAl.V+l TO VAO.V

ZAC LT VX2 .V MPY CA2 .V LTD VXl .V MPY CA1.V LTD VXO .V MPY CAO .V LTA VY2 .V MPY CB2 .V LTD VYl .V MPY CB1.V APAC SACH VYl.V: r 1 $END -116 -

MACRO " TABLE "

* THIS MACRO READS COSINE & SINE VALUES FROM * THE ROM TABLE AND UPDATES FOR NEXT TIME * INPUT TO MACRO "TABLE" IS LOCATION FOR : * 1. increment - DELTA

TABLE $MACRO DELTA $VAR OFSTC,OFSTS,COSVL,SINVL,TEMP $ASG DELTA.V+l TO OFSTC.V $ASG OFSTC.V+l TO OFSTS.V $ASG OFSTS.V+1 TO COSVL.V $ASG COSVL.V+l TO SINVL.V $ASG SINVL.V+l TO TEMP.V

* FOR COSINE LAC .•OFSTC.V: , 8 SACH :TEMP.V: LAC :TEMP.V: ADD FIRST TBLR :COSVL.V * cos value in Q15

* FOR SINE LAC :OFSTS.V:,8 SACH : TEMP . V: LAC :TEMP.V: ADD FIRST TBLR :SINVL.V: * sin value in Q15

* UPDATING LAC :OFSTC.V: ADD :DELTA.V: SACL :OFSTS.V: AND MASK * modulo 128 mask SACL :OFSTC.V: * store next cosine addr LAC :OFSTS.V: ADD SPRA AND MASK SACL :OFSTS.V: * store next sine addr. $END - 117-

" SINE "

* GENERATING SINUSOIDAL WAVE

DELTA EQU 0 ★ init. to increment value (in Q8) OFSET EQU DELTA+1 * offset from first cos * ★ table address COSVL EQU OFSET+1 ★ cos value picked from table TEMP EQU COSVL+1 MASK EQU TEMP+1 ★ init. to >7FFF for 128 pt. table FIRST EQU MASK+1 * init. to start of table address YO EQU 10 * output AORG 0000 RST B BEGIN AORG 24 INTR B GETIT AORG >300 * LOOK--UP TABLE FOR SINE or COSINE FUNCTION COPY COS-D.ASM MI DATA >7FFF INCRE DATA 2360 AORG >20 BEGIN DINT ROVM SSXM LDPK 0 SPM 0 LARP AR4 LARK AR4,3 LACK 50 * using timer interrupt SACL *+ * with interrupt freq= 25 kHz LALK >FFC8 * Mask all interrupts except SACL *+ * timer interrupt SACH ★ LDPK 6 LALK SEP TBLR SPRA LALK Ml TBLR MASK LALK INCRE * in Q8 format TBLR DELTA LALK COS SACL FIRST ZAC SACL OFSET EINT LOOP IDLE -118-

B LOOP GETIT DINT LAC OFSET,8 SACH TEMP LAC TEMP ADD FIRST TBLR COSVL ★ cos value in Q15 ADD DELTA * calc. next addr. AND MASK * modulo 128 mask SACL OF SET * store next addr. LAC SINVL,15 SACH Y0,1 OUT YO, 0 EINT RET END - 119-

" TIMING "

* TO GENERATE EXACT TIMING USING INTERNAL TIMER

YO EQU 0 AORG 0000 RESET B BEGIN AORG 24 INTR B OUTPUT AORG >20 BEGIN DINT ROVM SSXM LDPK 0 SPM 0 LARP AR4 LARK AR4,3 LACK 50 ★ using timer interrupt SACL *+ * with intr. freq= 25 kHz LALK >FFC8 * mask all interrupts except SACL * + ★ timer interrupt SACH ★ LDPK 6 LACK >7FFF SACL Y0 EINT * Wait for internal timer interrupt WAIT IDLE B WAIT OUTPUT DINT LAC Y0 NEG SACL Y0 OUT Y0,0 EINT RET END -120 -

" LPF8 "

* LOWPASS HR FILTER * Cut-Off Freq =1.5 kHz ; Sampling Freq=25 kHz

VAL EQU 20 XO EQU 42 * input * LOCATIONS FOR DELAYED INPUT AND OUTPUT SAMPLES V1X0 EQU 0 COPY V-E.ASM * LOCATIONS FOR FILTER COEFFICIENTS C1B2 EQU 21 COPY C-E.ASM * FILTER COEFFICIENTS DATA IN Q15 FORMAT AORG >20 D1B2 DATA -32424 D1B1 DATA 63192 DA2 DATA 152 DAI DATA 304 DAO DATA 152 D2B2 DATA -31776 D2B1 DATA 63112 D3B2 DATA -31288 D3B1 DATA 63400 D4B2 DATA -31024 D4B1 DATA 63688

AORG 0000 RESET B START INTR B SMPL AORG >50 START DINT * PROCESSOR INITIALIZATION INIT ROVM SSXM LDPK 0 SPM 0 LARP AR4 LARK AR4, 3 LALK >FFFF SACL *+ * enable all interrupts SACL *+ SACH * LDPK 6 ZAC * Initially clear all locations LRLK AR4,>300 RPTK VAL SACL *+ -121 -

LRLK AR4,>315 LACK >20 RPTK 19 TBLR *+

IN X0,0 * DUMMY! to kick A/D conversion EINT WAIT IDLE B WAIT * wait for interrupt

SMPL IN V1X0,0 * 8th ORDER FILTER WITH 2nd ORDER SECTIONS IN CASCADE FIL V1X0,C1B2,CA2 SACH V2X0,1 FIL V2X0,C2B2,CA2 SACH V3X0,1

FIL V3X0,C3B2,CA2 SACH V4X0,1

FIL V4X0,C4B2,CA2 SACH V4Y0,1 OUT V4Y0,0 RET END - 122-

MACRO " THRES "

* THIS MACRO CHECKS IF THE INPUT IS BELOW THE THRESHOLD * (and since when)

THRS $MACRO X0,Y0 THRSP equ 655 ★ Threshold for +100 mV THRSM EQU -655 * Threshold for -100 mV CNTVL EQU 1000 * COUNT EQU 100 * count of no. of consective input * * samples below threshold ( ±100 mV) * Check for input below threshold levels * (i . e . between ±100 mV) else Exit LAC :X0.S: SBLK :THRSP.S BGZ EXIT o LAC CO SBLK :THRSM.S BLZ EXIT If input below threshold for a time < CNTVL LAC :COUNT.S: SBLK :CNTVL.S: BGEZ CLEAR then increment COUNT INCR LAC :COUNT.S: ADLK :ONE.S: SACL :COUNT.S: B RETRN * else Clear the output CLEAR ZAC SACL :Y0.S: B RETRN EXIT ZAC SACL :COUNT.S: RETRN NOP $END -123-

" V-E.ASM "

* LOCATIONS FOR STORING DELAYED INPUT & OUTPUT SAMPLES * FOR 8 th ORDER HR FILTER WITH CASCADE STRUCTURE * ( for upper branch filter )

V1X1 EQU V1X0+1 V1X2 EQU V1X1+1 V1Y1 EQU V1X2+1 V1Y2 EQU V1Y1+1 V2X0 EQU V1Y2+1 V2X1 EQU V2X0+1 V2X2 EQU V2X1+1 V2Y1 EQU V2X2+1 V2Y2 EQU V2Y1+1 V3X0 EQU V2Y2+1 V3X1 EQU V3X0+1 V3X2 EQU V3X1+1 V3Y1 EQU V3X2+1 V3Y2 EQU V3Y1+1 V4X0 EQU V3Y2+1 V4X1 EQU V4X0+1 V4X2 EQU V4X1+1 V4Y0 EQU V4X2+1 V4Y1 EQU V4Y0+1 V4Y2 EQU V4Y1+1 - 124 -

" W-E.ASM "

* LOCATIONS FOR STORING DELAYED INPUT & OUTPUT SAMPLES * FOR 8 th ORDER HR FILTER WITH CASCADE STRUCTURE * ( for lower branch filter )

W1X1 EQU W1X0+1 W1X2 EQU W1X1+1 W1Y1 EQU W1X2+1 W1Y2 EQU W1Y1+1 W2X0 EQU W1Y2+1 W2X1 EQU W2X0+1 W2X2 EQU W2X1+1 W2Y1 EQU W2X2+1 W2Y2 EQU W2Y1+1 W3X0 EQU W2Y2+1 W3X1 EQU W3X0+1 W3X2 EQU W3X1+1 W3Y1 EQU W3X2+1 W3Y2 EQU W3Y1+1 W4X0 EQU W3Y2+1 W4X1 EQU W4X0+1 W4X2 EQU W4X1+1 W4Y0 EQU W4X2+1 W4Y1 EQU W4Y0+1 W4Y2 EQU W4Y1+1 -125-

TXER

* SSB MODULATION BY WEAVER’S METHOD

VAL EQU 41 * LOCATIONS FOR DELAYED INPUT AND OUTPUT SAMPLES * FOR LOWPASS HR FILTERS V1X0 EQU 0 * for filter in upper branch COPY V-E.ASM W1X0 EQU 21 * for filter in lower branch COPY W-E.ASM * LOCATIONS FOR LOWPASS IIR FILTER COEFFICIENTS C1B2 EQU 51 COPY C-E.ASM * LOCATIONS FOR DATA REQUIRED IN SINE & COSINE * FUNCTIONS GENERATION DELTA1 EQU 71 COPY FREQ-E.ASM XO EQU 86 * input AORG 00 RESET B BEGIN AORG 24 INTR B SMPL AORG >300 * LOOK -UP TABLE FOR GENERATING SINE & COSINE COPY COS-D.ASM * DATA FOR FUNCTION GENERATION Ml DATA >7FFF INCRE1 DATA 2359 * Sinusoidal freq = 1.8 kHz INCRE2 DATA 14132 * Sinusoidal freq = 10 kHz SEP DATA >6000 * Separation between ★ * in the table AORG >390 * IIR FILTER TAP COEFFICIENTS IN Q15 FORMAT D1B2 DATA -31736 D1B1 DATA 59920 DA2 DATA 432 DAI DATA 864 DAO DATA 432 D2B2 DATA -29880 D2B1 DATA 59352 D3B2 DATA -28480 D3B1 DATA 59672 D4B2 DATA -27720 D4B1 DATA 60104 AORG >20 -126 -

* PROCESSOR INITIALIZATION BEGIN SXF ROVM SSXM LDPK 0 SPM 0 LARP AR4 LARK AR4, 3 LACK 50 * using internal timer interrupt SACL ★4. * interrupt freq= 25.0 kHz LALK >FFC8 * mask all interrupts except SACL *+ * timer interrupt SACH *

LDPK 6 LALK Ml TBLR MASK LALK INCREl TBLR DELTA1 LALK INCRE2 TBLR DELTA2 LALK SEP TBLR SPRA LALK COS SACL FIRST ZAC SACL OFSTC1 SACL OFSTC2 LAC SPRA SACL OFSTS1 SACL OFSTS2

* Initialization for the filter section ZAC * Initially clear all locations LRLK AR4,>300 RPTK VAL SACL *+ LRLK AR4,>333 LALK >390 RPTK 10 TBLR *+ EINT WAIT IDLE B WAIT * Wait for TIMER Interrupt SMPL IN X0,0 * Get the input * READING THE COSINE & SINE VALUES * FROM THE LOOK-UP TABLE AND UPDATING FOR NEXT TIME * - FOR CARRIER FREQ. OF 1800 Hz - TABLE DELTA1 * PROCESSING IN THE UPPER BRANCH - 127 -

* FIRST COSINE MODULATION LT COSVLl MPY XO PAC SACH V1X0,1 UPPER BRANCH LOWPASS FILTER Cut-Off Freq =1.5 kHz FIL V1X0,C1B2,CA2 SACH V2X0,1 FIL V2X0,C2B2,CA2 SACH V3X0,1 FIL V3X0,C3B2,CA2 SACH V4X0,1 FIL V4X0,C4B2rCA2 SACH V4Y0,1 * READING SECOND COSINE & SINE VALUES * FROM THE LOOK-UP TABLE AND UPDATING FOR NEXT TIME * - FOR CARRIER FREQ. OF 10 kHz - TABLE DELTA2 * SECOND COSINE MODULATION LT COSVL2 MPY V4Y0 PAC SACH V4Y0,1 PROCESSING IN THE LOWER BRANCH

★ FIRST SINE MODULATION LT SINVL1 MPY XO PAC SACH W1X0,1 * LOWER LOWPASS FILTER * cutoff freq = 1.5 kHz FIL W1X0,C1B2 rCA2 SACH W2X0,1 FIL W2X0,C2B2,CA2 SACH W3X0,1 FIL W3X0,C3B2,CA2 SACH W4X0,1 FIL W4X0,C4B2 rCA2 SACH W4Y0,1 * SECOND SINE MODULATION LT SINVL2 MPY W4Y0 PAC SACH W4Y0,1 - 128-

LAC W4Y0 * Add the outputs from two ADD V4Y0 * branches to get SSB signal SACL W4Y0 r1 LOOP BIOZ READY ★ Check if Receiver is ready B LOOP * else wait READY OUT W4Y0,0 LARK AR4, 5 CONV BANZ CONV,*- * Allow time for D/A conversion RXF ★ Inform Receiver of new data ACKN BIOZ ACKN ★ Wait for acknowledgement * * from Receiver SXF EINT RET END - 129 -

RXER

* SSB DE-MODULATION BY WEAVER’S METHOD

VAL EQU 41 * LOCATIONS FOR DELAYED INPUT AND OUTPUT SAMPLES * FOR LOWPASS HR FILTERS V1X0 EQU 0 * for filter in upper branch COPY V-E.ASM W1X0 EQU 21 * for filter in lower branch COPY W-E.ASM * LOCATIONS FOR LOWPASS IIR FILTER COEFFICIENTS C1B2 EQU 51 COPY C-E.ASM LOCATIONS FOR DATA REQUIRED IN SINE & COSINE FUNCITONS GENERATION DELTA1 EQU 71 COPY FREQ-E.ASM XO EQU 86 AORG 00 RESET B BEGIN INTR B SMPL AORG >300 * LOOK--UP TABLE FOR GENERATING SINE & COSINE COPY COS-D.ASM * DATA FOR FUNCITON GENERATION Ml DATA >7FFF INCREl DATA 14132 * Sinusoidal freq = :10 kHz INCRE2 DATA 2359 * Sinusoidal freq = :1.8 kHz SEP DATA >6000 * Separation between ★ * in the table AORG >390 * IIR FILTER TAP COEFFICIENTS IN Q15 FORMAT D1B2 DATA -31736 D1B1 DATA 59920 DA2 DATA 432 DAI DATA 864 DAO DATA 432 D2B2 DATA -29880 D2B1 DATA 59352 D3B2 DATA -28480 D3B1 DATA 59672 D4B2 DATA -27720 D4B1 DATA 60104 AORG >20 * PROCESSOR INITIALIZATION -130 -

BEGIN SXF ROVM SSXM LDPK 0 SPM 0 LARP AR4 LARK AR4, 3 LALK >FFFF SACL *+ * enable all interrupts SACL *+ SACH * LDPK 6 LALK Ml TBLR MASK LALK INCRE1 TBLR DELTA1 LALK INCRE2 TBLR DELTA2 LALK SEP TBLR SPRA LALK COS SACL FIRST ZAC SACL OFSTC1 SACL OFSTC2 LAC SPRA SACL OFSTS1 SACL OFSTS2 * Initialization for the ZAC * Initially clear all locations LRLK AR4,>300 RPTK VAL SACL *+ LRLK AR4,>333 LALK >390 RPTK 10 TBLR *+ RXF * WAIT FOR TRANSMIT SIGNAL WAIT BIOZ GETIN Wait for transmit signal B WAIT from Transmitter GET IN SXF IN X0,0 * DUMMY ! To kick off A/D conv. EINT * WAIT FOR A/D CONVERSION WAIT2 IDLE B WAIT2 o o SMPL IN X get the input -131 -

RXF * READING THE COSINE & SINE VALUES * FROM THE LOOK-UP TABLE AND UPDATING FOR NEXT TIME * - FOR CARRIER FREQ. OF 10 kHz - TABLE DELTA1

* PROCESSING IN THE UPPER BRANCH

FIRST COSINE MODULATION LT COSVLl MPY XO PAC SACH V1X0,1 UPPER BRANCH LOWPASS FILTER Cut-Off Freq =1.5 kHz FIL V1X0,C1B2,CA2 SACH V2X0,1 FIL V2X0,C2B2,CA2 SACH V3X0,1 FIL V3X0,C3B2,CA2 SACH V4X0,1 FIL V4X0,C4B2,CA2 SACH V4Y0,1 * READING THE COSINE & SINE VALUES * FROM THE LOOK-UP TABLE AND UPDATING FOR NEXT TIME * - FOR CARRIER FREQ. OF 1800 Hz - TABLE DELTA2 ★ SECOND COSINE MODULATION LT COSVL2 MPY V4Y0 PAC SACH V4Y0,1

* PROCESSING IN THE LOWER BRANCH * * FIRST SINE MODULATION LOWER LT SINVL1 MPY XO PAC SACH W1X0,1 ★ LOWER BRANCH LOWPASS FILTER * cutoff freq = 1.5 kHz FIL W1X0,C1B2,CA2 SACH W2X0,1 FIL W2X0,C2B2,CA2 SACH W3X0,1 FIL W3X0,C3B2,CA2 SACH W4X0,1 - 132 -

FIL W4X0,C4B2,CA2 SACH W4Y0,1 * SECOND SINE MODULATION LT SINVL2 MPY W4Y0 PAC SACH W4Y0,1 LAC W4Y0 ★ Add the outputs from ADD V4Y0 ★ the two branches to get SACL W4Y0,1 * the demodulated signal OUT W4Y0,0 RET END -133 -

"FIRV-E.ASM "

* LOCATIONS FOR DELAYED SAMPLES * FOR upper INTERPOLATION/DECIMATION FILTER * VO is defined in the MAIN program

VI EQU VO+1 V2 EQU Vl+1 V3 EQU V2+1 V4 EQU V3+1 V5 EQU V4+1 V6 EQU V5+1 V7 EQU V6+1 V8 EQU V7+1 V9 EQU V8+1 VI0 EQU V9+1 VI1 EQU V10+1 V12 EQU Vll+1 V13 EQU V12+1 VI4 EQU V13+1 VI5 EQU V14+1 VI6 EQU V15+1 V17 EQU VI6+1 VI8 EQU V17+1 VI9 EQU V18+1 V20 EQU VI9+1 V21 EQU V20+1 V22 EQU V21+1 V23 EQU V22+1 V24 EQU V23+1 V25 EQU V24+1 V26 EQU V25+1 V27 EQU V26+1 V28 EQU V27+1 V29 EQU V28+1 V30 EQU V29+1 V31 EQU V30+1 V32 EQU V31+1 V33 EQU V32+1 V34 EQU V33+1 V35 EQU V34+1 V36 EQU V35+1 V37 EQU V36+1 V38 EQU V37+1 V39 EQU V38+1 V40 EQU V39+1 V41 EQU V40+1 - 134 -

" FIRW-E.ASM "

* LOCATIONS FOR DELAYED SAMPLES * FOR lower INTERPOLATION/DECIMATION FILTER * WO is defined in the MAIN program

W1 EQU WO+1 W2 EQU Wl+1 W3 EQU W2+1 W4 EQU W3+1 W5 EQU W4+1 W6 EQU W5+1 W7 EQU W6+1 W8 EQU W7+1 W9 EQU W8+1 W10 EQU W9+1 Wll EQU W10+1 W12 EQU Wll+1 W13 EQU W12+1 W14 EQU W13+1 W15 EQU W14+1 W16 EQU W15+1 W17 EQU W16+1 W18 EQU W17+1 W19 EQU W18+1 W20 EQU W19+1 W21 EQU W20+1 W22 EQU W21+1 W23 EQU W22+1 W24 EQU W23+1 W25 EQU W24+1 W26 EQU W25+1 W27 EQU W26+1 W28 EQU W27+1 W29 EQU W28+1 W30 EQU W29+1 W31 EQU W30+1 W32 EQU W31+1 W33 EQU W32+1 W34 EQU W33+1 W35 EQU W34+1 W36 EQU W35+1 W37 EQU W36+1 W38 EQU W37+1 W39 EQU W38+1 W40 EQU W39+1 W41 EQU W40+1 H41 DATA 40 H40 DATA -48 H39 DATA 56 H38 DATA -80 H37 DATA 112 H36 DATA -152 H35 DATA 200 H34 DATA -256 H33 DATA 336 H32 DATA -424 H31 DATA 536 H30 DATA -664 H29 DATA 824 H28 DATA -1024 H27 DATA 1280 H26 DATA -1616 H25 DATA 2080 H24 DATA -2792 H23 DATA 4032 H22 DATA -6872 H21 DATA 20832 H20 DATA 20832 H19 DATA -6872 H18 DATA 4032 H17 DATA -2792 H16 DATA 2080 H15 DATA -1616 H14 DATA 1280 H13 DATA -1024 H12 DATA 824 Hll DATA -664 H10 DATA 536 H9 DATA -336 H8 DATA 336 H7 DATA -256 H6 DATA 200 H5 DATA -152 H4 DATA 112 H3 DATA -80 H2 DATA 56 HI DATA -42 HO DATA 40 -136 -

"INPOL "

SSB MODULATION BY WEAVER’S METHOD (with INTERPOLATION)

VAL EQU 41 TIMES EQU 41 * LOCATIONS FOR DELAYED INPUT AND OUTPUT SAMPLES * FOR LOWPASS IIR FILTERS V1X0 EQU 0 * for filter in the upper branch COPY V-E.ASM W1X0 EQU 21 * for filter in the lower branch COPY W-E.ASM * LOCATIONS FOR LOWPASS FILTER COEFFICIENTS C1B2 EQU 51 COPY C-E.ASM * LOCATIONS FOR DATA REQUIRED IN SINE & COSINE * FUNCTION GENERATION DELTA1 EQU 71 COPY FREQ-E.ASM XO EQU 120 TEST EQU 77 PLOUTl EQU 1 PLOUT2 EQU 2 Y0 EQU 3 * LOCATIONS FOR DELAYED SAMPLES OF INTERPOLATION FILTERS VO EQU 11 * in the upper branch COPY FIRV—E.ASM WO EQU 60 * in the lower branch COPY FIRW-E.ASM AORG 00 RST B BEGIN AORG 24 INTR B GETIT AORG >300 * LOOK--UP TABLE FOR GENERATING SINE & COSINE FUNCTIONS COPY COS-D.ASM * DATA FOR FUNCTION GENERATION Ml DATA >7FFF INCREl DATA 2437 * Sinusoidal freq = 1800 Hz INCRE2 DATA 10836 * Sinusoidal freq = 10 kHz SEP DATA >6000 * Separation between Cos & Sin in TESTY DATA 2 * for SET or RESET of 'TC' bit AORG >390 * HR FILTER TAP COEFFICIENTS IN Q15 FORMAT D1B2 DATA -31504 -137 -

D1B1 DATA 57296 DA2 DATA 656 DAI DATA 1304 DAO DATA 656 D2B2 DATA -29248 D2B1 DATA 57016 D3B2 DATA -27536 D3B1 DATA 57904 D4B2 DATA -26600 D4B1 DATA 58776 * COEFFICIENTS FOR INTERPOLATION FILTER COEFF AORG >400 COPY H-E.ASM AORG >20 * PROCESSOR INITIALIZATION SXF ROVM SSXM LDPK 0 SPM 0 LARP AR4 LARK AR4,3 LACK 52 * using internal timer interrupt SACL *+ ★ with interrupt freq= 24 kHz LALK >FFC8 * mask all interrupts except SACL *+ * timer interrupt SACH * * Copy all data from PMA to DMA LDPK 6 LALK Ml TBLR MASK LALK INCREl TBLR DELTA1 LALK SEP TBLR SPRA LALK COS SACL FIRST ZAC SACL OFSTC1 LAC SPRA SACL OFSTSI LDPK 7 LALK Ml TBLR MASK LALK INCRE2 TBLR DELTA2 LALK SEP -138 -

TBLR SPRA LALK COS TBLR FIRST ZAC SACL OFSTC2 LAC SPRA SACL OFSTS2 LDPK 6

* Initialization for the filter sections ZAC * Initially clear all locations LRLK AR4,>300 * Corresponds to V1X0 RPTK VAL SACL *+ LRLK AR4,>38B * Corresponds to V0 RPTK TIMES SACL *+ LRLK AR4,>3BC * Corresponds to W0 RPTK TIMES SACL *+

* Copy filter coefficients from PMA to DMA LRLK AR4,>333 * for IIR filter LALK >390 RPTK 10 TBLR *+ LRLK AR4,>200 * for Interpolation filter RPTK TIMES BLKP COEFF,*+ CNFP LALK TESTY TBLR TEST BIT TEST,>F (i.e. TC —> 0 ) EINT WAIT IDLE B WAIT * wait for timer interrupt GETIT BBNZ LOOP 2 * test BIT for loop 1 or 2 L00P1 IN X0,0 * GET THE INPUT NOP

* READING THE COSINE & SINE VALUES * FROM THE LOOK-UP TABLE AND UPDATING FOR NEXT TIME * - FOR CARRIER FREQ. OF 1800 Hz - TABLE DELTA1 * FIRST COSINE MODULATION LT COSVLl MPY XO PAC SACH V1X0,1 * UPPER BRANCH LOWPASS HR FILTER -139 -

* Cut-Off Freq =1.5 kHz FIL V1X0,C1B2,CA2 SACH V2X0,1 FIL V2X0,C2B2,CA2 SACH V3X0,1 FIL V3X0,C3B2,CA2 SACH V4X0,1 FIL V4X0,C4B2,CA2 SACH V4Y0,1 ZAC LDPK 7 SACL VO SACL WO LDPK 6 CALL INPOLA BIT TEST,>E * TC —> 1 ) EINT RET * FIRST SINE MODULATION LOOP2 LT SINVL1 MPY XO PAC SACH W1X0,1 * LOWER BRANCH LOWPASS HR FILTER * Cut-Off freq = 1.5 kHz FIL W1X0,C1B2,CA2 SACH W2X0,1 FIL W2X0,C2B2,CA2 SACH W3X0,1 FIL W3X0,C3B2,CA2 SACH W4X0,1 FIL W4X0,C4B2,CA2 SACH W4Y0,1 LDPK 7 SACH WO, 1 LDPK 6 LAC V4Y0 LDPK 7 SACL VO CALL INPOLA BIT TEST,>F * ( i.e. TC —> 0 ) EINT RET - 140 -

* SUBROUTINE "INPOLA" * PERFORMS : INTERPOLATION and SECOND MODULATION * OUTPUTS AT 20 kHz RATE INPOLA LDPK 7 LRLK AR4,>3B4 * corresponds to V41 MPYK 0 ZAC * Interpolation (filtering) RPTK TIMES * in UPPER branch MACD >FF00,*- APAC SACH PLOUTl,1 * READING SECOND COSINE & SINE VALUES * FROM THE LOOK-UP TABLE AND UPDATING FOR NEXT TIME - FOR CARRIER FREQ. OF 10 KHz - TABLE DELTA2 SECOND COSINE MODULATION LT COSVL2 MPY PLOUTl PAC SACH PLOUTl,1 LRLK AR4,>3D5 * corresponds to W41 MPYK 0 * Interpolation (filtering) ZAC * in LOWER branch RPTK TIMES MACD >FF 0 0,*- APAC SACH PLOUT2,1 1ECOND SINE MODULATION LT SINVL2 MPY PLOUT2 PAC SACH PLOUT2,1 LAC PLOUTl * Add the outputs from two ADD PLOUT2 * branches to get SSB signal SACL Y0,1 OUT Y0,0 LDPK 6 RET END - 141 -

" OECIM "

* SSB DEMODULATION BY WEAVER’S METHOD (with DECIMATION)

VAL EQU 41 TIMES EQU 41 * LOCATIONS FOR DELAYED INPUT AND OUTPUT SAMPLES * FOR LOWPASS HR FILTERS (INCLUDING DELAYED) V1X0 EQU 0 * for filter in upper branch COPY V-E.ASM W1X0 EQU 21 * for filter in lower branch COPY W-E.ASM * LOCATIONS FOR LOWPASS IIR FILTER COEFFICIENTS C1B2 EQU 51 COPY C-E.ASM * LOCATIONS FOR DATA REQUIRED IN SINE & COSINE * FUNCTIONS GENERATION DELTAl EQU 71 * init. to increment value (in Q8) COPY FREQ-E.ASM XO EQU 120 * input TEST EQU 77 Y0 EQU 3 * LOCATIONS FOR DELAYED SAMPLES OF DECIMATION FILTERS VO EQU 11 * upper branch filter COPY FIRV—E.ASM WO EQU 60 * lower branch filter COPY FIRW—E.ASM AORG 00 RST B BEGIN AORG 24 INTR B SMPL AORG >300 * LOOK--UP TABLE FOR SINE & COSINE FUNCTIONS GENERATION COPY COS—D.ASM * DATA REQUIRED FOR FUNCTIONS GENERATION Ml DATA >7FFF INCREl DATA 10836 * Sinusoidal freq =10 kHz INCRE2 DATA 2437 * Sinusoidal freq = 1800 Hz SEP DATA >6000 * Separation between Cos & Sin : TESTY DATA 2 * to SET or RESET the 'TC' bit AORG >390 * IIR FILTER TAP COEFFICIENTS IN Q15 FORMAT D1B2 DATA -31504 D1B1 DATA 57296 DA2 DATA 656 DAI DATA 1304 - 142-

DAO DATA 656 D2B2 DATA -29248 D2B1 DATA 57016 D3B2 DATA -27536 D3B1 DATA 57904 D4B2 DATA -26600 D4B1 DATA 58776 * COEFFICIENTS FOR DECIMATION FILTER IN Q15 FORMAT COEFF AORG >400 COPY H-E.ASM AORG >20 BEGIN SXF ROVM SSXM LDPK 0 SPM 0 LARP AR4 LARK AR4,3 LACK 52 * using internal timer interrupt SACL *+ * with intr. freq= 24 kHz LALK >FFC8 * mask all interrupts except SACL *+ * timer interrupt SACH ★ * Copy all data from PMA to DMA LDPK 6 LALK Ml TBLR MASK LALK INCRE1 * in Q8 format TBLR DELTA1 LALK SEP TBLR SPRA LALK COS SACL FIRST ZAC SACL OFSTC1 LAC SPRA SACL OFSTS1 LDPK 7 LALK Ml TBLR MASK LALK INCRE2 TBLR DELTA2 LALK SEP TBLR SPRA LALK COS TBLR FIRST ZAC SACL OFSTC2 -143-

LAC SPRA SACL OFSTS2 LDPK 6

★ Initialization for the filter section ZAC * Initially clear all locations LRLK AR4,>300 * Corresponds to V1X0 RPTK VAL SACL *+ LRLK AR4,>38B * Corresponds to VO RPTK TIMES SACL *+ LRLK AR4,>3BC * Corresponds to WO RPTK TIMES SACL *+

★ Copy filter coefficients from PMA to DMA LRLK AR4,>333 LALK >390 * for HR filter RPTK 10 TBLR *+ LRLK AR4,>200 * for Decimation filter RPTK TIMES BLKP COEFF,*+ CNFP LALK TESTY TBLR TEST BIT TEST,>F (i.e. TC —> 0 ) EINT WAIT IDLE B WAIT * wait for timer interrupt SMPL LDPK 6 IN X0,0 * get the input

★ READING THE COSINE & SINE VALUES FROM THE * LOOK-UP TABLE AND UPDATING FOR NEXT TIME * - FOR CARRIER FREQ. OF 10 kHz - TABLE DELTA1 * FIRST COSINE MODULATION LT COSVLl MPY XO PAC SACH V0,1 * FIRST SINE MODULATION LT SINVLl MPY XO PAC SACH W0,1 BBNZ LOOP2 * test the 'TC' bit L00P1 LDPK 7 - 144-

DECIMATION FILTERS IN UPPER & LOWER BRANCHES LRLK AR4,>3B4 * Corresponds to V41 MPYK 0 ZAC RPTK TIMES MACD >FF00,*- APAC LDPK 6 SACH V1X0,1 * Input to upper LPF LDPK 7 LRLK AR4,>3D5 * Corresponds to W41 MPYK 0 ZAC RPTK TIMES MACD >FF00,*- APAC LDPK 6 SACH W1X0,1 * Input to lower LPF R LOWPASS FILTER b-Off Freq =1.5 kHz FIL VlXO,C1B2,CA2 SACH V2X0,1 FIL V2X0,C2B2,CA2 SACH V3X0,1 FIL V3X0,C3B2,CA2 SACH V4X0,1 FIL V4X0,C4B2,CA2 SACH V4Y0,1 BIT TEST,>E * ( i.e. TC —> 1 ) EINT RET LOOP 2 LDPK 7 LRLK AR4,>3B4 * Corresponds to V41 RPTK TIMES DMOV ★ _ ★ only shifting of samples ★ and no multiplications LRLK AR4,>3D5 * Corresponds to W41 RPTK TIMES DMOV ★ _ LDPK 6 * LOWER LOWPASS FILTER * Cut-Off freq = 1.5 kHz FIL W1X0,C1B2, CA2 SACH W2X0,1 FIL W2X0,C2B2,CA2 SACH W3X0,1 FIL W3X0,C3B2,CA2 - 145-

SACH W4X0,1

FIL W4X0,C4B2r CA2 SACH W4Y0,1 * READING THE SECOND COSINE & SINE VALUES * FROM THE LOOK-UP TABLE1 AND UPDATING FOR NEXT TIME * - FOR CARRIER FREQ. OF 1800 Hz - LDPK 7 TABLE DELTA2 * SECOND COSINE AND SINE MODULATIONS LT COSVL2 LDPK 6 MPY V4Y0 PAC SACH V4Y0,1 LDPK 7 LT SINVL2 LDPK 6 MPY W4Y0 PAC SACH W4Y0,1

LAC V4Y0 * Add the outputs from two branches ADD W4Y0 * to get the Demodulated signal LDPK 7 SACL YO OUT YO, 0 LDPK 6 BIT TEST,>F * ( i.e. TC —> 0 ) EINT RET END -146-

" PHAS-TX "

* SSB MODULATOR FOR THE PHASING METHOD * USING A CARRIER OF 8 kHz

VAL EQU 54 ★ (no. of coeffs -1) * * used in repeat instruction DELTA EQU 0 * init. to increment value (in Q8) OFSTC EQU 1 ★ offset from first cos table addr OF STS EQU 2 COSVL EQU 3 ★ cos value picked from table SINVL EQU 4 TEMP EQU 5 MASK EQU 6 * init. to >7FFF for 128 pt. table FIRST EQU 7 ★ init. to start of table addr. SPRA EQU 8

XO EQU 20 * input XI EQU 21 *---- continued- — *---down to - — X53 EQU 73 X54 EQU 74 * keep a blank location here YO EQU 640 YAO EQU 81 YBO EQU 82 YAl EQU 83 YB1 EQU 84

AORG 00 RST B BEGIN AORG 24 INTR B SMPL AORG >300 * LOOK-UP TABLE FOR SINE & COSINE FUNCTIONS GENERATION COPY COS-D.ASM Ml DATA >7FFF INCRE DATA 12325 ★ SEP DATA >6000

COEFF AORG >390 * COEFF 'S IN Q15 FOR FILTER PART H54 DATA -1824 H53 DATA 0 H52 DATA -552 H51 DATA 0 H50 DATA -640 H49 DATA 0 H48 DATA -744 - 147-

H47 DATA 0 H46 DATA -6912 H45 DATA 0 H44 DATA -1016 H43 DATA 0 H42 DATA -1200 H41 DATA 0 H40 DATA -1440 H39 DATA 0 H38 DATA -1752 H37 DATA 0 H36 DATA -2200 H35 DATA 0 H34 DATA -2888 H33 DATA 0 H32 DATA -4104 H31 DATA 0 H30 DATA -6912 H29 DATA 0 H28 DATA -20848 H27 DATA 0 H26 DATA 20848 H25 DATA 0 H24 DATA 6912 H23 DATA 0 H22 DATA 4104 H21 DATA 0 H20 DATA 2888 H19 DATA 0 H18 DATA 2200 H17 DATA 0 H16 DATA 1752 H15 DATA 0 H14 DATA 1440 H13 DATA 0 H12 DATA 1200 Hll DATA 0 H10 DATA 1016 H9 DATA 0 H8 DATA 6912 H7 DATA 0 H6 DATA 744 H5 DATA 0 H4 DATA 640 H3 DATA 0 H2 DATA 552 HI DATA 0 HO DATA 1824

AORG >20 BEGIN DINT -148 -

ROVM SSXM LDPK 0 SPM 0 LARP AR4 LARK AR4,3 LACK 40 ★ using timer interrupt SACL *+ LALK >FFC8 ★ mask all interrupts except SACL * timer interrupt SACH ★ * Copy all data from PMA to DMA LDPK 6 LALK Ml TBLR MASK LALK INCRE TBLR DELTA LALK SEP TBLR SPRA LALK COS SACL FIRST ZAC SACL OFSTC LAC SPRA SACL OFSTS * Initialization for the filter section ZAC * Initially clear all locations LRLK AR4,>314 * Corresponds to X0 RPTK VAL SACL *+ LRLK AR4,>200 RPTK VAL BLKP COEFF,*+ CNFP * use Block BO as program area EINT WAIT IDLE B WAIT SMPL DINT IN X0,0 * get the input * PHASE SHIFTING FILTER (Hilbert Transformer) LRLK AR4,>3 4A MPYK 0 ZAC RPTK VAL MACD >FF00,*- APAC SACH YBO, 1 * READ THE COSINE & SINE VALUES FROM - 149 -

* THE LOOK-UP TABLE AND UPDATE FOR NEXT TIME TABLE DELTA * COSINE AND SINE MODULATIONS LT COSVL MPY XO PAC SACH YAl, 1 LT SINVL MPY YBO PAC SACH YBl, 1 LAC YAl * Add the two outputs to get ADD YBl ★ SSB signal SACL YO, 0 HOLD BIOZ READY ★ Check if Receiver is ready else wait B HOLD READY OUT YO, 0 LARK AR4, 5 ★ Allow time for D/A convertion CONV BANZ CONV,* — RXF ★ Inform Receiver of new data ACKN BIOZ ACKN ★ Wait for acknowledgement from Receiver SXF EINT RET END -150-

" PHAS-RX "

* SSB DEMODULATOR for PHASING METHOD

VAL EQU 25 * LOCATIONS FOR DELAYED INPUT AND OUTPUT SAMPLES * FOR LOWPASS HR FILTER V1X0 EQU 0 COPY V-E.ASM V5X0 EQU V4Y2+1 V5X1 EQU V5X0+1 V5X2 EQU V5X1+1 V5Y0 EQU V5X2+1 V5Y1 EQU V5Y0+1 V5Y2 EQU V5Y1+1

* LOCATIONS FOR FILTER TAP COEFFICIENTS C1B2 EQU 26 COPY C-E.ASM C5B2 EQU C4B1+1 C5B1 EQU C5B2+1

DELTA EQU 39 * init. to increment value (in Q8) OFSTC EQU DELTA+1 * offset from first cos table addr COSVL EQU OFSTC+1 * cos value picked from table TEMP EQU COSVL+1 MASK EQU TEMP+1 * init. to >7FFF for 128 pt. table FIRST EQU MASK+1 * init. to start of table addr. XO EQU 78 * input

AORG 00 RST B BEGIN INTR B SMPL AORG >300 * LOOK-UP TABLE FOR SINE & COSINE FUNCTIONS GENERATION COPY COS-D.ASM

Ml DATA >7FFF INCRE DATA 12325 * Sinusoidal freq = 8.0 kHz

AORG >390 ★ FILTER TAP COEFFICIENTS IN Q15 FOR FILTER PART D1B2 DATA -31608 D1B1 DATA 48984 DA2 DATA 1352 DAI DATA 2712 DAO DATA 1352 D2B2 DATA -29440 D2B1 DATA 49744 D3B2 DATA -27560 -151 -

D3B1 DATA 52256 D4B2 DATA -26112 D4B1 DATA 55224 D5B2 DATA -25312 D5B1 DATA 57208 AORG >20 BEGIN SXF ROVM SSXM LDPK 0 SPM 0 LARP AR4 LARK AR4,3 LALK >FFFF SACL *+ * enable all interrupts SACL *+ SACH * * COPY ALL DATA FROM PMA TO DMA LDPK 6 LALK Ml TBLR MASK LALK INCRE TBLR DELTA LALK COS SACL FIRST ZAC SACL OFSTC * Initialization for the filter section ZAC * Initially clear all locations LRLK AR4,>300 RPTK VAL SACL *+ LRLK AR4,>31A LALK >390 RPTK 12 TBLR *+ RXF * Send ready signal to Transmitter WAIT BIOZ GETIN * Wait for new data B WAIT GETIN NOP SXF * Acknowledge Transmitter for data IN X0,0 * DUMMY ! to kick off A/D conv. EINT CONV IDLE * Wait for A/D conversion B WAIT SMPL IN X0,0 * getget thethe inputinput RXF - 152 -

NOP NOP * READ THE COSINE VALUE FROM LOOK-UP TABLE * AND UPDATE FOR NEXT TIME * - FOR CARRIER FREQ. OF Hz - LAC OFSTC,8 * FOR COS SACH TEMP LAC TEMP ADD FIRST TBLR COSVL * cos value in Q15 LAC OFSTC * updating ADD DELTA AND MASK * modulo 128 mask SACL OFSTC * store next addr. * COSINE MODULATION LT COSVL MPY XO PAC SACH V1X0,1 * LOW PASS FILTER * Cut-Off Freq =1.5 kHz FIL V1X0,C1B2,CA2 SACH V2X0,1 FIL V2X0,C2B2 ,CA2 SACH V3X0,1 FIL V3X0,C3B2,CA2 SACH V4X0,1 FIL V4X0,C4B2,CA2 SACH V5X0,1 FIL V5X0,C5B2,CA2 SACH V5Y0,1 OUT V5Y0, 0 RET END