Emerson / Motorola / Force Computers ISCSI-1 Manual (Pdf)
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Find the Emerson / Motorola / Force Computers ISCSI-1 at our website: Click HERE • SYS68K/ISCSI-1 • USER'S MANUAL Revision No. 0 NOVEMBER 1992 FORCE COMPUTERS Inc./GmbH All Rights Reserved This document shall not be duplicated, nor its contents used for any purpose, unless expose permission has been granted. Copyright by FORCE COMPUTERS® • • • • • INTRODUCTION • • • • • This page was intentionally left blank • • • • NOTE The information in this document has been carefully checked and is believed to be entirely reliable. FORCE COMPUTERS makes no warranty of any kind with regard to the material in this document, and assumes no responsibility for any errors that may appear in this document. FORCE COMPUTERS reserves the right to make changes without notice to this, or any of its products, to improve reliability, performance or design. FORCE COMPUTERS assumes no responsibility for the use of any circuitry other than circuitry which is part of a product of FORCE COMPUTERS GmbH/Inc. • FORCE COMPUTERS does not convey to the purchaser of the product described herein any license under the patent rights of FORCE COMPUTERS GmbH/Inc. nor the rights of others. FORCE COMPUTERS Inc. FORCE COMPUTERS GmbH 3165 Winchester Blvd. Prof.-Messerschmitt-Str. 1 • Campbell, CA 95008-6557 D-8014 Neubiberg/Munich U.S.A. West Germany Phone : (408) 370-6300 Phone : (089) 608 14-0 FAX : (408) 374-1146 Telex : 524190 forc-d FAX : (089) 609 77 93 • FORCE COMPUTERS FRANCE Sarl FORCE Computers UK Ltd. 11, rue Casteja No. 1 Holly Court 92100 Boulogne 3 Tring Road France Wendover Buckinghamshire HP22 6PE England Phone : (1) 4620 37 37 Phone : (0296) 625456 Telex : 206 304 forc-f Telex : 838033 FAX : (1) 4621 35 19 FAX : (0296) 624027 • • • • • This page was intentionally left blank • • • • • Table of Contents • 1.0 General Information 1-1 1.1 Hardware Features of the SYS68K/ISCSI-1 1-3 1.2 The Hardware Functions 1-4 1.2.1 The Local 68010 CPU 1-4 1.2.2 The SCSIbus Interface 1-5 1.2.3 The Floppy Disk Interface 1-6 1.2.4 The PI/T 68230 1-6 • 1.2.5 The Dual Ported RAM 1-7 1.2.6 The VMEbus Interface 1-8 1.2.7 The Bus Interrupter Module 1-8 1.2.8 The Optional Back Panel 1-9 • 2.0 Specification of the SYS68K/ISCSI-1 2-1 3.0 Ordering Information 3-1 • List of Figures Figure 1-1: Photo of the SYS68K/ISCSI-11-2 • • • • • This page was intentionally left blank • • • • • 1.0 General Information • The SYS68K/ISCSI-1 board is a high performance intelligent SCSIbus controller board which fully supports the SCSI standard. Up to four floppy drives can be controlled locally, without using the SCSIbus. The board provides local intelligence with a 68010 CPU, 68450 DMAC, SCSI Bus Controller (SCSIBC) and Floppy Disk Controller (FDC). A 128Kbyte Dual Ported RAM (DPR) is used to store data and to interface the SYS68K/ISCSI-1 board. Highest throughput is guaranteed by using a 10MHz 68450 DMAC and the NCR 5386S SCSIBC. On a single ended SCSIbus, the board works under the powerful firmware (128Kbyte EPROM area) as initiator or as target. The SYS68K/ISCSI-1's own SCSIbus I.D. is software controlled. • Four floppy drives are fully firmware supported, and can also be accessed via the SCSIbus in the target mode. The SYS68K/ISCSI-1 contains a VMEbus Rev.C/IEEE P1014 compatible interface to communicate to the host CPUs via its 128Kbyte DPR. The access address and the Address Modifier code are jumper selectable. A Bus Interrupter Module - BIM 68153 - is installed on the board to support fully asynchronous operation with the 4 different software programmable interrupt request channels. • The firmware of the SYS68K/ISCSI-1 described in the Firmware User's Manual handles all activities to/from the SCSIbus and the floppy interface. For special applications, the source code of the firmware is optionally available. • • • 1-1 /MS I: (I 1 0 0 c 1 .=. 17 7, I _.,.- .._ .7 ,.,:,.,..t.7 •Z" --' ,-...,....., CaCI 10I ° -7'' 0° ,r I. 1 ',' , C / = - CI 1 0 , 0 .-- i 1 15 I 1 :- 1 t C.,c7...--,i,,,., rx.,4 7• CI I'0 0 :.: 05. ',- C1 C1 I,7 __....,....___. CI LO 0 1, 4 - C4 ' I;1 C 1 '' I 1 .. '-',-- LC ;: CI 1O 0 Ii ,) 4 c 1 ' 1 C 1 mz7 ,,:, CI i 0 0 i I .) 1 I c / rx..;-.:_` CI V 0 0 . ! C ! ,:. ,I allill,. e• r. ..• ....-2; a. 42 :H. ' ° 0 i,'...1';.';':".'f.".:T.'.. c,,.E. 861E' ..74F046 8618 .74.64C E513 '.';:.7.:?-3- OA Q-' r:,--3: .7 •r• t- Iz fil .1 OurG IN 8628 G, •• • I) 90NLS02E4 ,7'7 8507 " falarafil/iWiart all.11111111111111.11110 am;'. cn (-) cn 053,8 _•• -0, • CV ,354236 ©NCR/5385E I:373 215fC:1101,.. 6548Y0 C905804 00 -02 3E:0 04065 6-1085057 SrO4C5641-1' 8626A •••• (30.rordc 64351 964425642-10 -J ©NCR 0370 C254161 6-10520/ . .v!ALAYS'A 61EXT PC. 0i474L5052N7 SN741S.441-1N .... .. '714111.111111.1111. Z.Z4'd ISH41111.1111.11111111111111.11111111111111. SYSOOK- ll11:1'1'111.111t111:11111111111.11111'•illIddl PrN • :1 • • • • • • • • ▶jimozwaspierd-19A8 9 • 1.1 Hardware Features of the SYS68K/ISCSI-1 • - 68010 CPU for local control (10MHz) - 68450 DMA Controller for local transfers (10MHz) - Dual Ported 128Kbyte 0 wait state static RAM between the VMEbus and the local CPU - SCSIbus interface built with the NCR 5386S SCSIbus controller. Programmable as an initiator or target - Transfer rate via the SCSIbus up to 1.5Mbyte/s • - SHUGART compatible floppy interface with the WD1772 FDC. Up to 4 floppy drives can be controlled independent of the SCSIbus - All I/O signals available on P2 connector 4 different interrupt request signals to the VMEbus. Each channel contains a software programmable IRQ level (1 to 7) and vector - Local parallel interface for controlling and monitoring board functions • - VMEbus Rev.C/IEEE P1014 compatible interface A24:D16, D8 - Watchdog timer controlling correct functions of on-board hard and software - Status and control LEDs for monitoring local activities - High level handling firmware for communication, selftest, data caching/hashing and control • • 1-3 1.2 The Hardware Functions • The local CPU reacts on the commands and initialisation parameters within the 128Kbyte DPR. Constant program run times are • guaranteed through the special hardware logic providing zero wait state operation from the DPR, independent of the accesses from the VMEbus to the DPR. The SYS68K/ISCSI-1 consists of self-test functions as well as a hardware watchdog timer which controls the activities of the 68010 CPU running with 10MHz. User supplied programs can be loaded into the DPR and executed by the local CPU to adapt and extend board functionality. The local CPU controls the SCSIbus and the floppy disk interface via local interrupts, and communicates to the host CPU via the DPR or via interrupt request to the VMEbus, generated by a Bus Interrupter Module. • The I/O signals to be supported through the NCR 5386S are terminated on the PC board. The terminators can be removed in order to be able to connect more than 3 SCSI devices. 1.2.1 The Local 68010 CPU • A 10MHz 68010 CPU is installed on the SYS68K/ISCSI-1 to control the data traffic between the serial I/O channels and the VMEbus host CPU(s). Two EPROMs with a maximum capacity of 128Kbyte are installed on the SYS68K/ISCSI-1 to hold the handling firmware. Constant zero wait state operation from the EPROM guarantees maximum CPU throughput and a fixed program run time. The 128Kbyte Dual Ported RAM is also accessible without the • insertion of wait states by using a CPU clock synchronized arbitration mechanism. The accesses from the CPU to the DPR are not delayed if a VMEbus access is pending or being executed. A local timer, included in the PI/T, is used to interrupt the CPU for task scheduling, command interpretation and execution. The CPU and all I/O devices can be RESET through a SYSTEM reset via the SYSRESET signal of the VMEbus or by accessing a dedicated location within the DPR reserved for this function. 1-4 • • 1.2.2 The SCSIbus Interface The SYS68K/ISCSI-1 contains an NCR 5386S SCSIbus controller and an • NCR 8310 SCSIbus driver/transceiver. These chips provide the following features: - Support of the ANSI X3T9.2 SCSI standard - Asynchronous data transfer to 1.5Mbyte per second - Support of both initiator and target modes - Parity generation with optional checking - Support of arbitration - Control of all bus signals except RESET • - Doubly-buffered data register - Versatile MPU bus interface - Memory or I/O mapped MPU interface - DMA or programmed I/O transfer • - 24-bit internal transfer counter - Programmable (re)selection timeouts - Interrupt of MPU on all bus conditions requiring service - SCSI pass parity optional with checking - 48mA driver • The NCR 53865 SCSI Bus Controller communicates with the 68010 CPU and the 68450 DMAC as a peripheral device.