Alpha 21164 Microprocessor Data Sheet

Alpha 21164 Microprocessor Data Sheet Order Number: EC–QP98C–TE Revision/Update Information: This is a revised manual. It supersedes the Digital Semiconductor 21164 Alpha Microprocessor Data Sheet (EC–QP98B–TE). Digital Equipment Corporation Maynard, Massachusetts http://www.digital.com/semiconductor/alpha/alpha.htm August 1998 While DIGITAL believes the information included in this publication is correct as of the date of publication, it is subject to change without notice. Digital Equipment Corporation makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication imply the granting of licenses to make, use, or sell equipment or software in accordance with the description. ©Digital Equipment Corporation 1998. All rights reserved. Printed in U.S.A. DIGITAL, DIGITAL Semiconductor, DIGITAL UNIX, OpenVMS, VAX, and the DIGITAL logo are trademarks of Digital Equipment Corporation. GRAFOIL is a registered trademark of Union Carbide Corporation. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Microsoft is a registered trademark and Windows NT is a trademark of Microsoft Corporation. UNIX is a registered trademark in the United States and other countries licensed exclusively through X/Open Company Ltd. All other trademarks and registered trademarks are the property of their respective owners. Contents 1 About This Data Sheet . 1 2 Alpha 21164 Microprocessor Features . 2 3 Microarchitecture . 3 3.1 Instruction Fetch/Decode and Branch Unit . 5 3.1.1 Instruction Prefetch and Decode . 5 3.1.2 Branch Prediction . 5 3.1.3 Instruction Translation Buffer. 5 3.1.4 Interrupts . 6 3.2 Integer Execution Unit. 6 3.3 Floating-Point Execution Unit . 7 3.4 Memory Address Translation Unit. 7 3.4.1 Data Translation Buffer . 8 3.4.2 Miss Address File . 8 3.4.3 Store Execution . 8 3.4.4 Write Buffer . 9 3.5 Cache Control and Bus Interface Unit . 9 3.6 Cache Organization . 9 3.6.1 Data Cache . 9 3.6.2 Instruction Cache. 9 3.6.3 Second-Level Cache . 10 3.6.4 External Cache . 10 3.7 Serial Read-Only Memory Interface . 10 3.8 Pipeline Organization . 10 4 Pinout and Signal Descriptions . 12 4.1 Pin Assignment . 12 4.2 21164 Packaging . 17 4.3 21164 Microprocessor Logic Symbol . 18 4.4 21164 Signal Names and Functions . 20 5 21164 Microprocessor Functional Overview . 35 5.1 Clocks . 36 5.1.1 CPU Clock . 37 5.1.2 System Clock. 37 5.1.3 Reference Clock . 38 5.2 Board-Level Backup Cache Interface . 39 5.2.1 Bcache Victim Buffers . 40 5.2.2 Cache Coherence Protocol . 40 iii 5.3 System Interface . 41 5.3.1 Commands and Addresses . 42 5.4 Interrupts. 44 5.4.1 Interrupt Signals During Initialization . 45 5.4.2 Interrupt Signals During Normal Operation . 46 5.5 Test Modes . 46 5.5.1 Normal Test Interface Mode . 47 5.5.2 Serial ROM Interface Port . 47 5.5.3 Serial Terminal Port . 48 5.5.4 IEEE 1149.1 Test Access Port . 48 5.5.5 Test Status Signals . 48 6 Alpha Architecture Basics . 49 6.1 The Architecture . 49 6.2 Addressing . 50 6.3 Integer Data Types . 50 6.4 Floating-Point Data Types . 51 7 IEEE Floating-Point Conformance . 52 8 Internal Processor Registers . 55 8.1 IDU, MTU, Dcache, and PALtemp IPRs . 55 8.2 External Interface Control (CBU) IPRs . 58 8.3 PALcode Storage Registers . 59 9 PALcode . 60 9.1 PALcode Entry Points . 60 9.1.1 PALcode Trap Entry Points . 61 9.2 Required PALcode Function Codes . 62 9.3 Opcodes Reserved for PALcode . 62 10 Alpha Instruction Summary . 63 10.1 Reserved Opcodes . 70 10.1.1 Opcodes Reserved for DIGITAL . 71 10.1.2 Opcodes Reserved for PALcode . 71 10.2 IEEE Floating-Point Instructions . 72 10.3 VAX Floating-Point Instructions . 74 10.4 Opcode Summary . 75 10.5 Required PALcode Function Codes . 77 11 Electrical Data . 78 11.1 Electrical Characteristics. 78 11.2 DC Characteristics . 79 11.2.1 Power Supply. ..

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