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Logic-Level Countermeasures to Secure FPGA Based Designs Shivam Bhasin

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Logic-Level Countermeasures to Secure FPGA Based Designs Shivam Bhasin Logic-Level Countermeasures to Secure FPGA based Designs Shivam Bhasin To cite this version: Shivam Bhasin. Logic-Level Countermeasures to Secure FPGA based Designs. Cryptography and Security [cs.CR]. Télécom ParisTech, 2011. English. pastel-00683079 HAL Id: pastel-00683079 https://pastel.archives-ouvertes.fr/pastel-00683079 Submitted on 27 Mar 2012 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. EDITE - ED 130 Doctorat ParisTech THÈSE pour obtenir le grade de docteur délivré par TELECOM ParisTech Spécialité « Électronique et Communication » présentée et soutenue publiquement par Shivam BHASIN le 14 Décembre 2011 Contremesures au niveau logique pour sécuriser les architectures de crypto-processeurs dans un FPGA Directeur de thèse : Jean-Luc DANGER Co-encadrement de la thèse : Tarik GRABA Jury M. François-Xavier STANDAERT, Professeur, UCL, Belgique Président M. Viktor FISCHER, Professeur, ENSM SE, France Rapporteur Mme. Ingrid VERBAUWHEDE, Professeur, KUL, Belgique Rapporteur M. Habib MEHREZ, Professeur, UPMC, France Examinateur M. Patrick SCHAUMONT, Professeur, Virginia Tech, Etats-Unis Examinateur M. Sylvain GUILLEY, Maitre de Conferences Associé, Télécom ParisTech, France Examinateur TELECOM ParisTech école de l’Institut Télécom - membre de ParisTech Abstract Modern field programmable gate arrays (FPGA) are capable of implementing complex system on chip (SoC) and providing high performance. Therefore, FP- GAs are finding wide application. A complex SoC generally contains embedded cryptographic cores to encrypt/decrypt data to ensure security. These crypto- graphic cores are computationally secure but their physical implementations can be compromised using side channel attacks (SCA) or fault attacks (FA). This thesis focuses on countermeasures for securing cryptographic cores on FPGAs. First, a register-transfer level countermeasure called “Unrolling” is proposed. This hiding countermeasure executes multiple rounds of a cryptographic al- gorithm per clock which allows deeper diffusion of data. Results show excel- lent resistance against SCA. This is followed by dual-rail precharge logic (DPL) based countermeasures, which form a major part of this work. Wave dynamic differential logic (WDDL), a commonly used DPL countermeasure well suited for FPGAs is studied. Analysis of WDDL (DPL in general) against FA revealed that it is resistant against a majority of faults. Therefore, if flaws in DPL namely early propagation effect (EPE) and technological imbalance are fixed, DPL can evolve as a common countermeasure against SCA and FA. Continuing on this line of research we propose two new countermeasures: DPL without EPE and Balanced-Cell based DPL (BCDL). Finally advanced evaluation tools like stochastic model, mutual information and combined attacks are discussed which are useful when analyzing counter- measures. Dedicated to my family, for their unconditional love and support. Acknowledgements This PhD has been performed in the auspices of group SEN (Systèmes Élec- tronique Numérique) of Department COMELEC (Communications & Électron- ique) of Telecom-ParisTech. During these three years of graduate studies, I have learned the essence of research and development. This has been possible by working and interacting with a group of very intelligent, resourceful and kind personalities. Surely without them, my stay in Telecom-ParisTech would not be as fruitful. First and foremost,I extend my utmost thankfulness to my PhD director, Profes- sor Jean-Luc Danger for his guidance and encouragement. His experience and expertise in the subject are matchless. Having a highly diverse knowledge base, his suggestions were of immense importance. He was of great help in getting out of many complex circumstances. I would like to express my most sincere gratitude to Dr. Sylvain Guilley, who showed confidence in me and gave me numerous advice in academics, research and career. He is a person of great scientific acumen and admirable human values. He was by my side throughout the three years and taught me how to find paths in the dark alleys of research. I am extremely thankful to my Co-adviser, Dr. Tarik Graba, for his guidance through various lengthy and productive discussions on the subject. His pro- found knowledge and extensive experience along with his helping nature proved to be a treasure for me. I take great pride in having worked with these three gentlemen, who are the specialists in the domain of Cryptography and Security. I have learned a lot from them. I am also thankful to Professor Francois-Xavier Standaert for accepting me as an intern in his team at UCL, Belgium for a period of three months. His profound knowledge in the feild of side-channel analysis helped me learn a lot and widen my research perspectives. v I am extremely grateful to the members of my jury who gave their consent to analyze and consequently validate my work. I feel honored that my work got approved by such well renowned specialists. The moments spent with many peers is perhaps one of the best memories that I will take with me of my graduate studies. I cherish all the moments of stress and joy spent with my collegues Nidhal, Olive (Olivier), Joe (Youssef), Fhal (Houssem), Max (Maxime), Taufeek, Seb (Sebastian), Zizou (Aziz), Zouha, Nicholas, Amel, Florent, Chantal, Daniel, Zouina and Laurent. I specially admire the efforts of Olivier which he took to teach me french. I have very much enjoyed being in the company of friends like Babu (Sumanta), Shady (Chadi), Mirani (Farhan), Hasham, Mayassa, Marcel, Paulo, Francesco, Lauriane, Nora, Davi, Gutemberg, Khalil, Waqqas, Sami, Tushar, Arif and the list goes on and on. The various ecsapades in Paris with Shady (Chadi), Babu (Sumanta), Hasham and Mirani (Farhan) goes into my ROM. I am most fortunate to have my family: my parents, my grandmother and sister. Their constant encouragement has pushed me to be the best that I can be. I am certain that this work has been a product of my family’s love and support throughout my life. Last but not the least I am thankful to The French National Research Agency (ANR), who financed this thesis through the ANR-07-ARFU-010 grant “SeFPGA” (Secured Embedded FPGAs). I would also like to thank the DGA project “Rapid BCDL” for its support. vi Contents Abstract iii List of Figures xi List of Tables xv Glossary xvii Résumé Français xix 1 Introduction 1 1.1 Motivation . .1 1.2 Organization . .2 1.3 Contributions . .4 2 General Background5 2.1 Modern Cryptography . .6 2.2 Symmetric Key Cryptography . .7 2.2.1 Data Encryption Standard . .9 2.2.2 Advanced Encryption Standard . 10 2.3 Public-Key Cryptography . 12 2.3.1 RSA......................................... 13 2.3.2 Elliptic Curve Cryptography . 13 2.4 Physical Cryptanalysis . 14 2.4.1 Fault Attacks . 15 2.4.2 Side Channel Attacks . 18 2.5 Side Channel Attack Model & Distinguisher . 20 2.5.1 Leakage Model . 20 2.5.2 Simple Power Analysis . 21 2.5.3 Differential Power Analysis . 22 vii CONTENTS 2.5.4 Correlation Power Analysis . 22 2.5.5 Mutual Information Analysis . 23 2.6 Need for Countermeasures . 24 2.6.1 Countermeasures against FA . 25 2.6.2 Countermeasures against SCA . 29 2.7 Field Programmable Gate Arrays . 33 2.7.1 Generic FPGA Design Flow . 35 3 Protecting Cryptographic Circuits at the RTL Level 37 3.1 Protecting Cryptographic Implementations at the Component Level . 38 3.1.1 AES Co-processor . 38 3.1.2 Experimental setup and data acquisition . 41 3.1.3 Cost Comparison of the Three AES Architectures . 43 3.1.4 Security Evaluation of the Three AES Architectures against SCA . 44 3.1.5 Security Evaluation of the Three AES Architectures against FA . 44 3.1.6 Discussion . 50 3.2 Unrolling Cryptographic Circuits as a Countermeasure . 51 3.2.1 Rationale of the Countermeasure . 51 3.2.2 Fully unrolled DES implementation on ASIC . 53 3.2.3 Security Evaluation of the Proposed Countermeasure . 56 3.2.4 Attack on the Unrolled DES . 59 3.2.5 Evaluation Based on Mutual Information Metric . 62 3.3 Conclusions . 63 4 DPL Countermeasures for FPGA 65 4.1 Dual-Rail with Precharge Logic . 66 4.1.1 Dual-Rail with Precharge Logic Protocol . 66 4.1.2 DPL Flaw: Early Propagation Effect . 67 4.1.3 DPL Flaw: Technological Imbalance . 69 4.2 Wave Dynamic Differential Logic . 69 4.2.1 Basic theory of WDDL . 69 4.2.2 Design Flow for WDDL Implementation on FPGA . 71 4.2.3 WDDL Implementation and Synthesis Results . 72 4.3 Security Evaluation of WDDL against SCA . 74 4.4 Security Evaluation of WDDL against FA . 74 4.4.1 Experimental Results . 75 viii CONTENTS 4.4.2 Theoretical Fault Analysis . 78 4.5 DPL: State of the Art . 85 4.5.1 WDDL Variants . 86 4.5.2 SDDL . 90 4.5.3 Partial DDL . 91 4.5.4 MDPL . 92 4.5.5 DRSL . 92 4.5.6 STTL . 96 4.5.7 DPL styles Comparison . 96 4.6 Security Evaluation of DPL against FA . 98 4.6.1 Fault Model . 98 4.6.2 Faults Transformation . 99 4.6.3 Propagation of NULL Values Through Substitution Boxes . 101 4.6.4 Analysis of the FA Protection of DPL . 101 4.6.5 Low-cost countermeasure against setup time violation attacks . 105 4.7 Conclusions . 106 5 Novel DPL countermeasures for FPGA 109 5.1 DPL without Early Propagation Effect (DPL w/o EPE) .
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