An Experimental Comparison of Galvanically Isolated DC-DC Converters: Isolation Technology and Integration Approach

electronics

Article An Experimental Comparison of Galvanically Isolated DC-DC Converters: Isolation Technology and Integration Approach

Egidio Ragonese 1,* , Nunzio Spina 2, Alessandro Parisi 2 and Giuseppe Palmisano 1

1 Dipartimento di Ingegneria Elettrica Elettronica e Informatica (DIEEI), University of Catania, 95125 Catania, Italy; [email protected] 2 STMicroelectronics, 95121 Catania, Italy; [email protected] (N.S.); [email protected] (A.P.) * Correspondence: [email protected]; Tel.: +39-095-738-2331

Abstract: This paper reviews state-of-the-art approaches for galvanically isolated DC-DC converters based on radio frequency (RF) micro-transformer coupling. Isolation technology, integration level and fabrication issues are analyzed to highlight the pros and cons of fully integrated (i.e., two chips) and multichip systems-in-package (SiP) implementations. Speciﬁcally, two different basic isolation technologies are compared, which exploit thick-oxide integrated and polyimide standalone transformers, respectively. To this aim, previously available results achieved on a fully integrated isolation technology (i.e., thick-oxide integrated transformer) are compared with the experimental performance of a DC-DC converter for 20-V gate driver applications, speciﬁcally designed and implemented by exploiting a stand-alone polyimide transformer. The comparison highlights that

similar performance in terms of power efﬁciency can be achieved at lower output power levels (i.e., about 200 mW), while the fully integrated approach is more effective at higher power levels

Citation: Ragonese, E.; Spina, N.; with a better power density. On the other hand, the stand-alone polyimide transformer approach Parisi, A.; Palmisano, G. An allows higher technology ﬂexibility for the active circuitry while being less expensive and suitable Experimental Comparison of for reinforced isolation. Galvanically Isolated DC-DC Converters: Isolation Technology and Keywords: basic isolation; electromagnetic coupling; gate drivers; integrated circuits; polyimide; Integration Approach. Electronics rectiﬁers; reinforced isolation; Schottky diode; silicon dioxide; system in package; transformers 2021, 10, 1186. https://doi.org/ 10.3390/electronics10101186

Academic Editor: Raed 1. Introduction A. Abd-Alhameed Safety rules for equipment operated by human beings, along with severe reliability requirements for electronics in harsh environments, call for galvanic isolation in several Received: 21 April 2021 application ﬁelds, even at very low power levels, as summarized in Figure1a [ 1]. A Accepted: 14 May 2021 Published: 15 May 2021 typical galvanically isolated system is shown in Figure1b [ 1]. It consists of two isolated domains (i.e., with different isolated ground references) that exchange data signals across

Publisher’s Note: MDPI stays neutral the galvanic barrier. However, full isolation is provided only if the power supply of Domain with regard to jurisdictional claims in 2, VDD2, is provided from the power supply of Domain 1, VDD1, by means of a galvanically published maps and institutional afﬁl- isolated DC-DC converter. Usually, power levels from a few tens of mW to about 1 W iations. can be transferred across the galvanic barrier by means of magnetic coupling. To this aim, micro-transformer devices are currently used, which exploit a dielectric layer between two stacked spiral windings to withstand an isolation voltage of several kilovolts [2,3]. Typically, by using one galvanic barrier (i.e., one transformer), the basic isolation level can be achieved (i.e., about 5–6 kV). Reinforced isolation, which is the highest level of isolation, Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland. requires the use of two galvanic barriers connected in series (i.e., double isolation) in order This article is an open access article to comply with the 10-kV surge test of the VDE 0884-11 standard [4]. Double isolation distributed under the terms and for a power transfer has been demonstrated by using an LC hybrid approach (i.e., an conditions of the Creative Commons isolation capacitor and an isolation transformer in a resonant mode operation), which Attribution (CC BY) license (https:// boosts efﬁciency with respect to a traditional two-series-connected scheme [5]. However, creativecommons.org/licenses/by/ less costly solutions for reinforced isolation rely on one galvanic barrier by means of an 4.0/). isolation transformer with increased thickness for the dielectric layer [6,7].

Electronics 2021, 10, 1186. https://doi.org/10.3390/electronics10101186 https://www.mdpi.com/journal/electronics Electronics 2021, 10, 1186 2 of 12

However, less costly solutions for reinforced isolation rely on one galvanic barrier by Electronics 2021, 10, 1186 means of an isolation transformer with increased thickness for the dielectric layer [6,7]. 2 of 12 This paper reviews commonly used transformer-based technologies for galvanically isolated DC-DC conversion, which are based on fully integrated thick-oxide transformers [8,9] and post-processed stand-alone polyamide transformers [7,10,11], respectively. To thisHowev aim, isolationer, less technologies costly solutions are compared for by reinforced means of previously isolation available rely re onsults one and galvanic barrier by newmeans experimental of an isolation data of a DC transformer-DC converter with specifically increased designed thickness and implemented. for the Thedielectric layer [6,7]. comparison is carried out at a similar isolation rating (i.e., 5 kV) in terms of electrical per- formanceThis (i.e., paper isolated reviews output power commonly and efficiency), used transformer integration level,-based design technologies flexibility for galvanically andisolated fabrication DC costs-DC in conversion, order to highlight which the prosare basedand cons on of fullythe two integrated approaches. thick -oxide transformers [8,9The] and paper post is organized-processed as follows. stand -Sectionalone 2polyamide describes the transformerssystem architecture [7,10,11] and , respectively. To main circuit topologies for galvanically isolated DC-DC converters, while the characteris- ticsthis of theaim, two isolation isolation technologies under are comparison compared are by detailed means in of Section previously 3. Section available results and 4 newpresents experimental the design and data experimental of a DC performance-DC converter of a 5 -specificallykV 200-mW DC designed-DC converter and implemented. The Electronics 2021, 10, 1186 forcomparison gate drivers, alongis carried with a out wide at comparison a similar between isolation the ratingintegration (i.e., technologies 5 kV) in termsfor2 of 12 of electrical per- powerformance transfer (i.e., applications. isolated output power and efficiency), integration level, design flexibility and fabrication costs in order to highlight the pros and cons of the two approaches. The paper is organized as follows. Section 2 describes the system architecture and main circuit topologies for galvanically isolated DC-DC converters, while the characteristics of the two isolation technologies under comparison are detailed in Section 3. Section 4 presents the design and experimental performance of a 5-kV 200-mW DC-DC converter for gate drivers, along with a wide comparison between the integration technologies for power transfer applications.

(a) (b)

FigureFigure 1. 1. (a)( aGalvanic) Galvanic isolation isolation application application fields; ﬁelds; (b) simplified (b) simpliﬁed block diagram block diagram of a galvanically of a galvanically isolatedisolated system. system. Reproduced Reproduced from from [1]. Copyright [1]. Copyright 2019, Springer 2019, Springer Nature NatureCustomer Customer Service Centre Service Cen- GmbH. tre GmbH.

2. GalvanicallyThis paper Isolated reviews DC commonly-DC Conversion used transformer-based: System and Circuit technologies Description for galvanically isolatedA galvanically DC-DC conversion, isolated DC which-DC converter are based requires on fully a transformer integrated-based thick-oxide power link transform- to exploiters [8, 9the] and magnetic post-processed coupling between stand-alone two polyamideisolated windings transformers, according [7,10 to,11 the], respectively.general schemeTo this in aim, Figure isolation 2. When technologies isolated power are compared regulation by is means required, of previously a further isolated available data results linkand (not new represented experimental in Figure data of 2) a must DC-DC be converterincluded for specifically the feedback designed control, and which implemented. typi- callyThe comparisonuses a pulse- iswidth carried modula out attion a similar(PMW) isolationapproach rating [9]. In (i.e., common 5 kV) implementations in terms of electrical (seeperformance Figure 2), (i.e.,the DC isolated-AC conversion output power is performed and efficiency), by a radio integration frequency level, (RF) power design oscil- flexibility (a) (b) lator,and fabricationwhile a diode costs rectifier in order is used to highlight for the AC the-DC pros conversion and cons of the twoisolated approaches. voltage at the secondaryThe paper winding. is organized The isolation as follows. transformer Section can2 describes be also used the systemfor the voltage architecture step- and up,Figure as required 1. (a) byGalvanic gate driver isolation applications, application typically fields; operated (b) simplifiedat about 20 V.block diagram of a galvanically mainisolated circuit system. topologies Reproduced for galvanically from isolated[1]. Copyright DC-DC converters,2019, Springer while Nature the characteristics Customer Service Centre of the two isolation technologies under comparison are detailed in Section3. Section4 GmbH. presents the design and experimental performance of a 5-kV 200-mW DC-DC converter for gate drivers, along with a wide comparison between the integration technologies for power2. Galvanically transfer applications. Isolated DC-DC Conversion: System and Circuit Description A galvanically isolated DC-DC converter requires a transformer-based power link to 2. Galvanically Isolated DC-DC Conversion: System and Circuit Description exploit the magnetic coupling between two isolated windings, according to the general A galvanically isolated DC-DC converter requires a transformer-based power link to exploitscheme the in magnetic Figurecoupling 2. When between isolated two power isolated regulation windings, according is required, to the a general further isolated data schemelink (not in Figure represented2. When isolated in Figure power 2) regulation must be is included required, afor further the isolatedfeedback data control, link which typi-

(notcally represented uses a pulse in Figure-width2) must modula be includedtion (PMW) for the feedbackapproach control, [9]. In which common typically implementations Figure 2. Galvanically isolated DC-DC converter scheme and power efficiency expression, η. uses(see a Figure pulse-width 2), the modulation DC-AC conversion (PMW) approach is performed [9]. In common by a implementationsradio frequency (see (RF) power oscil- Figure2), the DC-AC conversion is performed by a radio frequency (RF) power oscillator, whilelator, a while diode rectiﬁera diode is rectifier used for theis used AC-DC for conversion the AC-DC of the conversion isolated voltage of the at isolated the voltage at secondarythe secondary winding. winding. The isolation The transformer isolation cantransformer be also used can for thebe voltagealso used step-up, for asthe voltage step- requiredup, as required by gate driver by gate applications, driver typicallyapplications, operated typically at about operated 20 V. at about 20 V.

FigureFigure 2. 2.Galvanically Galvanically isolated isolated DC-DC DC converter-DC converter scheme and scheme power efﬁciencyand power expression, efficiencyη. expression, η.

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The crucial performance of an isolated power link is its power efficiency, η. Indeed, it limits the maximum reliable output power due to thermal dissipation issues. The overall efficiency of the isolated power link is mainly determined by the product of the efficiencies of the three main building blocks (i.e., ηOSC, ηTRASF and ηRECT). Therefore, it is mandatory to maximize each contribution to obtain a significant DC-DC performance. As far as the power oscillator is concerned, transformer-loaded implementations are straightforward, as the primary winding can be easily used for the LC tank. On the other hand, transistor availability in the adopted integration technology drives the choice of the circuit topology. The main oscillator topologies for the DC-AC conversion are shown in Figure3. The most efficient solution is the D-class oscillator with cross-coupled transistors working as power switches (Figure3a), which boosts the drain voltages above the supply voltage, VDD [12,13]. Unfortunately, this solution requires the cross-coupled pair to be implemented with special transistors with very high breakdown for drain voltage, such as the laterally diffused transistors (LDMOS) that are usually integrated into the bipolar-CMOS-DMOS (BCD) technologies [14,15]. In this topology, capacitors CB are used to perform a voltage partition with the gate capacitance of M1,2, thus properly setting the VGS peak to prevent gate-oxide breakdown. If only standard MOS devices are available, as in a CMOS process, the traditional complementary cross-coupled oscillator shown in Figure3b is an option. It maximizes the oscillation amplitude within the supply voltage, thus avoiding the risk of transistor breakdown while giving the advantage of nearly doubled transconductance at the same current level compared with a simple cross-coupled oscillator. Circuit topologies in Figure3c,d are enhanced versions of the traditional complementary cross-coupled oscillator [16]. They take advantage of current-reuse (CR) and power, combining techniques to improve both output power and efficiency. On the other hand, they require three- winding isolation transformers with a more complex configuration compared to the other circuit topologies. Proper operation of such oscillators requires frequency synchronization at the primary windings, which can be obtained either with a pure inductive (Figure3c) [17] Electronics 2021, 10, 1186 4 of 12 or hybrid coupling (i.e., inductive and capacitive as in Figure3d) between the p-MOS and n-MOS cross-coupled pairs [18].

FigureFigure 3. 3.Power Power oscillator oscillator topologiestopologies for for DC DC-AC-AC conversion: conversion: (a) (Da)-classD-class oscillator; oscillator; (b) complementary (b) complementary cross-coupled cross-coupled os- oscillator;cillator; (c) inductivelyinductively coupled coupled CR CR oscillators oscillators;; (d ()d hybrid) hybrid-coupled-coupled CR CR oscillator. oscillator.

Typical isolation transformer configurations for an isolated power link are reported in Figure4. A traditional stacked transformer with a high turn ratio for voltage step-up is shown in Figure4a, which is well suited for gate-driver applications. A three-winding transformer can be implemented by means of an interleaved configuration (Figure4b) for both CR oscillator topologies, while a tapped winding arrangement (Figure4c) is only compatible with the hybrid coupling one. Due to the three-winding transformer structure, a small voltage step-up can be performed, and therefore, both current-reuse oscillator topologies are suitable for low-/medium-voltage applications. Transformer efficiency,

ηTRASF, is the very bottleneck of the overall system. It is related to both series and parallel Figure 4. Three-dimensional (3D) views of isolation transformer configurations for DC-DC conversion. (a) Stacked topology; (b) three-winding interleaved transformer; (c) three-winding tapped transformer. Reproduced from [19]. Copyright 2018, Elsevier.

(*) threshold compensation

Figure 5. Building block topology selection for galvanically isolated DC-DC converters.

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losses taking place in the metal windings and substrate, respectively [19]. Therefore, it is of utmost importance to use thick conductive layers (i.e., copper or gold), as well as fabricating the transformer on a low-conductivity substrate (<104 S/m). A crucial role is also played by the magnetic coupling coefficient, k, between the primary and secondary windings. It is inversely related to the isolation layer thickness and then to the maximum isolation rating of the transformer. The AC-DC conversion is performed by means of a full-wave rectifier. A traditional bridge configuration is preferred for high-voltage applications (i.e., VOUT > 8–10 V)[13,17,18,20], where the diode threshold losses can be tolerated. Alternatively, a simple full-wave rectifier is preferred at the cost of including a center tap connection also for the secondary winding of the isolated transformer [7]. Schottky diodes are mandatory to achieve a rectifier efficiency above 80% while enabling operation in the VHF band. If the adopted technology does not include Schottky diodes, the rectifier can be also implemented by using diode-connected transistors, especially at Figure 3. Power oscillator topologies for DC-AC conversion: (a) D-class oscillator; (b) complementary cross-coupled oscillator; (c) inductively coupledlower outputCR oscillators voltages,; (d) hybrid also-coupled including CR oscillator. a threshold compensation scheme [2,5,9]. Figure 3. Power oscillator topologies for DC-AC conversion: (a) D-class oscillator; (b) complementary cross-coupled oscillator; (c) inductively coupled CR oscillators; (d) hybrid-coupled CR oscillator.

FigureFigure 4. Three-dimensional 4. Three-dimensional (3D) (3D views) views of isolationof isolation transformer transformer conﬁgurations configurations for for DC DC-DC-DC conversion. conversion. (a) (Satacked) Stacked topol- topology; ogy; (b) three-winding interleaved transformer; (c) three-winding tapped transformer. Reproduced from [19]. Copyright (b) three-winding interleaved transformer; (c) three-winding tapped transformer. Reproduced from [19]. Copyright 2018, 2018, Elsevier. Elsevier. Figure 4. Three-dimensional (3D) views of isolation transformer configurations for DC-DC conversion. (a) Stacked topology; (b) three-winding interleavedFigure transformer;5 can be (c used) three to-winding drive the tapped topology transformer. selection Rep forroduced the three from building [19]. Copyright blocks of a 2018, Elsevier. galvanically isolated DC-DC converter.

(*) threshold compensation

Figure 5. Building block topology selection for galvanically isolated DC-DC converters.

(*) threshold compensation

Figure 5. Building block topology selection for galvanically isolated DC-DCDC-DC converters.

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3. Isolation Technology A crucial role in the performance of a galvanically isolated DC-DC converter is played by the isolation transformer, whose characteristics affect system power efﬁciency and maximum isolation rating, as well as the integration level and overall costs. Basically, there are two different approaches that are discussed in the following subsections.

3.1. Integrated Isolation Transformers The first isolation approach adopts integrated transformers (i.e., integrated along with the active circuitry) exploiting a dedicated back end of line (BEOL) with thick silicon dioxide (SiO2), whose simplified cross-section is shown in Figure6a. This approach has several important advantages. It enables the highest possible integration level, i.e., two chips per isolated physical channel. Indeed, the isolation transformer can be embedded into the first die by exploiting the on-chip direct connection between the oscillator drains and the transformer primary winding, while the second die hosting the rectifier is connected to the isolated secondary winding through bonding wires, as represented in Figure7a. Moreover, thanks to the high dielectric strength of silicon dioxide (i.e., about 1000 V/µm), basic isolation can be achieved by using sufficiently close stacked windings, thus keeping Electronics 2021, 10, 1186 the magnetic coupling coefficient, k, quite high. On the other hand, metal layers6 with of 12 limited thickness, t (about 3 µm for the top metals), must be used to comply with the integration process, while very close spacing, s, between winding turns (usually equal to t) can be exploited to increase both the inductance-to-area ratio and Q-factors, as well. A transformer.performance This limitation produces of additional an integrated off transformer-chip parasitics is its into isolation the main capability, LC tank as severe of the powerreliability oscillator issues and (i.e., involves wafer mechanicalthe codesign stress with and the second-order isolation transformer breakdown in effects) comparison occur withwhen the fully the oxide integrated thickness approach overcomes [13]. approximately On the other 10hand,µm, the which standalone corresponds transformer to basic technologyisolation provides levels (i.e., better 5–6 kV).flexibility However, in terms the most of isolation limiting rating drawback, as the of polyimide this approach thick- is nessthe between need for the a transformer low-conductivity windings substrate can be (typically tuned to lower guarantee than 10different S/m) to isolation hinder thelev- els (fromenergy basic losses to duereinforced to the magneticallyone) without inducedsignificant eddy modifications currents [19 of], whichthe other calls two for chips RF- (i.e.,oriented Chips A technologies, and B in Figure such as 7b). CMOS Another or BiCMOS. advantage As previously relies on outlinedthe complete in Section freedom2, BCD to fabricatetechnologies Chips A are and widely B, whose used technologies for high-voltage can applications be chosen without (such as any isolated constraints gate driver from the interfaces),isolation transformer. also thanks to A the final availability consideration of LDMOS is the devices overall for cost efficient of theD galvanically-class oscillators. iso- 4 latedTypically, DC-DC BCD converter. platforms It is are the built result on aof very a combination high conductive of silicon substrate and (i.e., package about costs 10 S/m) and drivesto hinder the choice latch-up between phenomena. silicon integrated Such a substrate or standalone is not compatible transformers. with anTypically, acceptable be- efficiency for the isolation transformer. For these reasons, the fully integrated isolation cause silicon area consumption of on-chip transformers prevails in the overall area of die approach can be used only with special BCD technologies, which exploit a silicon-on- A, the three-chip approach is cheaper than the two-chip approach, thanks to the lower oxide-insulation (SOI) substrate (see Figure6a) with a consequent increase in cost by costabout of the 30%. standalone isolation die.

(a) (b)

FigureFigure 6. Isolation 6. Isolation technology technology comparison: comparison: (a ()a thick) thick-oxide-oxide technology; technology; ( (bb)) polyimide technology.technology.

(a)

POLYIMIDE

4. Experimental Comparison The comparison between the isolation approaches described in Section 3 is carried out by taking advantage of two different technologies by STMicroelectronics, which are based on fully integrated thick-oxide and standalone polyimide transformers, respectively. Figure 8 depicts the scanning electron microscope (SEM) cross-section for both isolation technologies. The thick-oxide technology in Figure 8a is available on 0.35 µm BCD

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transformer. This produces additional off-chip parasitics into the main LC tank of the power oscillator and involves the codesign with the isolation transformer in comparison with the fully integrated approach [13]. On the other hand, the standalone transformer technology provides better flexibility in terms of isolation rating, as the polyimide thickness between the transformer windings can be tuned to guarantee different isolation levels (from basic to reinforced one) without significant modifications of the other two chips (i.e., Chips A and B in Figure 7b). Another advantage relies on the complete freedom to fabricate Chips A and B, whose technologies can be chosen without any constraints from the isolation transformer. A final consideration is the overall cost of the galvanically isolated DC-DC converter. It is the result of a combination of silicon and package costs and drives the choice between silicon integrated or standalone transformers. Typically, because silicon area consumption of on-chip transformers prevails in the overall area of die A, the three-chip approach is cheaper than the two-chip approach, thanks to the lower cost of the standalone isolation die.

Electronics 2021, 10, 1186 (a) (b) 6 of 12 Figure 6. Isolation technology comparison: (a) thick-oxide technology; (b) polyimide technology.

(a)

POLYIMIDE

(b) Figure 7. SiP Figureimplementation 7. SiP implementation approaches: approaches: (a) integrated (a) integrated transformer; transformer; (b) standalone (b) standalone isolation isolation transformer. transformer.Reproduced Reproduced from [19]. from Copyright [19]. Copyright 2018, 2018,Elsevier. Elsevier. 3.2. Stand-Alone Isolation Transformers 4. Experimental Comparison An alternative isolation technology uses a standalone transformer implemented in The comparisona third die bybetween using low-cost the isolation fabrication, approaches as shown in described Figure6b. Typically,in Section the 3 adopted is carried out by takingdielectric advantage is a polyimide of two thatdifferent has been technologies traditionally by used STMicroelectronics, in the semiconductor industrywhich are for stress relief. It has a lower dielectric strength compared with silicon dioxide (i.e., about based on fully integrated thick-oxide and standalone polyimide transformers, respec- 250 V/µm), and thus thicker insulation is required to withstand the same isolation voltage. tively. FigureConsequently, 8 depicts the polyimide scanning transformers electron microscope have a lower magnetic(SEM) cross coupling-section coefficient for both than isolation technologies.silicon oxide The transformers thick-oxide at thetechnology same isolation in Figure rating. 8a Because is available no constraints on 0.35 are µm given BCD by active device integration, both substrate and BEOL can be properly chosen to improve winding Q-factors and hence transformer transfer efficiency. To this aim, a low-conductivity substrate and thick Au metals are exploited. However, the use of thick metals could affect the minimum spacing, s, between winding turns, thus limiting both inductance-to-area ratio and Q-factors. The most limiting drawback of this approach is the reduction of the integration level, as three chips are required to implement a single isolated physical channel, as shown in Figure7b. Specifically, bonding wires are also used to connect the power oscillator drains to the primary (upper) winding of the isolation transformer. This produces additional off-chip parasitics into the main LC tank of the power oscillator and involves the codesign with the isolation transformer in comparison with the fully integrated approach [13]. On the other hand, the standalone transformer technology provides better flexibility in terms of isolation rating, as the polyimide thickness between the transformer windings can be tuned to guarantee different isolation levels (from basic to reinforced one) without significant modifications of the other two chips (i.e., Chips A and B in Figure7b ). Another advantage relies on the complete freedom to fabricate Chips A and B, whose technologies can be chosen without any constraints from the isolation transformer. A final consideration is the overall cost of the galvanically isolated DC-DC converter. It is the result of a combination of silicon and package costs and drives the choice between silicon integrated or standalone transformers. Typically, because silicon area consumption of on- chip transformers prevails in the overall area of die A, the three-chip approach is cheaper than the two-chip approach, thanks to the lower cost of the standalone isolation die. Electronics 2021, 10, 1186 7 of 12

4. Experimental Comparison The comparison between the isolation approaches described in Section3 is carried

Electronics 2021, 10, 1186 out by taking advantage of two different technologies by STMicroelectronics, which7 of are12 based on fully integrated thick-oxide and standalone polyimide transformers, respectively. Figure8 depicts the scanning electron microscope (SEM) cross-section for both isolation technologies. The thick-oxide technology in Figure8a is available on 0.35 µm platformsBCD platforms (with (withan SOI an option SOI option for power for power transfer transfer applications). applications). The Thetransformer transformer can canbe integratedbe integrated on C onhip Chip A along A along with with the the oscillator oscillator active active core core (see (see Figure Figure 7a).7a). An An i isolationsolation ratingrating of of 5 5 kV kV is is guaranteed guaranteed by by the the oxide oxide layer layer between between a a Cu Cu-thick-thick metal metal (Metal (Metal 4 4)) and and an an AlAl-thin-thin metal metal (Metal (Metal 3 3)) (i.e., (i.e., 3.7 3.7 and and 0.9 0.9 µm,µm, respectively) respectively) [ [88,13,13].]. A A 6 6-kV-kV isolation isolation level level is is achievedachieved by by using using the the oxide oxide layer layer between between M Metalsetals 3 3 and and 2 2 [9 [9].]. Several Several experimental experimental results results areare already already available available on on this this isolation isolation technology, technology, which which can can be be used used for for the the proposed proposed comparison.comparison. The The polyimide polyimide technology technology in Figure in Figure 8b 8isb used is used to fabricate to fabricate a stand a stand-alone-alone isolationisolation transformer transformer (i.e., (i.e., Chip Chip T in T inFigure Figure 7b).7b). AA full full Au Au metal metal back back-end-end is is preferred preferred to minimizeminimize the the winding winding series series resistances. resistances. Specifically, Speciﬁcally, two two upper upper 5 5--µmµm thick thick metals metals are are usedused for for the the primary primary and and secondary secondary windings, windings, while while a a 3 3--µmµm metal metal (Metal (Metal 1 1)) is is exploited exploited forfor the the underpasses. underpasses. High High resistivity resistivity subs substratetrate is is adopted adopted to to minimize minimize losses losses due due to to both both magneticallymagnetically induced induced and and vertical vertical displacement displacement currents currents without without using using any any shielding shielding structurestructure requiring requiring additional additional masks masks and and higher higher manufacturing manufacturing costs costs [ [2121].]. The The polyimide polyimide transformertransformer technology technology withstands withstands ba basicsic to to reinforced reinforced isolation isolation voltages voltages (i.e., (i.e., 5 5 to to 10 10 kV) kV),, thanksthanks to to a a variable variable insulator insulator thickness thickness (from (from 20 20 to to more more than than 30 30 µm)µm) that that is is obtained obtained by by severalseveral deposition deposition steps. steps. The The m mainain parameters parameters for for the the polyimide polyimide isolation isolation technology technology are are summarizedsummarized in in Table Table 11..

(a) (b)

FigureFigure 8. 8. IsolationIsolation technology technology SEM: SEM: (a) ( athick) thick-oxide-oxide technology. technology. Reproduced Reproduced from from [9]. [9Copyright]. Copyright 2018,2018, IEEE IEEE;; (b (b) )polyimide polyimide technology. technology. Reproduced Reproduced from from [7]. [7]. Copy Copyrightright 2020, 2020, IEEE. IEEE.

Table 1. Main process stack parameters for polyimide isolation technology. Table 1. Main process stack parameters for polyimide isolation technology.

Layer Permittivity, εR Loss Tangent Conductivity S/m Layer Permittivity, εR Loss Tangent Conductivity S/m Metals - - 3.8 × 107 Metals - - × 7 Polyimide 3 <0.01 3.8 - 10 Polyimide 3 <0.01 - SiliconSilicon substrate substrate 11.711.7 - 0.6 0.6

By exploiting the stand-alone polyimide transformer approach, a galvanically iso- By exploiting the stand-alone polyimide transformer approach, a galvanically isolated lated DC-DC converter for gate driver applications was specifically designed and charac- DC-DC converter for gate driver applications was speciﬁcally designed and characterized terized for an extensive comparison with the fully integrated thick-oxide technology. For for an extensive comparison with the fully integrated thick-oxide technology. For a fair a fair comparison, the basic isolation option was chosen. A three-chip architecture (as de- comparison, the basic isolation option was chosen. A three-chip architecture (as depicted picted in Figure 7b) was used to convert the 5-V voltage supply, VDD, to a 20-V output in Figure7b) was used to convert the 5-V voltage supply, VDD, to a 20-V output voltage, voltage, VOUT, for a maximum isolated output power, POUT, of about 200 mW. An operative V , for a maximum isolated output power, P , of about 200 mW. An operative frequencyOUT of about 250 MHz was chosen for the DCOUT-DC conversion as a tradeoff among frequency of about 250 MHz was chosen for the DC-DC conversion as a tradeoff among the the efficiency performance of its three building blocks. Chip A was designed in a 0.18-μm efﬁciency performance of its three building blocks. Chip A was designed in a 0.18-µm BCD BCD technology by STMicroelectronics, which provides high-voltage LDMOS transistors technology by STMicroelectronics, which provides high-voltage LDMOS transistors suited suited for a D-class power oscillator (see Figure 3a). It is worth mentioning that the for a D-class power oscillator (see Figure3a). It is worth mentioning that the adopted adopted LDMOS devices have similar performance to those previously used for fully integrated thick-oxide DC-DC converters [9,13]. On the other hand, Chip B was fabricated in the same 0.13-μm CMOS process by STMicroelectronics used in [13,17,18]. Indeed, such technology provides a high-frequency Schottky diode with an elementary active area of 100 μm2 and a breakdown voltage of 25 V. The rectifier efficiency, ηRECT, depends on the number of elementary diode cells in parallel, M. It was set equal to 2 to maximize

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performance at VOUT and POUT of about 20 V and 200 mW, respectively. A full-bridge topology was preferred, as the voltage drops across two series-connected diodes are negligible. As far as the isolation transformer is concerned, a fully stacked two-winding topol- Electronics 2021, 10, 1186 8 of 12 ogy was adopted to maximize the magnetic coupling coefficient, k. The coil geometry was optimized by means of EM simulations in ADS Momentum. A high turn ratio was chosen LDMOSto obtain devices the haverequired similar step performance-up voltag to thosee. The previously overall used geometrical for fully integrated parameters of primary and thick-oxidesecondary DC-DC windings converters are [9,13 reported]. On the other in Table hand, Chip 2. The B was microphotograph fabricated in the same of the fabricated poly- 0.13-µm CMOS process by STMicroelectronics used in [13,17,18]. Indeed, such technology providesimide aisolation high-frequency transformer Schottky diode (i.e., with C anhip elementary T in Figure active area7b) of is 100 shownµm2 and in Figure 9. The dashed abox breakdown highlights voltage the of 2520 V.-µm The pol rectifieryimide efficiency, layerηRECT that, depends is required on the numberto guarantee of basic galvanic iso- elementarylation. The diode transformer cells in parallel, secondaryM. It was set equal primary to 2 to maximize winding performance outputs at areVOUT connected to the rectifier and POUT of about 20 V and 200 mW, respectively. A full-bridge topology was preferred, as theinput voltage (V dropsR1 and across VR2 two) and series-connected to the oscillator diodes are open negligible. drains As far (V asD1 the and isolation VD2), respectively, with the transformercenter tap is concerned,available a fullyfor the stacked voltage two-winding supply topology connection was adopted (i.e., to maximizeVDD). Figure 10 shows the sim- the magnetic coupling coefficient, k. The coil geometry was optimized by means of EM simulationsulated performance in ADS Momentum. of the A high isolation turn ratio transformer was chosen to obtain in terms the required of inductance step- and Q-factor of upprimary voltage. Theand overall secondary geometrical windings parameters as of a primaryfunction and of secondary frequency. windings Table are 3 summarizes the elec- reportedtrical performance in Table2. The microphotograph of the isolation of the fabricatedtransformer polyimide at the isolation operative transformer frequency of 250 MHz. (i.e., Chip T in Figure7b) is shown in Figure9. The dashed box highlights the 20- µm polyimideThe layer DC that-DC is converter required to guarantee was assembled basic galvanic chip isolation. on board The transformer for electrical characterization. A secondaryphoto of primary the assembled winding outputs chips, are connected along with to the the rectifier corresponding input (VR1 and V R2sizes,) and is shown in Figure 11a, towh theile oscillator the testing open drains printed (VD1 and circuitVD2), respectively,board (PCB) with theis depicted center tap available in Figure for 11b. The DC-DC con- the voltage supply connection (i.e., VDD). Figure 10 shows the simulated performance of theverter isolation was transformer characterized in terms at of inductanceincreasing and dcQ-factor output of primary voltage, and V secondaryOUT, from 15 to 20 V by means windingsof a semiconductor as a function of frequency. parameter Table analyzer.3 summarizes All the measurements electrical performance were of the performed at a 5-V power isolation transformer at the operative frequency of 250 MHz. supply, VDD, and room temperature. Figure 12 shows the isolated output power, POUT, and Tablethe power 2. Geometrical efficiency, parameters η of, theas polyimidea function isolation of transformer.the isolated output voltage, VOUT. The DC-DC con- OUT verterTransformer achieves Windings its best MTL performance No. t (µm) at na V w of(µm) abouts (µ m)18.5d V,OUT delivering(µm) an isolated output powerPrimary of 215 mW with 325% efficiency. 5 4.5 At a 20 53-V output 8.5 voltage, 1012 the measured POUT and η are 200Secondary mW and 24.5%, 2 respectively. 5 12 15.5 8.5 1012

VR1 VR2

VD1 VD2

VDD

Polyimide layer

FigureFigure 9. Micrograph 9. Micrograph of the stand-alone of the stand polyimide-alone isolation polyimide transformer isolation (Chip T). transformer (Chip T).

Table 2. Geometrical parameters of the polyimide isolation transformer.

Transformer Windings MTL no. t (µm) n w (µm) s (µm) dOUT (µm) Primary 3 5 4.5 53 8.5 1012 Secondary 2 5 12 15.5 8.5 1012

ElectronicsElectronics 20212021, 10, ,10 1186, 1186 9 of9 of12 12

140 14 1400 10 Secondary Secondary coil 120 12 1200 Primary Primary coil 8 100 10 1000

80 8 800 Q 60 6 600 Q

4 -

factor factor 40 4 400 2

20 2 200 Primary coil inductance [nH] inductancecoil Primary

0 0 [nH] inductancecoil Secondary 0 0 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 Frequency [GHz] Frequency [GHz]

(a) (b) Electronics 2021, 10, 1186 9 of 12 FigureFigure 10. 10. TransformerTransformer simulated simulated performance: performance: (a) ( aprimary) primary winding; winding; (b) ( bsecondary) secondary winding. winding.

TableTable 3. 3.ElectricalElectrical parameters parameters of ofthe the polyimide polyimide isolation isolation transformer transformer at at250 250 MHz. MHz.

140 14 1400 10 Secondary Secondary coil Transformer120 Winding Inductance (nH12 ) Q-Factor1200 k Self-Resonance Frequency (MHz) Transformer Primary coil Self-Resonance Primary Inductance32 (nH) Q11.6-Factor k 8 100Winding 10 1000 0.81 Frequency840 (MHz) Secondary 239 9.1 6

Primary80 328 11.6800 Q 0.81Q 840 Secondary60 2396 9.1600

4 -

factor factor Power40 (a)4 400 2 oscillator20 2 200

Primary coil inductance [nH] inductancecoil Primary The DC-DC converter was assembled chip on board for electricalRectifier characterization. A 0 0Isolation [nH] inductancecoil Secondary 0 0 photo of the assembled chips, along with the corresponding0.0 0.2 0.4 sizes,0.6 is0.8 shown1.0 in Figure 11a, 0.0 0.2 0.4 0.6 0.8 1.0transformer Frequency [GHz] Frequency [GHz] while the testing printed circuit board (PCB) is depicted in Figure 11b. The DC-DC converter was characterized( ata) increasing dc output voltage, VOUT,( fromb) 15 to 20 V by means of a semiconductor parameter analyzer. All measurements were performed at a 5-V power Figure 10. Transformer simulated performance: (a) primary winding; (b) secondary winding. supply, VDD, and room temperature. Figure 12 shows the isolated output power, POUT, Tableand the3. Electrical power parameters efﬁciency, ofη the, as polyimide a function isolation of the transformer isolated outputat 250 MHz. voltage, VOUT. The DC-DC converter achieves its best performance at a V of about 18.5 V, delivering an isolated Transformer Winding Inductance (nH) Q-Factor OUTk Self-Resonance Frequency (MHz) outputPrimary power of 215 mW with32 25% efﬁciency.11.6 At a 20-V output voltage, the measured P and η are 200 mW and 24.5%, respectively.0.81 840 PowerOUTSecondary oscillator (Chip A) 239 9.1 Tech: 0.18-µm BCD (b) Size: Power1058 µm x 1058 µm (a) oscillator Rectifier Transformer (Chip T) Isolation Tech: Polyimide isolation transformer Size: 2400 µm x 2400 µm Rectifier (Chip B) Tech: 0.13-µm CMOS Size: 904 µm x 1214 µm Figure 11. (a) Isolated DC-DC converter assembled chip on board; (b) testing PCB. Power oscillator (Chip A) Tech: 0.18-µm BCD (b) Size: 1058 µm x 1058 µm Transformer (Chip T) Tech: Polyimide isolation Size: 2400 µm x 2400 µm Rectifier (Chip B) Tech: 0.13-µm CMOS Size: 904 µm x 1214 µm FigureFigure 11. 11. (a)( aIsolated) Isolated DC DC-DC-DC converter converter assembled assembled chip on chip board; on ( board;b) testing (b )PCB. testing PCB.

ElectronicsElectronics 20212021,, 1010,, 1186 1186 1010 of of 12 12

300 27

275 24 efficiency,Power [mW]

250 21

OUT P 225 18

200 15 η [%]

175 12 Output power, power, Output

150 9 15 16 17 18 19 20 Output voltage, V [V] OUT

FigureFigure 12. 12. PowerPower efficiency, efﬁciency, ηη,, and and output output power, power, POUT, ,vs vs.. isolated isolated output output power. power.

TheThe experimental experimental performance performance is is summarized summarized and and compared compared with with state state-of-the-art-of-the-art galvanicallygalvanically isolated isolated DC DC-DC-DC convert convertersers adopting adopting different different basic basic isolation isolation technologies technologies in in TableTable 44.. TheThe comparisoncomparison onlyonly includesincludes isolatedisolated convertersconverters forfor high-/medium-voltagehigh-/medium-voltage applications (i.e., with a voltage gain from 1.6 to 4), which require the most complex isolation plications (i.e., with a voltage gain from 1.6 to 4), which require the most complex isolation transformers in terms of turn ratio compared to DC-DC converters with almost unitary transformers in terms of turn ratio compared to DC-DC converters with almost unitary voltage gain [3,11]. Moreover, traditional isolation technologies are considered, i.e., with- voltage gain [3,11]. Moreover, traditional isolation technologies are considered, i.e., without the adoption of magnetic materials, which considerably boost both output power and out the adoption of magnetic materials, which considerably boost both output power and efficiency performance at the expense of a more complex and expensive process [22]. efficiency performance at the expense of a more complex and expensive process [22]. Table 4. State of theFrom art of isolatedthe comparison DC-DC converters in Table for4, several HV/MV considerations applications (basic arise. isolation). Better performance results are achieved with D-class power oscillators, enabled by high-BV devices (such as Refs. [13LDMOS][ of HV MOS18),][ especially when VOUT19 is][ higher than 10 V.20 On] the other Thishand, Work the Isolationwidespread adopted Thick topology oxide for the rectifier is the Schottky diode Polyimide full bridge, as Polyimide it allows Isolation transformer 3.7-µm Cu 6-µm Au 5-µm Au BEOL efficient operation in0.9- theµm AlVHF band. Finally, two-chip implementations6-µm Au achieve5-µ mhigher Au Isolation transformer Low Low BCD SOI substrate power densities than the three-chip one at the expense of higherconductivity costs due toconductivity larger ex- Chip no.pensive silicon chips. It 2is worth noting that, despite significant differences 3 in the isola 3 tion Oscillator topology LDMOS D-class CMOS CR inductively coupled CMOS CR hybrid-coupled HV CMOS D-class LDMOS D-class Rectifier topologytechnologies, similar power efficiency Schottky dioderesults full bridgeare achieved. For deeper analysis, the pro- POUT (mW) 780posed DC-DC converter 200 is compared with the 300 DC-DC converters 225 in [13,18], which 200 shares η (%) 28 27 24 25 24.5 VDD/VOUT (V) 5/20both similar circuit topologies 5/8 and technologies 5/10 for the active circuitries. 5/15 Specifically, 5/20 Ta- f OSC (MHz) 165 240 225 160 250 Power density ble 5 reports the simulated power efficiency breakdown among the DC-DC converter 83 19 36 n.a. 25 (mW/mm2) building blocks, also including efficiencies of the bonding wires from the oscillator to the transformer, ηB1, and from the transformer to the rectifier, ηB2. It is quite evident that the advantageFrom of the a comparisoncustomized isolation in Table 4transformer, several considerations (i.e., 60% efficiency) arise. Better is frustrated performance by the needresults for are additional achieved bonding with D -classwires powerbetween oscillators, Chips A and enabled T. This by is high-BV only partially devices due (such to additionalas LDMOS bonding of HV MOS),wire losses especially while when beingV mainlyOUT is higherrelated thanto the 10 degradation V. On the other of power hand, oscillatorthe widespread efficiency, adopted ηOSC, which topology is 17 for percentage the rectifier points is the lower Schottky than diodein [13] full. Indeed, bridge, only as a it fullyallows integrated efficient approach operation for in thethe VHFisolation band. transformer Finally, two-chip guarantees implementations an effective codesign achieve betweenhigher power the oscillator densities active than core the and three-chip the transformer one at the itself, expense which of benefits higher costsfrom duea very to accuratelarger expensive predictio siliconn of on chips.-chip It interconnection is worth noting parasitics that, despite for significantthe actual differences optimization in the of DCisolation-AC power technologies, efficiency. similar power efficiency results are achieved. For deeper analysis, the proposed DC-DC converter is compared with the DC-DC converters in [13,18], which shares both similar circuit topologies and technologies for the active circuitries. Specifically, Table5 reports the simulated power efficiency breakdown among the DC-DC converter building blocks, also including efficiencies of the bonding wires from the oscillator to the transformer, ηB1, and from the transformer to the rectifier, ηB2. It is quite evident that the advantage of a customized isolation transformer (i.e., 60% efficiency) is frustrated by the need for additional bonding wires between Chips A and T. This is only partially due to

Electronics 2021, 10, 1186 11 of 12

additional bonding wire losses while being mainly related to the degradation of power oscillator efficiency, ηOSC, which is 17 percentage points lower than in [13]. Indeed, only a fully integrated approach for the isolation transformer guarantees an effective codesign between the oscillator active core and the transformer itself, which benefits from a very accurate prediction of on-chip interconnection parasitics for the actual optimization of DC-AC power efficiency.

Table 5. Simulated power efﬁciency breakdown for galvanically isolated DC-DC converters.

Isolation Transformer Simulation Measurement Technology Unit ηOSC ηB1 ηTRAF ηB2 ηRECT η η [13] 1 On-chip thick oxide 75.5 90 52.6 - 85.5 30.6 28 [%] [18] On-chip thick oxide 73 90 50 - 75 24.6 24 [%] This work Standalone polyimide 58 90 60 90 90 25.4 24.5 [%] 1 Efﬁciency values are calculated from Tables IV and V in [13].

5. Conclusions An experimental comparison of galvanically isolated DC-DC converters for high- voltage applications was presented in order to analyze the benefits and drawbacks of the two most adopted isolation approaches in terms of performance, design flexibility, integration level and costs. To this aim, a DC-DC converter was specifically designed and implemented by using a polyimide-based low-cost technology for 5-kV basic isolation. Despite better transfer efficiency of the isolation transformer with respect to a fully integrated approach, the overall efficiency performance is affected by additional losses, the codesign optimization is quite involved due to off-chip parasitics in the DC-AC conversion and, finally, the power density is lower. On the other hand, a three-chip architecture is more flexible and suitable for a continuous silicon process upgrade (i.e., process scaling) while being able to achieve up to a 10-kV isolation rating, thanks to more than 30-µm thick polyimide layers.

Author Contributions: Conceptualization, E.R.; validation, E.R. and N.S.; formal analysis, E.R.; investigation, E.R., N.S. and A.P.; methodology, E.R.; project administration, G.P.; supervision, E.R.; writing—original draft, E.R.; writing—review and editing, E.R. All authors have read and agreed to the published version of the manuscript. Funding: This research received no external funding. Data Availability Statement: The data presented in this study are available on request from the corresponding author. Acknowledgments: The authors would like to thank A. Cantoni, G. Allegato, and V. Palumbo of STMicroelectronics for isolation technology access. Conﬂicts of Interest: The authors declare no conﬂict of interest.

References 1. Ragonese, E.; Parisi, A.; Spina, N.; Palmisano, G. Fully integrated galvanically isolated DC-DC converters based on inductive coupling. In International Conference on Applications in Electronics Pervading Industry, Environment and Society; Springer International Publishing: Cham, Switzerland, 2019; pp. 335–341. 2. Lombardo, P.; Fiore, V.; Ragonese, E.; Palmisano, G. A fully-integrated half-duplex data/power transfer system with up to 40Mbps data rate, 23mW output power and on-chip 5kV galvanic isolation. In Proceedings of the IEEE Int. Solid-State Circuits Conference. Dig. Tech. Papers (ISCCC), San Francisco, CA, USA, 31 January–4 February 2016; pp. 300–301. 3. Qin, W.; Yang, X.; Ma, S.; Liu, F.; Zhao, Y.; Zhao, T.; Chen, B. An 800mW fully integrated galvanic isolated power transfer system meeting CISPR 22 Class-B emission levels with 6dB margin. In Proceedings of the IEEE International Solid-State Circuits Conference. Dig. Tech. Papers (ISSCC), San Francisco, CA, USA, 17–21 February 2019; pp. 246–248. 4. Devices-Magnetic, D.V.S. DIN VDE Semiconductor Devices-Magnetic and Capacitive Coupler for Basic and Reinforced Isolation; VDE Verlag VDE V 0884-11: Berlin, Germany, 1 January 2017. 5. Greco, N.; Parisi, A.; Lombardo, P.; Spina, N.; Ragonese, E.; Palmisano, G. A double-isolated DC-DC converter based on integrated LC resonant barriers. IEEE Trans. Circuits Syst. I Regul. Pap. 2018, 65, 4423–4433. [CrossRef] Electronics 2021, 10, 1186 12 of 12

6. Yun, R.; Sun, J.; Gaalaas, E.; Chen, B. A transformer-based digital isolator with 20kVPK surge capability and > 200kV/µS common mode transient immunity. In Proceedings of the IEEE Symposium. on VLSI Circuits, Honolulu, HI, USA, 15–17 June 2016; pp. 1–2. 7. Parisi, A.; Ragonese, E.; Spina, N.; Palmisano, G. Galvanically isolated DC-DC converter using a single isolation transformer for multi-channel communication. IEEE Trans. Circuits Syst. I Regul. Pap. 2020, 67, 4434–4444. [CrossRef] 8. Palumbo, V.; Ghidini, G.; Carollo, E.; Toia, F. Integrated Transformer. U.S. Patent 10236115B2, 19 March 2019. 9. Ragonese, E.; Spina, N.; Castorina, A.; Lombardo, P.; Greco, N.; Parisi, A.; Palmisano, G. A fully integrated galvanically isolated DC-DC converter with data communication. IEEE Trans. Circuits Syst. I Regul. Pap. 2018, 65, 1432–1441. [CrossRef] 10. Chen, B. High Frequency Power Converter Based on Transformers. U.S. Patent 7983059B2, 19 July 2011. 11. Chen, B. Fully integrated isolated DC-DC converter using microtransformers. In Proceedings of the 2008 Twenty-Third Annual IEEE Applied Power Electronics Conference and Exposition, Austin, TX, USA, 24–28 February 2008; pp. 335–338. 12. Fanori, L.; Andreani, P. Class-D CMOS oscillators. IEEE J. Solid State Circuits 2013, 48, 3105–3119. [CrossRef] 13. Fiore, V.; Ragonese, E.; Palmisano, G. A fully-integrated watt-level power transfer system with on-chip galvanic isolation in silicon technology. IEEE Trans. Power Electron. 2017, 32, 1984–1995. [CrossRef] 14. Moscatelli, A.; Merlini, A.; Croce, G.; Galbiati, P.; Contiero, C. LDMOS implementation in a 0.35 µm BCD technology (BCD6). In Proceedings of the International Symposium on Power Semiconductor Devices & IC’s (ISPSD), Toulouse, France, 22–25 May 2000; pp. 323–326. 15. Riccardi, D.; Causio, A.; Filippi, I.; Paleari, A.; Pregnolato, L.V.; Galbiati, P.; Contiero, C. BCD8 from 7V to 70V: A new 0.l8µm technology platform to address the evolution of applications towards smart power IC’s with high logic contents. In Proceedings of the 19th International Symposium on Power Semiconductor Devices and ICs, Jeju, Korea, 27–31 May 2007; pp. 73–76. 16. Ragonese, E.; Fiore, V.; Spina, N.; Palmisano, G. Power Oscillator Apparatus with Transformer-Based Power Combining. U.S. Patent 9240752 B2, 19 January 2016. 17. Spina, N.; Fiore, V.; Lombardo, P.; Ragonese, E.; Palmisano, G. Current-reuse transformer coupled oscillators with output power combining for galvanically isolated power transfer systems. IEEE Trans. Circuits Syst. I Regul. Pap. 2015, 62, 2940–2948. [CrossRef] 18. Greco, N.; Spina, N.; Fiore, V.; Ragonese, E.; Palmisano, G. A galvanically isolated DC-DC converter based on current-reuse hybrid coupled oscillators. IEEE Trans. Circuits Syst. II Exp. Briefs 2017, 64, 56–60. [CrossRef] 19. Greco, N.; Parisi, A.; Spina, N.; Ragonese, E.; Palmisano, G. Scalable lumped models of integrated transformers for galvanically isolated power transfer systems. Elsevier Integr. VLSI J. 2018, 63, 323–331. [CrossRef] 20. Chen, B. Isolated half-bridge gate driver with integrated high-side supply. In Proceedings of the 2008 IEEE Power Electronics Specialists Conference, Rhodes, Greece, 15–19 June 2008; pp. 3615–3618. 21. Biondi, T.; Scuderi, A.; Ragonese, E.; Palmisano, G. Analysis and modeling of layout scaling in silicon integrated stacked transformers. IEEE Trans. Microw. Theory Tech. 2006, 54, 2203–2210. [CrossRef] 22. Zhuo, Y.; Ma, S.; Zhao, T.; Qin, W.; Zhao, Y.; Guo, Y.; Yan, H.; Chen, B. A 52% peak efﬁciency> 1-W isolated power transfer system using fully integrated transformer with magnetic core. IEEE J. Solid State Circuits 2019, 54, 3326–3335. [CrossRef]