Semiconductor Galvanic Isolation Based Onboard Vehicle Battery Chargers

DISSERTATION

Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy

in the Graduate School of The Ohio State University

Chengcheng Yao

Graduate Program in Electrical and Computer Engineering

The Ohio State University

2018

Dissertation Committee:

Dr. Jin Wang, Advisor

Dr. Longya Xu

Dr. Yuan Zhang

Chengcheng Yao

2018

Abstract

Power converters with galvanic isolation are widely used in various applications, which is also required by the industry safety standards (e.g., IEC60950 and UL2202). Traditionally, there are mainly three solutions to achieve the galvanic isolation in power converters, including the magnetic field-based isolation, electric field-based isolation, and optics-based isolation. Semiconductor-based galvanic isolation (SGI) is a paradigm shift in realizing galvanic isolation. It uses semiconductor switches’ output capacitance to isolate two sides of the circuit when the switches are off. When the switches are on, differential-mode (DM) power can still be delivered from the primary side to the secondary side circuit. It means both the common-mode (CM) current blocking and DM power delivery are handled by the semiconductor switch. This dissertation conducts a comprehensive study of the principle, safety requirements, suitable circuit topologies, the touch current issue and design guidelines of SGI based power converters. The goal is to achieve high power density, high efficiency, and valid galvanic isolation performance that meet safety standards. Onboard vehicle battery charger is selected for the target application.

The discussion starts with a review of safety standards on galvanic isolation, which can be evaluated with two tests: the withstand voltage test and the touch current test. Then, principles, benefits, and challenges of the SGI technology are discussed.

A family of SGI circuit topologies is explored. Basically, the SGI concept can be applied to most traditional inductor-based and capacitor-based circuit topologies. The developed topologies include (a) SGI based buck cell, (b) SGI based buck-boost cell, (c) SGI based boost cell, (d) SGI based switched capacitor converters, and (e) SGI based bridgeless power factor correction converters. Using onboard battery charger as an example, the selection of

SGI topologies for different ac/dc power levels is discussed.

The touch current issue is one of the key challenges of SGI power converters. Systematic analysis and modeling methods are proposed to predict the touch current. The analysis shows that for a given SGI topology, it is preferred to have smaller Coss and fsw to reduce the touch current. However, these constraints greatly limits the power density and efficiency of SGI power converters. TC compensation is an approach to mitigate the tradeoff between satisfying safety standards and achieving high power density and high efficiency. Several passive and active TC compensation approaches have been investigated. The passive filtering techniques are not very effective due to the low-frequency nature of the touch current. Instead, active compensation methods are far more effective. A comprehensive discussion is presented on various aspects of active compensation methods, including system architecture, TC detection, compensation current injection methods, channel sharing and the timing control. A buck-boost based distribution method with local control is presented to illustrate the design process. Several local detection and control methods are also explored to realize a local control of the TC compensation circuit so that the main controller does not need to involve in the control of the TC compensation.

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The design procedure of SGI based power converters is quite different from the traditional transformer-based isolated converters because semiconductor devices handle both DM power delivery and galvanic isolation. A systematic design approach is presented.

The design of galvanic isolation and differential mode power delivery can start in parallel and but need to merge together at some point. Galvanic isolation determines the voltage rating of the main devices. It also sets a limit a switching frequency and device output capacitance if a TC compensation is not applied. DM power delivery sets the requirements of the main device on-resistance, switching losses, circuit topology, and energy storage component size. With an effective TC compensation, the switching frequency constraint can be alleviated from the touch current requirement. To validate the analysis, a 2-kW SGI based onboard battery charger is prototyped. The PFC stage is realized by a GaN-based totem-pole topology. The dc/dc stage is an SGI based 1:1 switching capacitor circuit. The system efficiency is 94% - 96%. The system is able to pass the UL2202 touch current test.

The fast response of the proposed local TC control ensures user safety by initiating and stopping the TC compensation whenever it is needed.

Conclusions and recommendations for future work are presented.

Dedication

This document is dedicated to my family.

Acknowledgments

Foremost, I would like to express my sincere gratitude to my supervisor, Prof. Jin Wang for his patient guidance, encouragement, and advice throughout this journey. It is my privilege to join and work in his great team. Under his guidance, I have learned a lot and also got exposed to many aspects of power electronics. There are numeral takeaways from him but here I want to highlight several points that I will always remember. 1) Always think from the big picture, that’s the key to a successful engineer. 2) Always be open- minded and think out of the box. 3) Being able to explain your work clearly is equally important as doing the work itself.

My thanks also go to the committee: Prof. Longya Xu, Prof. Julia Zhang, and Prof. Dr.

Robert R. Seghi for their support, advice, and directions. I would also like to thank Prof.

Fang Luo, Prof. Ayman Fayed, and Prof. Fusheng Wang for their advice on my research.

Thanks Prof. Stephen Sebo for setting me a great example of an organized and life-long engineer.

I also want to thank Dr. Chingchi Chen, Dr. Lihua Chen, Dr. Ke Zou, Dr. Xi Lu, Dr.

Zhuxian Xu, Dr. Ming Su, Dr. Jun Kikuchi, Mr. Chih-Lun Wang and Dr. Dong Cao at Ford

Motor Company, for their guidance and support during my internship in Dearborn,

Michigan. I really appreciate the guidance, help, and opportunity from Dr. Satish Thuta,

Mr. Mehmet Ozbek, Mr. Colin Campbell, Mr. Nick Kalayjian, Dr. Xuan Zhang, Dr.

Michelle Liu, Mr. Jan Rutkjaer, Dr. Jizheng Qiu and Dr. Kia Filoof at Tesla.

Thanks to Dr. Xuan Zhang, Mr. He Li, Ms. Xintong Lv, Mr. Lixing Fu, Dr. Feng Guo,

Dr. Cong Li and Dr. Mark Scott for being my best support in both life and work throughout these years. Thanks for accompanying me over the years as both close friends and colleagues. I’m very grateful to them all for helping me move forward, overcome the hardships, and get through the most difficult days. I wouldn’t have made it without them.

I am really grateful to be working closely with a lot of talented junior students in numerous projects. Without their support, the projects just could not be finished. Special thanks to Mr. Yue Zhang, Mr. Pengzhi Yang, Mr. Mingzhi Leng, Ms. Huanyu Chen, Ms.

Zhongjing Wang, Ms. Gengyao Li, Mr. Xiaoteng He, Mr. Andong Lang, Mr. Fanbo Zhang,

Ms. Chaoran Han, Mr. Hao Wen, Ms. Huwei Liu and Mr. Markus Sievers.

Thanks to my friends Dr. Xiu Yao, Dr. Luis Herrera, Dr. Mohammed Alsolami, Mr.

Jinzhu Li, Mr. Balaji Narayanasamy, Mr. Da Jiao, Ms. Shuang Tan, Dr. Linyu Zhu, Dr.

Xiang Hao, Mr. Amol R. Deshpande, Mr. Ziwei Ke, Dr. Hao Yang, Mr. Boxue Hu, Ms.

Qing Jia, Mr. Zuo Wei, Mr. Yingzhuo Chen, Mr. Karun Arjun Potty, Mr. Eric Bauer, Mr.

Yousef Abdullah, Mr. Mohamed Elshaer, Mr. John A. Brothers, Mr. Ke Zhu, Mr. Lucheng

Wen, Dr. Zhendong Zhang, Dr. Thomas Tsai, Ms. Pu Xu, Mr. Cong Deng, Dr. Dakai Hu,

Dr. Haiwei Cai, Dr. Yu Liu, Dr. Miao Wang, Ms. Xiaodan Wang, Mr. Jianyu Pan, Dr. Feng

Qi, Mr. Xiaotao Dong, Mr. Rachid Darbali Zamora, Mr. Ernest Davidson, Mr. Hanning

Tang, and Mr. Jizhou Jia for sharing this journey at the Ohio State University. Thank you

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all for those joys and shared memories. I will not forget all the days I was embraced by your friendship, help, and support.

I would also like to thank all the students who took ECE5047 and ECE5025 in 2016.

Thank you all for making this teaching experience fun, memorable, and rewarding.

I would also like to take this opportunity to thank all student council members of the

Center for High-Performance Power Electronics (CHPPE). It takes some effort to initiate this platform but it takes even much more to run this organization. It’s our privilege to serve the CHPPE family. I sincerely appreciate the contribution from our faculty advisor, council president, committee chairmen and students.

I own my deepest gratitude to my parents Zhili Yao and Mihui Chen. Without your love and support, I would not have been where I am today.

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Vita

June 2011 ...... B.S. Electrical Engineering, Changsha University

of Science and Technology

Sept. 2011 to present ...... Ph.D. student, Electrical Engineering, The Ohio

State University

Publications

[1] C. Yao, P. Yang, H. Chen, M. Leng, H. Li, K. Zou, M. Su, C. C. Chen, and J. Wang,

" Electromagnetic Noise Mitigation for Ultra-fast On-die Temperature Sensing in

High Power Modules ", IEEE Trans. Power Electron., early online access.

[2] X. Zhang, C. Yao and J. Wang, "A Quasi-Switched-Capacitor Resonant Converter,"

in IEEE Transactions on Power Electronics, vol. 31, no. 11, pp. 7849-7856, Nov.

2016.

[3] X. Zhang, C. Yao, C. Li, L. Fu, F. Guo, and J. Wang, "A Wide Bandgap Device-

Based Isolated Quasi-Switched-Capacitor DC/DC Converter," in IEEE Trans.

Power Electron., vol. 29, no. 5, pp. 2500-2510, May 2014.

[4] H. Li, X. Zhang, L. Wen, John. Brother, C. Yao, C. Han, L. Liu, J. Xu, J. Puukko,

J. Wang, "Paralleled Operation of High-Voltage Cascode GaN HEMTs," in IEEE

Journal of Emerging and Selected Topics in Power Electronics, vol. 4, no. 3, pp.

815-823, Sept. 2016.

[5] F. Guo, L. Fu, X. Zhang, C. Yao, H. Li, J. Wang, "A Family of Quasi-Switched-

Capacitor Circuit Based Dual-Input DC/DC Converters for Photovoltaic Systems

Integrated with Battery Energy Storage," IEEE Trans. Power Electron., vol. 31, no.

12, pp. 8237-8246, Dec. 2016.

[6] M. J. Scott, L. Fu, X. Zhang, J. Li, C. Yao, M. Sievers, and J. Wang, “Merits of

gallium nitride power conversion,” IOP Semicond. Sci. Technol., vol. 28, no. 7, pp.

1-10, July 2013.

[7] J. Wang, C. Yao, H. Li, E. Bauer, K. A. Potty and Boxue He, "How to change the

landscape of power electronics with wide bandgap power devices," 2017 IEEE 3rd

International Future Energy Electronics Conference and ECCE Asia (IFEEC 2017

- ECCE Asia), Kaohsiung, Taiwan, 2017, pp. 151-156.

[8] C. Yao, Y. Zhang, X. Zhang, H. Chen, H. Li, J. Wang, " Adaptive Constant Power

Control and Power Loss Analysis of an MHz GaN Based High Power Density

AC/DC Converter for Low Power Applications ", accepted in IEEE 32th Applied

Power Electronics Conf. and Expo. (APEC), 2017

[9] Y. Zhang, C. Yao, X. Zhang, H. Chen, H. Li and J. Wang, "Power loss model for

MHz critical mode power factor correction circuits," 2016 IEEE 4th Workshop on

Wide Bandgap Power Devices and Applications (WiPDA), Fayetteville, AR, 2016,

pp. 275-281.

[10] C. Yao, M. Leng, P. Yang, H. Li, L. Fu, K. Zou, C. C. Chen, and J. Wang,

"Electromagnetic Noise Coupling and Mitigation for Fast Response On-die

Temperature Sensing in High Power Modules", in Proc. IEEE 31th Applied Power

Electronics Conf. and Expo. (APEC), 2016, pp. 1554-1560, Long Beach, CA, 2016.

[11] C. Yao, W. Li, H. Li, C. Han, M. Wang, J. Qian, X. Zhang, F. Luo, and J. Wang,

"Common-mode noise comparison study for lateral wire-bonded and vertically

integrated power modules," in Energy Conversion Congress and Exposition

(ECCE), 2015 IEEE, pp.3092-3098, 20-24 Sept. 2015

[12] C. Yao, M. Leng, H. Li, L. Fu, K. Zou, CC. Chen, F. Luo, and J. Wang,

"Electromagnetic noise coupling and mitigation in dynamic tests of high power

switching devices," in Energy Conversion Congress and Exposition (ECCE), 2015

IEEE, pp.6610-6615, 20-24 Sept. 2015

[13] X. Zhang, C. Yao, P. Yang, H. Li, L. Fu, J. Wang "Touch Current Suppression for

Semiconductor-Based Galvanic Isolation", accepted in Wide Bandgap Power

Devices and Applications (WiPDA), 2016

[14] H. Li, C. Yao, L. Fu, X. Zhang and J. Wang, "Evaluations and applications of GaN

HEMTs for power electronics," 2016 IEEE 8th International Power Electronics and

Motion Control Conference (IPEMC-ECCE Asia), Hefei, 2016, pp. 563-569.

[15] H. Li, X. Zhang, Z. Zhang, C. Yao, F. Qi, B. Hu, L. Liu and J. Wang, “Design of a

10 kW GaN-based High Power Density Three Phase Inverter” accepted by 2016

IEEE Energy Conversion Congress and Exposition (ECCE), Milwaukee, WI, 2016.

[16] H. Li, X. Zhang, L. Wen, J. A. Brothers, C. Yao, and J. Wang. "Evaluation of High

Voltage Cascode GaN HEMTs in Parallel Operation", accepted by IEEE 31th

Applied Power Electronics Conf. and Expo. (APEC), 2016.

[17] X. Zhang, H. Li. C. Yao, and J. Wang, “Semiconductor-based Galvanic Isolation”,

accepted in Wide Bandgap Power Devices and Applications (WiPDA), 2015

[18] H. Li, L. Zhu, S. Yang, C. Yao, and J. Wang, "Events identification based load

modeling for residential microgrid," in Energy Conversion Congress and Exposition

(ECCE), 2015 IEEE, pp.3430-3435, 20-24 Sept. 2015

[19] M.J. Scott, L. Fu, C. Yao, X. Zhang, L. Xu, R. D. Zamora, J. Wang, "Design

considerations for wide bandgap based motor drive systems," in proc. IEEE

International Electric Vehicle Conference (IEVC), pp.1,6, 17-19, Florence Italy,

Dec. 17-19, 2014

[20] X. Zhang, C. Yao, F. Guo, and J. Wang, “Efficiency Improvement of the Quasi-

Switched-Capacitor Resonant Converter with Optimal Operation and Burst-mode

Control,” in Proc. IEEE Energy Conversion Congress and Expo (ECCE 2014), pp.

5444-5450, Pittsburgh, PA, Sept. 14-18, 2014.

[21] C. Li, R. D. Zamora, C. Yao, L. Fu, H. Li, X. Zhang, F. Guo, and J. Wang, “An

isolated hybrid switched C-L dc-dc circuit with high step-up ratio and reduced

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switch voltage stress,” in Proc. IEEE Energy Conversion Congress and Expo

(ECCE 2014), pp. 5376-5383, Pittsburgh, PA, Sept. 14-18, 2014.

[22] X. Zhang, C. Yao, F. Guo, L. Fu, and J. Wang, “A Family of Quasi-Switched-

Capacitor Converters,” in Proc. IEEE Transportation Electrification Conference

and Expo, Asia-Pacific, pp. 1-6, Beijing, China, Aug. 31- Sept. 3, 2014.

[23] C. Li, R. D. Zamora, C. Yao, L. Fu, A. Lang, H. Li, F. Guo, and J. Wang, “A family

of high gain hybrid switched capacitor-inductor dc-dc circuits for renewable energy

applications,” in Proc. IEEE Transportation Electrification Conference and Expo,

Asia-Pacific, pp. 1-6, Beijing, China, Aug. 31- Sept. 3, 2014.

[24] L. Fu, X. Zhang, M. Scott, C. Yao, and J. Wang, “The evaluation and application of

wide bandgap power devices,” in Proc. IEEE Transportation Electrification

Conference and Expo, Asia-Pacific, pp. 1-5, Beijing, China, Aug. 31- Sept. 3, 2014.

[25] H. Li, F. Guo, S. Yang, L. Zhu, C. Yao and J. Wang, "Usage Profile Optimization

of the Retired PHEV Battery in Residential Microgrid" in Proc. IEEE

Transportation Electrification Conference and Expo, Asia-Pacific, pp. 1-6, Beijing,

China, Aug. 31- Sept. 3, 2014.

[26] X. Zhang, C. Yao, M. Sievers, P. Xu, M. J. Scott, E. Davidson, and J. Wang, “A

GaN Transistor based 90W AC/DC Adapter with a Buck-PFC AC/DC Stage and an

Isolated Quasi-Switched-Capacitor DC/DC Stage” in Proceedings of the

29th Annual IEEE Applied Power Electronics Conference and Expo (APEC), pp.

109-116, March 16-20, Fort Worth, TX, March 16-20, 2014.

xiii

[27] X. Zhang, F. Guo, C. Yao, P. Xu, and J. Wang, “Small-signal Modeling and

Controller Design of an Isolated Quasi-Switched-Capacitor DC/DC Converter”

in Proceedings of the 29th Annual IEEE Applied Power Electronics Conference and

Expo (APEC), pp. 1032-1038, Fort Worth, TX, March 16-20, 2014.

[28] C. Li, D. Jiao, M. Scott, C. Yao, L. Fu, X. Lu, T. Chen, J. Li, and J. Wang, “A 2 kW

Gallium Nitride based switched capacitor three-port inverter,” in Proc. IEEE 1st

Workshop on Wide Bandgap Power Devices and Applications, pp. 119 – 124,

Columbus, OH, Oct. 27-29, 2013.

[29] X. Zhang, C. Yao, M. J. Scott, E. Davidson, J. Li, P. Xu, and J. Wang, “A GaN

Transistor based 90W Isolated Quasi-Switched-Capacitor DC/DC Converter for AC

Adaptors” in Proc. IEEE 1st Workshop on Wide Bandgap Power Devices and

Applications, pp. 15-22, Columbus, OH, Oct. 27-29, 2013.

[30] X. Zhang, C. Yao, F. Guo, C. Li, L. Fu, C. Deng, and J. Wang, "Soft Switching,

Frequency Control, and Bidirectional Power Flow of an Isolated Quasi-Switched-

Capacitor DC/DC Converter for Automotive Applications," in Proc. IEEE Energy

Conversion Congress and Exposition (ECCE), Denver, CO, pp. 1393-1400, Sept.

2013.

[31] X. Zhang, C. Yao, F. Guo, and J. Wang, “Reverse Power Flow Study of an Isolated

Quasi-Switched-Capacitor DC/DC Converter for Automotive Applications”

in Proc. IEEE 56th Int. Midwest Symposium On Circuits and Systems (MWCAS

2013), Aug. 4-7, 2013

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[32] X. Zhang, C. Li, C. Yao, L. Fu, F. Guo and J. Wang, "An Isolated DC/DC Converter

with Reduced Number of Switches and Voltage Stresses for Electric and Hybrid

Electric Vehicles," in Proc. 28th Annual IEEE Applied Power Electronics

Conference and Expo (APEC 2013), pp. 1759-1767, March 17-21, 2013.

Fields of Study

Major Field: Electrical and Computer Engineering

Table of Contents

Abstract ...... ii

Dedication ...... v

Acknowledgments...... vi

Vita ...... ix

Publications ...... ix

Fields of Study ...... xv

Table of Contents ...... xvi

List of Tables ...... xxi

List of Figures ...... xxii

Chapter 1. Introduction ...... 1

1.1. Power Converters with Galvanic Isolation...... 1

1.2. Wide Bandgap (WBG) Devices ...... 6

1.3. Onboard Vehicle Battery Chargers ...... 8

1.4. Motivations of this Work ...... 12

1.5. Outline of this Dissertation ...... 13

Chapter 2. Semiconductor-based Galvanic Isolation ...... 15 xvi

2.1. Overview of Safety Requirements ...... 15

2.1.1. Insulation Voltage Requirement ...... 16

2.1.2. Touch Current and Protective Conductor Current Requirement ...... 18

2.2. Principles of Semiconductor-based Galvanic Isolation ...... 20

2.2.1. Basic Principle ...... 20

2.2.2. Potential Benefits ...... 22

2.2.3. Challenges ...... 23

2.3. Conclusions ...... 25

Chapter 3. A Family of SGI Based Circuit Topologies ...... 27

3.1. SGI Building Blocks: Dc/dc cells ...... 27

3.2. SGI based Ac/dc and Dc/ac Topologies ...... 30

3.3. Topology Candidates for Onboard Battery Chargers ...... 31

3.3.1. AC Level 1 Chargers: SGI Critical Conduction Mode (CrM) Buck-boost

Converter ...... 31

3.3.2. AC Level 1 and 2 Chargers: SGI Continuous Conduction Mode (CCM)

Buck-boost Converter ...... 46

3.3.3. AC Level 2 and above Chargers: PFC stage and Switched-capacitor Cell 53

3.4. Conclusions ...... 57

xvii

Chapter 4. Generation Mechanism of CM Leakage Current in Semiconductor-Based

Galvanic Isolation ...... 59

4.1. Overview ...... 59

4.2. Isolation Voltage Stress ...... 60

4.2.1. Impact of AC/DC Stage Circuit Topology ...... 62

4.2.2. Impact of AC Source Grounding Configuration ...... 63

4.2.3. Impact of DC/DC Stage Circuit Topology ...... 65

4.3. Generation Mechanism of the Touch Current ...... 67

4.4. Modeling of the Touch Current ...... 73

4.4.1. High-frequency Pulse Current Model [48] ...... 73

4.4.2. Low-frequency Average Current Model ...... 75

4.5. Output Voltage Potentials and CM Leakage Current with Floating Outputs .... 81

4.6. Conclusions ...... 84

Chapter 5. Touch Current Suppression Methods...... 85

5.1. Requirements of Touch Current Suppressions ...... 85

5.2. Passive TC Suppressions Methods ...... 86

5.2.1. Increasing the CM Impedance by CM chokes ...... 87

5.2.2. Bypassing the TC with Y capacitors ...... 88

5.2.3. Soft-switching Techniques...... 90

xviii

5.3. Active Touch Current Compensation ...... 91

5.3.1. Overview ...... 91

5.3.2. Centralized or Distributed Architecture ...... 94

5.3.3. Detection of the CM Leakage Current ...... 95

5.3.4. Compensation Current Injection Methods ...... 97

5.3.5. Channel Sharing ...... 104

5.3.6. Control of the TC Compensation Circuits ...... 105

5.3.7. Implementation of the Active TC Compensation ...... 107

5.4. Conclusions ...... 114

Chapter 6. Design Guidelines of SGI based Power Converters ...... 115

6.1. Overview ...... 115

6.2. Design of Galvanic Isolation ...... 117

6.3. Design of Differential Power Delivery ...... 121

6.4. Prototype and Experimental Verifications ...... 126

6.4.1. Differential-mode Power Delivery Test ...... 129

6.4.2. Touch Current Test ...... 131

6.5. Conclusions ...... 134

Chapter 7. Conclusions and Future Work ...... 135

7.1. Conclusions ...... 135

xix

7.2. Recommendations for Future Work ...... 140

References ...... 143

List of Tables

Table 1.1. Electrical rating of AC EV chargers ...... 9

Table 3.1. Status and control signal of devices in mode 1 [t1, t2]...... 35

Table 3.2. Status and control signal of devices in mode 2 [t2, t3]...... 36

Table 3.3. Status and control signal of devices in mode 5 [t5, t6]...... 37

Table 3.4. Simulation parameters for verifying the CrM SGI buck-boost converter operation...... 38

Table 3.5. Switches conducting status in CrM SGI buck-boost PFC...... 42

Table 3.6. Switches power losses in SGI CCM buck-boost vehicle charger...... 51

Table 3.7. Power losses in SGI CCM buck-boost vehicle charger with different inductor ripple current...... 51

Table 3.8. Parameters for a case study of a 50 kW SGI switched-capacitor dc/dc stage. 57

Table 4.1. Verification of The Low-frequency Average Current Model ...... 81

Table 5.1. Comparison between centralized and distributed active TC compensation ... 95

Table 5.2. Isolated dc/dc topologies suitable for low-power and1:1 transfer ratio...... 103

Table 6.1. Specifications of the 2 kW SGI based onboard battery charger prototype. .. 127

xxi

List of Figures

Figure 1.1. A generic structure for high-frequency galvanic isolation solution...... 2

Figure 1.2. Magnetic-field-based galvanic isolation solution...... 4

Figure 1.3. Electric field-based galvanic isolation solution...... 5

Figure 1.4. Desired features for future power electronic converters...... 6

Figure 1.5. System diagram of current onboard vehicle battery chargers...... 9

Figure 1.6. Selected onboard charger commercial products in 2016. a) Efficiency vs. power density. b) Efficiency vs. power rating...... 10

Figure 1.7. Selected Onboard charger prototypes in academia from the year 2010 to 2016. a) Efficiency vs. power density. b) Efficiency vs. power rating ...... 11

Figure 2.1. Schematic of the dielectric voltage-withstand test...... 18

Figure 2.2. TC measuring instrument: an impedance network to roughly simulate a human body [74]...... 19

Figure 2.3. Schematic of the leakage current or touch current test...... 19

Figure 2.4. (a) The basic idea of the SGI technology. (b) Examples of the ac switches in anti-series connection. (c) A generic system diagram of SGI ...... 21

Figure 2.5. SGI based SC 1:1 cell. (a) Circuit schematic. DM and CM current flows in

(b) mode I, and (c) mode II...... 22

Figure 2.6. The development map of semiconductor-based galvanic isolation...... 24

xxii

Figure 3.1. SGI building blocks: dc/dc cells (a) SGI based buck cell. (b) SGI based buck- boost cell in CCM operation. (c) SGI based boost cell...... 28

Figure 3.2. (a) A 3X isolated boost dc/dc converter (where all switches are ac switches with bidirectional blocking). (b) The two operation modes of the converter [49]...... 29

Figure 3.3. (a) A 4X isolated Dickson converter, and (b) the equivalent circuits of the two operation modes [49]...... 29

Figure 3.4. SGI based single-phase PFC circuits. (a) A generic circuit diagram with SGI dc/dc cells. (b) SGI based buck PFC...... 30

Figure 3.5. SGI based bridgeless PFC circuits. (a) Bridgeless boost PFC. (b) Bridgeless buck PFC...... 31

Figure 3.6. SGI based dc/ac converter with a two-stage structure...... 31

Figure 3.7. Circuit diagram of the SGI critical conduction mode Buck-boost converter based vehicle battery charger...... 32

Figure 3.8. Comparison of (a) SGI buck-boost converter and (b) traditional buck-boost converter ...... 33

Figure 3.9. (a) Gate signals and circuit diagram of SGI buck-boost converter. (b) Circuit diagram the signal annotations...... 34

Figure 3.10. Schematic of the SGI buck-boost CrM PFC in mode 1 [t1, t2]...... 35

Figure 3.11. Schematic of the SGI buck-boost CrM PFC in mode 2 [t2, t3]...... 36

Figure 3.12. Schematic of the SGI buck-boost CrM PFC in mode 5 [t5, t6]...... 37

Figure 3.13. Simulation results of the SGI buck-boost CrM vehicle charger. (a) Line frequency waveforms. (b) Switching frequency waveforms...... 38

xxiii

Figure 3.14. Comparison of inductor waveforms in boost and buck-boost PFCs...... 40

Figure 3.15. Comparison of other key metrics boost and buck-boost PFCs...... 40

Figure 3.16. Current waveforms of SGI buck-boost PFC. (a) First quadrant devices. (b)

Third quadrant devices...... 41

Figure 3.17. Switching voltage and current of CrM SGI buck-boost PFC in different mode transitions...... 42

Figure 3.18. Calculated a) switching frequency and b) inductor current of CrM SGI buck- boost PFC in the half line cycle...... 43

Figure 3.19. Calculated power losses of CrM SGI buck-boost PFC in the half line cycle.

...... 44

Figure 3.20. Parametric study of efficiency and power loss vs. output power of CrM SGI buck-boost PFC. (a) Converter efficiency and total power loss. (b) Breakdown of major power losses...... 45

Figure 3.21. Parametric study of input RMS current and inductor RMS and peak current vs. output power of CrM SGI buck-boost PFC...... 45

Figure 3.22. Circuit diagrams of the CCM SGI buck-boost vehicle charger...... 46

Figure 3.23. The circuit operation of CCM SGI buck-boost vehicle charger. (a) Mode 1: inductor charging mode. (b) Mode 2: inductor current free-wheeling mode. (c) Mode 3: inductor current freewheeling mode. (d) Mode 4: a repetition of mode 2...... 48

Figure 3.24. Typical waveforms of CCM SGI buck-boost vehicle charger...... 49

Figure 3.25. Conduction and switching losses in each mode and mode transition. (a)

Mode 1. (b) Mode 2. (c) Mode 3 and mode 4...... 50

xxiv

Figure 3.26. Parametric study of CCM SGI buck-boost PFC. (a) Efficiency and total power loss vs. output power. (b) Inductance and average inductor current vs. output power...... 52

Figure 3.27. Parametric study of CCM SGI buck-boost PFC. (a) Efficiency and total power loss vs. switching frequency. (b) Inductance and average inductor current vs. switching frequency...... 53

Figure 3.28. System architecture for level 2 and level 3 onboard battery chargers...... 54

Figure 3.29. SGI boost PFC with combined circuit functions. (a) Circuit diagram. (b)

Gate signals...... 55

Figure 3.30. A battery charger with fully decoupled totem-pole bridgeless PFC stage and

SGI dc/dc stage...... 56

Figure 3.31. A level 3 battery charger with a three-phase buck-type PFC and a high- power SGI switched capacitor cell ...... 56

Figure 4.1. Touch current test of an EV battery charger with SGI-based dc/dc stage..... 60

Figure 4.2. Isolation voltage across the isolated dc/dc stage in off-line power supplies with a Boost PFC circuit. (a) and (b) are during the positive half line cycle where the line input voltage is positive; (c) and (d) are during the negative half-line cycle where the line input voltage is negative...... 61

Figure 4.3. Isolation voltage across the isolated dc/dc stage in a Boost-PFC based off- line power supply when (a) ZTC is connected to the negative output terminal and (b) ZTC is connected to the positive output terminal ...... 61

xxv

Figure 4.4. Potentials of the SGI AC/DC with Totem-pole PFC based off-line power supply at positive line cycle (Vac >0), when ZTC is connected to the positive output terminal...... 63

Figure 4.5. Isolation voltage across the isolated dc/dc stage in a Totem-Pole PFC based off-line power supply when (a) ZTC is connected to the negative output terminal and (b)

ZTC is connected to the positive output terminal ...... 63

Figure 4.6. Potentials of the SGI AC/DC with Totem-pole PFC based off-line power supply at positive line cycle (Vac >0), split phase input, when ZTC is connected to the positive output terminal...... 64

Figure 4.7. Isolation voltage across the isolated dc/dc stage in a Totem-Pole PFC based off-line power supply, split phase input, when (a) ZTC is connected to the negative output terminal and (b) ZTC is connected to the positive output terminal ...... 64

Figure 4.8. Potentials of the SGI buck-boost PFC based off-line power supply at positive line cycle (Vac >0), split phase input, when ZTC is connected to the positive output terminal...... 65

Figure 4.9. CM voltage stress of SGI buck-boost PFC based off-line power supply when

ZTC is connected to the negative output terminal: a) two lines separated, b) two lines added together...... 66

Figure 4.10. CM voltage stress of SGI buck-boost PFC based off-line power supply when ZTC is connected to the positive output terminal: a) two lines separated, b) two lines added together...... 66

xxvi

Figure 4.11. Switching mode diagrams of Totem-pole PFC and basic switched capacitor

1:1 cell with ZTC connected to the positive output terminal, transition of the right cell to the left cell (a) Mode 1: right cell conducts and left cell sustains CM voltage. (b) Mode 2: deadtime. Left cell sustains CM voltage. (c) Mode 3: left cell turns on, CM leakage current is generated by charging up the right cell devices’ Coss...... 68

Figure 4.12. Leakage current waveforms of an isolated dc/dc stage in a Totem-Pole PFC based off-line power supply when ZTC is connected to the positive output terminal ...... 69

Figure 4.13. Switching mode diagrams of Totem-pole PFC and basic switched capacitor

1:1 cell with ZTC connected to the positive output terminal, transition of the left cell to the right cell (a) Mode 1: right cell conducts and left cell sustains CM voltage. (b) Mode 2: deadtime. Left cell sustains CM voltage. (c) Mode 3: left cell turns on, CM leakage current is generated by charging up the right cell devices’ Coss...... 70

Figure 4.14. The CM leakage current generation mechanism at every turn-on event: a) hard turn-on, b) ZVS on (S3 for example)...... 71

Figure 4.15. The body impedance network. (a) Circuit diagram and (b) Transfer function

(Vbodyout vs. ITC) ...... 72

Figure 4.16. The TC profile of the Totem-pole PFC and basic switched capacitor 1:1 cell with ZTC connected to the negative output terminal ...... 73

Figure 4.17. TC equivalent circuit in an SGI based off-line power supply, when a human body touches the output ground (the circuit parameters are extracted in this case study, assuming 1.7-kV SiC MOSFET C2M1000170D)...... 74

xxvii

Figure 4.18. The calculated pulse CM leakage current with different values of Coss and

Lstray at VCM=170 Vdc...... 75

Figure 4.19. A model of switched capacitor converters using equivalent resistance concept. (a) Derivation process. (b) Equivalent circuit model...... 76

Figure 4.20. TC line frequency equivalent circuit using equivalent resistance concept, assuming ReqCMtop = ReqCMbot ...... 78

Figure 4.21. Constraints on main power device output capacitance Coss, and maximum switching frequency fsw ...... 79

Figure 4.22. Simulation of TC generation mechanism of the battery charger, when ZTC is connected to the negative output terminal ...... 80

Figure 4.23. Potentials of the SGI AC/DC with Totem-pole PFC based off-line power supply at positive line cycle (Vac >0), when the output is floating ...... 82

Figure 4.24. CM equivalent circuit of the SGI AC/DC stage when the output is floating

...... 82

Figure 4.25. Simulation verification of CM voltage distribution of the SGI AC/DC stage when the output is floating ...... 83

Figure 5.1. System diagram of the desired active TC compensation structure...... 86

Figure 5.2. A system diagram of passive TC suppression methods...... 87

Figure 5.3. Low-frequency TC equivalent circuit with a CM choke...... 88

Figure 5.4. RMS values of the ZTC output voltage in the simulation of the basic SC isolation cell circuit...... 88

Figure 5.5. Low-frequency TC equivalent circuit with Y capacitors...... 89

xxviii

Figure 5.6. The transfer function of Vbodyout vs. ITC with Y capacitors...... 89

Figure 5.7. Operation waveforms (a) before and (b) after implementing the ZVS operation to prevent the TC generation [49]...... 90

Figure 5.8. Circuit diagram for the goal of CM voltage transfer through soft-switching technique...... 91

Figure 5.9. Active TC compensation techniques at every turn-on event (S3 for example).

...... 92

Figure 5.10. Waveforms and timing sequence of the active touch current compensation.

...... 93

Figure 5.11. Overview of elements in active touch current suppressions methods...... 94

Figure 5.12. Shunt active touch current compensation methods. (a) Centralized compensation. (b) Distributed compensation...... 95

Figure 5.13. CM leakage current detection methods...... 96

Figure 5.14. Compensation logic control circuit based on the sensed CM voltage...... 97

Figure 5.15. Example of a unidirectional, linear-type current source circuit [49]...... 98

Figure 5.16. The concept of CM leakage current compensation based on current-sense- feedforward control. (a) System block diagram. (b) System diagram of applying the concept to SGI switched capacitor circuit...... 99

Figure 5.17. The implementation of leakage current compensation based on current- sense-feedforward control. (a) CM current sensing using the common-mode choke. (b)

Implementation of the linear-type compensation circuit...... 99

xxix

Figure 5.18. Simulation results of the CM leakage current (a) without compensation and

(b) with current-sense-feedforward compensation...... 100

Figure 5.19. Switching-type active compensation methods (a) inductor based circuits with gate drive power supply. (b) Capacitor based energy transfer with HV DC power supply.

...... 102

Figure 5.20. An example of boost-type compensation circuit: a buck-boost converter. 102

Figure 5.21. Channel sharing structure of compensation circuits. (a) Dedicated compensation circuit. (b) Shared compensation circuit...... 104

Figure 5.22. Shared TC compensation circuit for (a) boost-type inductor based energy transfer circuit and (b) capacitor based energy transfer circuit...... 105

Figure 5.23. Buck-boost circuit for TC compensation of the Coss’s charge at turn-on transients...... 107

Figure 5.24. Operation of waveforms of the buck-boost TC compensation circuit...... 108

Figure 5.25. Required gate drive signals for the buck-boost based distributed TC compensation circuits...... 109

Figure 5.26. System diagram TC compensation control with the Main MCU...... 109

Figure 5.27. DSP registers configuration for generating TC compensation gate signals.

...... 110

Figure 5.28. Signal diagram for generating SCOM with local intelligence...... 112

Figure 5.29. Block diagram for generating SCOM with local intelligence...... 112

Figure 5.30. Signal diagram of PWM generation by encoding pulse width into the deadtime of main power device PWM signals...... 113

xxx

Figure 5.31. Block diagram of PWM generation by encoding pulse width into the deadtime of main power device PWM signals...... 113

Figure 6.1. The design procedure of SGI based power converters...... 116

Figure 6.2. Control diagram of a battery charger with fully decoupled totem-pole bridgeless PFC stage and SGI dc/dc stage...... 117

Figure 6.3. Voltage stress of switches in the dielectric voltage-withstand test when a maximum positive voltage is applied to node 1 and 3...... 118

Figure 6.4. SGI switched-capacitor cell with buck-boost based distributed compensation circuit. (a) Overal circuit diagram. (b) Each TC compensation circuit...... 120

Figure 6.5. TC local control based on CM voltage sensing and buck-boost compensation circuits...... 120

Figure 6.6. TC logic circuit to enable and select the compensation channel...... 121

Figure 6.7. Three DM current patterns including (a) the hard-switching current with a time constant much smaller than the switching cycle; (b) the hard-switching current with a time constant much larger than the switching cycle; and (c) the resonant current with

ZCS on and off [48]...... 122

Figure 6.8. Power loss model of an SGI 1:1 SC cell in hard-switching mode...... 123

Figure 6.9. Power loss model of an SGI 1:1 SC cell in soft-charging mode...... 124

Figure 6.10. DM power delivery design of a 2 kW 1:1 SC cell. (a) Power loss vs. switching frequency. (b) Efficiency and filter capacitance vs. switching frequency. .... 125

Figure 6.11. A 2 kW SGI based onboard battery charger prototype...... 126

xxxi

Figure 6.12. (a) Power stage (bottom layer) and (b) TC compensation circuit board

(middle layer) of the SGI dc/dc stage...... 128

Figure 6.13. Isolated analog signal sensing board...... 129

Figure 6.14. Waveforms of the charger at the ac side...... 130

Figure 6.15. (a) Dc/dc power stage circuit schematic. (b) Test waveforms at 450 V, 2 kW...... 130

Figure 6.16. Measured full range efficiency of the entire charger system, as well as two stages alone...... 131

Figure 6.17. TC test of SGI charger prototype with a human body impedance network.

...... 132

Figure 6.18. Experimental results of the TC measurement with and without the active TC compensation. With TC compensation, the Vbodyout is 0.23 Vrms, which meet the UL2202 requirement of 0.25 Vrms...... 132

Figure 6.19. Experimental results of the TC local control circuit response around grid voltage zero crossing. (a) 20 us/div view. (b) Zoomed in view of 4 us/ div...... 133

xxxii

Chapter 1. Introduction

1.1. Power Converters with Galvanic Isolation

According to industry safety standards (e.g., IEC60950 and UL2202), most off-line power converters are required to provide galvanic isolation. Properly implemented galvanic isolation can ensure user safety, confine common mode (CM) noise, and break the ground loop when connecting electrical subsystems with different ground references. Galvanic isolation, in general, provides voltage isolation between sub-circuit function blocks, prevents excessive common-mode (CM) current, but at the same time, allows the differential-mode (DM) energy or information be exchanged between sub-circuit function blocks.

Galvanic isolation can be realized by line frequency transformers with magnetic-filed- based coupling. Being simple and reliable, this method is widely used by many industries, especially for high-power applications. However, line frequency transformer based isolation is bulky, heavy and expensive. Such characteristics cannot meet the low cost and high- power density requirements of power conversion systems. The solution is to increase the frequency of the voltage and current that pass through the isolation barrier. It can be realized by high-frequency inverters and rectifiers. As shown in Figure 1.1, this type of approach 1

relies on power converter operating at a high switching frequency, which can reduce the required inductance or capacitance of the isolation network significantly [1]. For a given circuit topology, the required inductance and capacitance typically scale inversely proportional to the switching frequency.

Isolation Inverter Rectifier Network

Figure 1.1. A generic structure for high-frequency galvanic isolation solution.

Based on the type of isolation network applied, the existing galvanic isolation methods can be classified into three categories, i.e., magnetic-field-based solutions, electric-field- based solutions, and optical-based solutions.

Ever since the early development of isolated dc/dc converters, the magnetic-field-based solution has been the primary choice in practice. As shown in Figure 1.2, the DM power is transferred via magnetic field between separate windings of a magnetic-core or an air-core transformer, which also provides high CM impedance. Magnetic-core transformers based isolation is commonly used in high-power-density, high-efficiency isolated dc/dc converters

[2]-[23]. Air-core transformers typically have a much lower coupling coefficient They are widely used in applications including inductive heating [24], [25], wireless battery charger for portable electronics [26]-[30] and isolated gate drives [31]. However, in a lot of cases, magnetic components are large, labor-intensive, and expensive. Moreover, they are 2

responsible for a large portion of the power loss, especially for high switching frequency applications [32]-[35]. It is true that required energy storage can be reduced by increasing the switching frequency. However, the passive components size may not scale down as fast as their value does, with respect to switching frequency. The first reason is that losses of magnetic components are not linearly related to the switching frequency. Both the core loss described by Steinmetz’s equation and the winding loss calculated by Dowell’s method shows that these two losses are at least quadratic vs. the switching frequency. The second reason is the difficult in heat extraction. Increased switching frequency may result in a smaller magnetic component but also increased heat density, which makes the heat extraction more difficult. More system volume may need to be spent on the thermal management system. Therefore, due to the loss characteristic of the magnetic material, there will be a limitation in improving the power density by increasing the switching frequency.

Similar to the multi-core idea in the processor design, nowadays power converters are moving towards not only high frequency but also multi-transformer solutions. Matrix transformer is one of the promising approaches to spread the loss and heat among several cores, without using a large number of printed circuit board (PCB) layers [36].

CT1

Vin Inverter Rectifier

GND1 GND2 C T2 Figure 1.2. Magnetic-field-based galvanic isolation solution.

As an alternative approach, the electric-field-based solution is discussed in [37] and [38].

As shown in Figure 1.3, isolation is realized by capacitors between two isolated sides of the converter. The isolation capacitor could be either a pair of opposing plane electrodes [39] or a pair of Y-class capacitors [40], [41]. With the sufficiently small isolation capacitance, the low-frequency CM current can be reduced effectively, and thus the galvanic isolation requirements can be met. Meanwhile, the DM energy transfer is realized by the resonance of isolation capacitors and additional inductors. Y-class isolation capacitors, however, are usually bulky and expensive. Furthermore, an inductor is still necessary for the power stage to lower the DM impedance at the switching frequency, which is realized by a resonance.

In addition, the inverter circuit and the rectifier circuit are still required, there is no reduction of circuit stages. Thus, compared to the magnetic-field-based solution, power density improvement of the electric field-based isolation is quite limited.

LC Resonant Tank

Ls1 Cs1 Inverter Rectifier VDC Ls2 Cs2 RL

Figure 1.3. Electric field-based galvanic isolation solution.

The optical-based galvanic isolation, especially the power over fiber [42], [43], provides the smallest CM coupling capacitance. However, the power density and efficiency of this solution are far lower than those of transformer or capacitive-based solutions. This is mainly because laser transmitters and receivers are bulky and inefficient. As power density and efficiency are the key requirements for power electronic circuits, optic-based solutions are only suitable for niche applications.

To further improve the system power density and manufacturability, semiconductor- based galvanic isolation (SGI) was proposed [44]-[48]. The improvements brought by SGI are mainly enabled by the following characteristics:

1) The superior characteristics of wide bandgap (WBG) devices, including high voltage rating, low output capacitance, low switching losses and low on-resistance;

2) Energy densities of capacitors are several orders of magnitude higher than those of magnetic components [49];

3) Semiconductor switches and capacitors are easier to be integrated, thus can enhance the manufacturability of converters. As shown in Figure 1.4, not only the power density and cost, manufacturability is also a key factor in power converters. Nowadays most magnetic components are manufactured in a labor-intensive way. Moving towards semiconductor- based galvanic isolation with simpler system structure and magnetic-less design can significantly simplify the manufacturing process.

. Lower cost . Higher power density & . More manufacturable . Higher efficiency

Source: tdk-lambda.com Semiconductor Galvanic Isolation is an promising technology Source: directindustry.com

Future? Now More integration with: •Surface-mount •Simpler system structure components •Magnetic-less design Past •Planar transformers •Through-hole components •Wound coil transformers

Figure 1.4. Desired features for future power electronic converters.

1.2. Wide Bandgap (WBG) Devices

Compared to Si power devices, WBG power devices exhibits superior advantages in a number of aspects [50]-[56]. The advantages are summarized are as follows. 1) Energy

bandgap: WBG power devices have wider energy bandgaps, which result in much lower leakage currents and higher operating temperatures. 2) Critical electric field: WBG power devices have higher critical electric fields which result in a higher breakdown voltage and a lower specific on-resistance. The higher breakdown voltage leads to less number of power devices in series, less gate-drive circuits, and higher reliability. The lower on-resistance offers reduced conduction loss, improved efficiency, and less heat dissipation; 3) Electron saturation velocity: WBG power devices have higher electron saturation velocity, which leads to higher switching speed. It not only reduces the switching loss and improves the efficiency, but also enables higher operating frequencies which shrinks the passive components; and 4) Thermal conductivity: WBG power devices have a higher thermal conductivity which improves heat spreading and allows easier thermal management.

Simply replacing Silicon devices with WBG devices in existing circuit topologies and systems can improve the power density and system performance. However, it may not fully explore the potential of WBG devices. New applications and solutions with fundamentally different approaches should be investigated to improve the power converter system metrics to the next level. WBG power devices open a new door of fundamentally different solutions for realizing galvanic isolation.

1.3. Onboard Vehicle Battery Chargers

Driven mainly by reducing CO2 emissions, reducing operating cost and improving the driving experience, interest is growing rapidly in electric vehicle (EV) and plug-in hybrid electric vehicle (PHEV) [57]. However, battery cost, range limit and charging time are still three main factors that limit with widespread of EV and PHEV. A lighter, more efficient and high-power battery charger can alleviate the above concerns. During the charging process, batteries of EVs and PHEVs usually acquire power from the grid through an onboard or off-board battery charger. The charger converts ac voltage from the grid to a stable dc voltage to charge the vehicle battery. Being an off-line power supply, the battery charger also requires galvanic isolation to prevent users and service personnel from electric shock. Required by industrial standards such as UL2202, EVs and PHEVs’ high voltage systems are galvanic isolated from the vehicle chassis, including the high-voltage battery, dc-dc converter, inverter for driving the electric motor. However, during the charging process, the vehicle chassis is required to be tied to the earth ground. Therefore, the battery charger needs to provide galvanic isolation between the ac input and dc output [58]. The most widely used system structure of onboard battery chargers is shown in Figure 1.5. The first stage, power factor correction (PFC), is used to convert ac grid voltage into a stable dc voltage while achieving a good power factor and a low total harmonic distortion (THD).

The PFC stage is also able to regulate the dc output voltage in the battery charging process.

Stage two consists of an inverter, a transformer, and a rectifier. The main function of this

stage is to provide isolation and a small range of voltage regulation. However, the isolation is realized at the expense of lower efficiency, lower power density, and higher system complexity.

Stage 1 Stage 2

CT1

EMI HV Grid PFC Inverter Rectifier filter Battery

CT2

Figure 1.5. System diagram of current onboard vehicle battery chargers.

According to SAE J1772 definition, AC charging can be separated into three levels, depending on the power rating and grid voltage, as shown in Table 1.1.

Table 1.1. Electrical rating of AC EV chargers Level Voltage Current Power AC level 1 120 Vac,rms 16 Vac,rms 1.92 kW AC level 2 204-240 Vac,rms 80 Vac,rms 19.2 kW AC level 3 n/a n/a >20 kW

Nowadays a number of companies offer onboard battery charger products for PHEVs and EVs. An overview is shown in Figure 1.6. Most of the chargers are in a power rating range of 3 kW to 6 kW with efficiency between 90% and 96 %. The highest power density is around 28 W/inch3. Isolation solution used are mostly the conventional transformer-based multi-stage solution. 9

On-Board Chargers: Efficiency v.s Power Density (Commercial Products in Year 2016) 96 95.5

95 94 94 93 93 93 92 92 92

Efficiency(% ) 91 Power Density 27 W/in3 90 90 Power Density 4.92 W/in3 89 0 5 10 15 20 25 30 Power Density(W/in3)

(a) On-Board Chargers: Efficiency vs. Power Rating (Commercial Products in Year 2016) 96 95.5

95 94 94 93 93 93 92 92

92 Efficiency Efficiency (% ) 91 90 90

89 3 3.5 4 4.5 5 5.5 6 6.5 7 Power Rating (kW)

(b) Figure 1.6. Selected onboard charger commercial products in 2016. a) Efficiency vs. power density. b) Efficiency vs. power rating.

In the academic side, recent research and development of onboard battery chargers focus on multiples aspects to achieve higher efficiency and power density of the charger [59]-[73].

Recent efforts are summarized are as follows. 1) New topologies: new circuit topologies have been proposed to reduce device conduction loss, to increase zero-voltage switching

(ZVS) operating range and to shrink the size of passive components. 2) Application of WBG devices: SiC and GaN devices have been applied to enable a significant increase of switch frequency thus smaller converter size. 3) Reduction of dc-link capacitance: researchers have made large efforts to reduce the dc-link capacitance in order to achieve a higher power density and to avoid using an electrolytic capacitor for a longer lifetime. Typical approaches such as sinusoidal charging and harmonic modulation are quite effective in reducing the required dc-link capacitance. Up to date, most of the research is still focusing on system structures that are similar as shown in Figure 1.5, which utilizes multiples stages and transformer to realize galvanic isolation.

On-Board Chargers: Efficiency vs. Power Density (Selected Prototypes from Year 2010 to 2016) 100

96 Arkansas Power Electronics 94 International, Inc, 2014

Efficiency (%) Efficiency 92

88 0 10 20 30 40 50 60 70 80 90 Power Density (W/in3)

(a) Figure 1.7. Selected Onboard charger prototypes in academia from the year 2010 to 2016. a) Efficiency vs. power density. b) Efficiency vs. power rating 11

Continue:

Virginia Polytechnic Institute and State University, 2013

Liverpool John Moores Chonbuk National University,2016 c University (South Myongji University, Korea), 2014 2016 North Carolina State University, 2010

Sungkyunkwan University (Korea), 2013

Fudan University (China) &Delta, 2016

(b)

1.4. Motivations of this Work

From the earlier discussion, it is evident that the power electronics industry is moving towards a higher power-density and higher efficiency at a lower cost and a smaller footprint. As a fundamentally different approach, semiconductor-based galvanic isolation could utilize the unprecedented properties of WBG devices to achieve the above goals.

However, there are still several challenges in this new technology. Therefore, this dissertation aims to develop a comprehensive view of the principle, safety requirement, suitable circuit topologies and design guidelines of SGI based power converters. Onboard vehicle battery charger is used for a target application for a system demonstration. It should be noted that all the developed theories can be applied to most SGI based power converters.

1.5. Outline of this Dissertation

This dissertation is divided into seven chapters as follows:

In Chapter 2, an overview of the industrial safety requirement on galvanic isolation is presented, including the insulation voltage and touch current requirements. The principles of semiconductor-based galvanic isolation are explained. Benefits and challenges of SGI are highlighted.

In Chapter 3, a family of SGI building block circuits is discussed. The SGI concept can be applied to realize galvanic isolation for variety of applications, including dc/dc, ac/dc, and dc/ac power conversions. Among these above three categories, SGI based dc/dc cells are basic building blocks for various topologies. Focusing the onboard vehicle battery charger, several SGI circuit candidates are discussed. These circuits are compared in terms of system complexity, power loss, and suitable power ratings.

Chapter 4 discusses an interesting problem, the CM leakage current generated during the high-frequency switching of the SGI dc/dc stage. The discussion starts from the isolation voltage stress on the SGI dc/dc stage, which varies for different ac/dc, dc/dc topologies, as well the grounding scheme of the grid. The generation mechanism of the touch current is explained. A high-frequency model and a low-frequency model are developed to describe the behavior of the touch current. Finally, the isolation voltage stress in the scenario where a floating dc output is discussed.

In Chapter 5, the TC compensation methods and their implementation are discussed. To reduce the touch current, it is preferred to have smaller Coss and fsw. However, such constraints greatly limit the converter power density. Therefore, TC suppression method is preferred. To reduce the touch current, several passive suppressions methods are discussed first. To implement more effective TC compensation, a compressive discussion of active compensation methods is presented. A design example is shown at the end of this chapter.

Chapter 6 presents the design considerations of SGI based Power Converters. With onboard battery charger as a target application, design guidelines of galvanic isolation and differential-mode power delivery are discussed. A 2 kW SGI based battery charger prototype is presented. Test results of DM power delivery and touch current tests are shown.

Chapter 7 summarizes the dissertation and provides an outlook of the future work.

Chapter 2. Semiconductor-based Galvanic Isolation

This chapter first presents an overview of the industrial safety requirements on galvanic isolation, including the insulation voltage and touch current requirements. The principles of semiconductor-based galvanic isolation are explained. Benefits and challenges are also highlighted.

2.1. Overview of Safety Requirements

Isolated power converters must meet the safety standard requirements to validate their galvanic isolation capability. There are varieties of standards specifying requirements for different applications. UL2202 is for electric vehicle charging systems. IEC 60950-1 is intended for information technology equipment. There are also other standards, such as IEC

60065 is for audio and video, IEC 60601 for medical, and IEC 61010 for laboratory supplies.

However, they share similar requirements. Taking UL2202 as an example, two tests have been defined to validate the equipment safety. They are the dielectric voltage-withstand test and the touch current test.

2.1.1. Insulation Voltage Requirement

Five categories of insulation are defined in IEC60950, including:

1) Functional insulation, which is only necessary for the proper circuit operation. It

is assumed to provide no safety protection.

2) Basic insulation, which provides basic protection against electric shock with a

single level. Safety is provided by the second level of protection such as

Supplementary insulation or protective earth.

3) Supplementary insulation, which normally is used in conjunction with Basic

insulation to provide a second level of protection in the event that the Basic level

fails.

4) Double insulation, which is a two-level system, usually consisting of Basic

insulation plus Supplementary insulation.

5) Reinforced insulation, which is a single-insulation system equivalent to Double

insulation.

Electric circuits rely on insulation to protect users and operators. The insulation design follows the logic that anything can fail, thus one level insulation redundancy is required. It is based on the fact that the chance of two simultaneous failures in the same spot is so low that it represents an acceptable risk. Therefore, accessible components must be insulated from hazardous voltages by a Double-level system. If the circuit is not accessible by user and operator, a single level of insulation is acceptable.

Safety standards also define circuits of different categories and their corresponding insulation requirements:

1) Class I Equipment: Systems which use protective earthing (e.g., a grounded metal

enclosure) as one level of protection and thus require only Basic insulation

between the enclosure and any part at hazardous voltage.

2) Class II Equipment: The use of Double or Reinforced insulation to eliminate the

need for a grounded metal enclosure as well as a grounded power plug.

3) Class III Equipment: Powered from a safety extra-low voltage (SELV) source (≤

42.4 Vpk, ac or 60 Vdc) with no potential for generation of hazardous voltages

internally, and therefore, requiring only functional insulation.

Safety standards usually require equipment to pass the dielectric voltage-withstand test.

This test evaluates the equipment’s insulation with a high CM voltage. In Figure 2.4, a transformer based isolated dc/dc converter is utilized as an example to illustrates the test. A single-phase ac input with TN distribution system is considered. During the test, a CM test voltage is applied between either node in the primary and secondary side circuitry, which are node 1 and 3, 2 and 3, 2 and 3, and finally 2 and 4. In UL2202, the test voltage specified for power circuits is one thousand volts plus twice the maximum rated voltage in the circuit.

The test waveform is a 60 Hz sinusoidal. The converter needs to sustain the test voltage at the maximum operating temperature for one minute without breakdown. For the transformer based isolation, the winding-to-winding insulation sustains the high CM voltage during the

test. However, in the SGI solution, this CM voltage is sustained by semiconductor switches.

As the CM test voltage is usually higher than the DM voltage in the converter operation, the switch voltage rating in SGI based converters is usually determined by the dielectric voltage-withstand test requirement.

CT1

1 3 PFC & Rectifier Inverter 2 4 Floating secondary circuit CT2

Figure 2.1. Schematic of the dielectric voltage-withstand test.

2.1.2. Touch Current and Protective Conductor Current Requirement

In IEC60950, touch current (TC) is defined as the electric current through a human body when it touches one or more accessible parts. Leakage current test or touch current test provides an overall evaluation of the effectiveness of galvanic isolation. Touch current is defined as the electric current through a human body when it touches one or more accessible parts. The human body can be modeled as the artificial passive network, as shown in Figure

2.2. As shown in Figure 2.3, if the circuit’s output is unearthed, the current through the human body is "leakage" through stray capacitance across the isolation stage, which is the transformer in Figure 2.3. During the touch current test, the circuit is in operation and the

TC is measured with a body impedance network (ZTC), which simulates a human body. In 18

Figure 2.3, the bridge rectifier inherently generates a time-varying CM voltage and applies across the isolation barrier. The generated CM voltage also depends on where the ZTC’s node

A is connected to, either 3 or 4. The touch current ITC is determined by Vout/500. In UL2202, the touch current limit is 0.5 mA for 2-wire cord or 3-wire plug-connected portable unit.

For 3-wire plug-connected fixed unit, the TC limit is 0.75 mA.

0.22 µF 1.5 k A 10 k

B 500 22 nF Vout

Figure 2.2. TC measuring instrument: an impedance network to roughly simulate a human body [74].

+ Isolated  Bridge Vac dc/dc  R + Rectifier L 1 2 Converter 4 ITC B A

ZTC (Body Impedance)

0.22 µF 1.5 k A ITC =Vout/500 10 k B 22 nF Vout (of ZTC)

Figure 2.3. Schematic of the leakage current or touch current test.

2.2. Principles of Semiconductor-based Galvanic Isolation

2.2.1. Basic Principle

The semiconductor-based galvanic isolation utilizes semiconductor switches to realize isolation. SGI solution delivers the DM power via semiconductor power switches during their ON states, while blocking the CM leakage current during their OFF states. This idea is illustrated in Figure 2.4 (a). A bipolar CM voltage is assumed for a general analysis; therefore, semiconductor switches need to withstand bidirectional voltage. As shown in

Figure 2.4 (b), for bi-directional power flow, the switch can be built with two active devices in an anti-series configuration. For unidirectional power flow, an active switch with a diode can be utilized. The basic operation principle of SGI converters is illustrated in Figure 2.4

(c). Switches need to be employed for both positive and negative rails of the circuit to achieve isolation. Typically, there are two operating modes in SGI converters. In the first mode, the DM energy is transferred from the input dc source to a temporary energy storage element. Meanwhile, the load side is isolated from the input side with barrier capacitances.

The barrier capacitances are formed by the output capacitances of the semiconductor switches. Similarly, in the second mode, the DM energy is transferred from the temporary energy storage element to the load. At the same time, the input side is isolated from the load with another pair of barrier capacitances. Therefore, at any given moment, there is no direct low impedance connection between the input and the output of the circuit, realizing galvanic isolation.

Mode 1

Energy Barrier Caps When the ac switch is When the ac switch is ON: OFF: Input Energy DC Load COSS Source

Temporary Energy Storage DM current CM leakage current Mode 2

(a) Barrier Caps Energy

Bi-directional power flow Uni-directional power flow

Input Energy DC Load Source

Temporary Energy Storage (b) (c)

Figure 2.4. (a) The basic idea of the SGI technology. (b) Examples of the ac switches in anti-series connection. (c) A generic system diagram of SGI

The simplest SGI dc/dc cell is shown in Figure 2.5 (a). It is realized by adding two switches, S2 and S4, in the basic 1:1 switched capacitor (SC) circuit. The circuit operation principle is explained as follows. As highlighted in Figure 2.5 (b) and (c), two pairs of switches in the left cell and right cell operate complementarily. S1 and S2 is one pair, while

S3 and S4 is the other pair. VCM, A generic CM voltage source, is assumed to be applied to two sides of the converter, which is usually generated by a bridge rectifier. It shows that, at any time, the converter has at least one pair of switches remained off. The switches turned- off serve to sustain the CM isolation voltage and their output capacitance limits the CM leakage current.

S1 S3 + + Cmid Cout Vin

S2 S4 DM current in the first half switching cycle DM current in the next half switching cycle

(a) Mode I Mode II

Coss_S3 Coss_S1 + + + + Vin IDM Cmid Cout Vin Cmid IDM Cout

Coss_S4 Coss_S2

VCM ITC VCM ITC

ZTC (body Impedance) ZTC (body Impedance)

DM current in the 1st half switching cycle DM current in the 2nd half switching cycle Line-frequency CM touch current Line-frequency CM touch current

(b) (c) Figure 2.5. SGI based SC 1:1 cell. (a) Circuit schematic. DM and CM current flows in (b) mode I, and (c) mode II.

2.2.2. Potential Benefits

The SGI solution is fundamentally different from the traditional solutions. It expands the function of semiconductor power devices to not only DM power delivery but also galvanic isolation. Potential benefits of this technology can be summarized as follows:

1) Simpler system structure. SGI can achieve direct isolated dc/dc conversion with a reduced number of circuit stages. It yields significant circuit topology simplification, the potential for efficiency improvement and cost reduction;

2) The potential for significant improvement of power density. The simpler system structure, higher energy density of capacitors and less number of magnetic components offer tremendous potential for a further improvement of power density;

3) Easier for integration and better manufacturability. Instead of applying transformer for isolation, the SGI based converter utilizes capacitors and semiconductor devices, which makes it a better candidate for integration. Additionally, a more integrated system with a less labor-intensive assembly process can improve the manufacturability, which can also benefit performance improvement and cost reduction.

In summary, SGI based power converters can potentially achieve better performance, higher power density, higher efficiency and better manufacturability with a lower cost.

2.2.3. Challenges

Being a drastically different approach in realizing isolation in power conversion, the

SGI solution looks simple. However, there are also several challenges.

One of key challenge is to reduce the CM leakage current to meet the touch current requirement and achieve high efficiency as well as high power density at the same time.

The high-frequency switching of semiconductor devices generates certain CM leakage current, which is decided by the switching frequency and output capacitance of the device.

To implement high-frequency and high-power SGI based converters, TC compensation technique is needed. As shown in Figure 2.6, throughout the past several years, SGI technology has gone through several development stages [46]-[49], from demonstrating the concept to identifying and modeling the CM leakage current, and finally meeting the industrial safety requirements. Cf is the temporary energy storage capacitance shown in

Figure 2.5 (c), which is mainly decided by the converter power rating and switching frequency.

102

Year 2014 )

101 RMS

Year 2015 400 W 0 10 fs = 1 kHz UL2202 Touch Current Limit: 0.5 mA Year 2017 2 kW -1 Year 2016 f = 120 kHz 10 400 W s

TouchCurrent (mA fs = 8 kHz

10-2 10-8 10-7 10-6 10-5 10-4 10-3

Energy Storage Capacitor, Cf (F)

Figure 2.6. The development map of semiconductor-based galvanic isolation.

The second challenge is the converter’s voltage transfer ratio and voltage regulation.

Without the help from a transformer to realize a turn ratio, the SGI based SC circuit inherently has a voltage transfer ratio of one. This challenge is addressed by stacking basic

SC cells together to form discrete voltage gains. A small range of voltage regulation can be realized by modulating the switching frequency of the SC resonant tank, which sacrificed the efficiency. If a continuous voltage gain adjustment or a larger range of voltage regulation is needed, an inductor has to be implemented in the circuit, leading to a larger loss.

The third challenge is a fundamental challenge of semiconductor devices. It is usually difficult to design a power device with a high voltage blocking capability, low on-resistance as well as low output capacitance. The low breakdown voltage limits the isolation voltage rating. The high on-resistance limits the efficiency of the circuit. The high output capacitor provides a low impedance path for the CM mode current. Therefore, to further expand the scope of SGI solutions, new and better semiconductor power devices are needed.

2.3. Conclusions

The safety requirement specified by the safety standards are discussed. Basically, two isolated sides of the converter need to sustain several kV voltages that are depending on the working voltage of the converter. This is to ensure the insulation coordination of the

converter. The touch current test is an ultimate test to evaluate the converter’s isolation performance. The touch current is essential a CM leakage current, which needs to be below certain limit when tested with an artificial human body impedance.

The basic principle of semiconductor-based galvanic isolation is to use semiconductor switches’ output capacitance to isolate two sides of the circuit when the switches are off.

When they are on, DM power can still be delivered from the primary side to the secondary side circuit. It means both the CM current block and DM power delivery are handled by the semiconductor switch. With proper selection of semiconductor switches, SGI based power converter could satisfy the safety standards.

Potential benefits of the SGI technology are 1) simpler system structure, 2) the potential for significant improvement of power density and easier for integration and better manufacturability. In summary, SGI based power converters can potentially achieve better performance, higher power density, higher efficiency and better manufacturability with lower cost.

However, there are still several challenges in the SGI technology, including 1) CM leakage. 2) Voltage transfer ratio and voltage regulation, 3) as well as requirements of high- performance high-voltage devices.

Chapter 3. A Family of SGI Based Circuit Topologies

The SGI concept can be applied to various power conversion applications to realize galvanic isolation, including dc/dc, ac/dc, and dc/ac power conversions. Among the above three categories, SGI based dc/dc cells are the basic building blocks for various topologies.

In this chapter, a family of SGI building block circuits is presented. Focusing the onboard vehicle battery charger, several SGI based circuit candidates are discussed. These circuits are compared in terms of system complexity, power loss, and suitable power ratings.

3.1. SGI Building Blocks: Dc/dc cells

The simplest SGI dc/dc cell is illustrated in Figure 2.5 (a), which is a 1:1 switched capacitor circuit with ac isolation switches. Similarly, with slight modifications in the traditional circuit topologies, three more SGI based dc/dc cells can be derived, as shown in

Figure 3.1. The buck-boost converter shown in Figure 3.1 (b) is modified by adding S2 and

S4 to achieve galvanic isolation. If the converter is operated in continuous conduction mode

(CCM), S5 is applied to allow inductor’s freewheeling current during the dead time. With additional switches, S2, S3, and S4, isolated setup-down dc/dc conversion can be realized with

the modified buck converter, as shown in Figure 3.1 (a). Similarly, the traditional boost converter can be modified by adding S2, S3, and S4, as shown in Figure 3.1 (c).

S1 S3 + + Vin Cout Cmid

S2 S4 (a) L

S1 S3 S1 S3 + + Vin L Cout C + Vin SB Cmid out S5

S2 S4 S2 S4 (b) (c)

DM current in the first half switching cycle DM current in the next half switching cycle Inductor free-wheeling current during the dead time

Figure 3.1. SGI building blocks: dc/dc cells (a) SGI based buck cell. (b) SGI based buck- boost cell in CCM operation. (c) SGI based boost cell.

If a dc/dc cell is preferred to operate with a fixed voltage ratio, namely a dc transformer

(DCX), traditionally switched capacitor topologies can be modified to incorporate the SGI concept [49]. For example, by stacking up these building blocks, an isolated converter with a 3X voltage transfer ratio is derived, as shown in Figure 3.2. Following this idea, advanced

Switched-capacitor (SC) circuits can also be modified to achieve galvanic isolation. For example, the Dickson converter can be modified into an isolated dc/dc converter, as shown in Figure 3.3.

S1 S3 Mode 1  C C  1 2 Vin C1 C3 C5

S2 S4

S5 S7 Mode 2 C C 3 4 RLoad C1 C2

Vin S6 S8

C C 3 4 RLoad S9 S11

C5 C6

S10 S12 (a) (b) Figure 3.2. (a) A 3X isolated boost dc/dc converter (where all switches are ac switches with bidirectional blocking). (b) The two operation modes of the converter [49].

  C2

S2 S3

L s S5 S6 S7 S8 S10 Switches w/ S S unidirectional AC AC 1 4 blocking Switches Switches C4 Cout RLoad

C1 C3

S9 S11 (a)

Mode 1 Mode 2  C C  3 2 C1 Ls Cout RLoad Ls C4 Cout RLoad

C2 C4 C1 C3

(b)

Figure 3.3. (a) A 4X isolated Dickson converter, and (b) the equivalent circuits of the two operation modes [49]. 29

3.2. SGI based Ac/dc and Dc/ac Topologies

With the proposed SGI dc/dc cells, the SGI concept can be applied to both ac/dc and dc/ac power conversion systems. Combining a diode bridge with any SGI based dc/dc cells discussed in the previous section, SGI based single-phase PFC circuits can be derived as shown in Figure 3.4 (a). For instance, an SGI buck PFC circuit can be derived as in Figure

3.4 (b) by plugging in the SGI based buck cell. Similarly, Boost and buck-boost PFC are realized by implement corresponding SGI cells. The three common modulation methods, continuous conduction mode, critical conduction mode and discontinuous conduction mode, can all be achieved with topologies proposed above.

S1 S3 SGI + Cmid + Cout Cout Vac dc/dc cells

S2 S4

(b) (a) Figure 3.4. SGI based single-phase PFC circuits. (a) A generic circuit diagram with SGI dc/dc cells. (b) SGI based buck PFC.

Bridgeless PFC circuits are becoming increasingly popular due to their higher efficiency and fewer component count. The boost-type bridgeless PFC can be constructed by connecting a totem-pole PFC circuit with a 1:1 SGI based SC circuit, as shown in Figure

3.5 (a). A bridgeless buck PFC modified based on [75] is shown in Figure 3.5 (b). DM current flow of two circuits is highlighted for the positive line cycle. For both circuits, S1 to 30

S5 are CM voltage rated ac switches. In Figure 3.5 (a), SA1 and SA2 are DM voltage rated

MOSFETs.

S1 S3 S1 S4 SA1 L C1 C1 C Vac 2 + + Cout Vac Cout S3

SA2 C2

S2 S4 S2 S5 L2 DM current in the first half switching cycle DM current in the next half switching cycle (a) (b) Figure 3.5. SGI based bridgeless PFC circuits. (a) Bridgeless boost PFC. (b) Bridgeless buck PFC.

Isolated dc/ac converters can also be designed with a two-stage structure, combining an

SGI based dc/dc cell with a traditional inverter, as shown in Figure 3.6.

SGI based  V Inverter Vac DC dc/dc cells 

Figure 3.6. SGI based dc/ac converter with a two-stage structure.

3.3. Topology Candidates for Onboard Battery Chargers

3.3.1. AC Level 1 Chargers: SGI Critical Conduction Mode (CrM) Buck-boost Converter

With semiconductor isolation technology, the system structure of vehicle battery charger can be significantly simplified, which consists of an EMI filter stage, a diode bridge, and an

SGI based buck-boost converter, as shown in Figure 3.7. With high switching frequency, a

single stage EMI filter could be enough. The second part, in shaded red, is a multifunction stage. It realizes power factor correction, galvanic isolation, and voltage regulation. The average inductor current can be controlled to follow a sinusoidal current command to realize

PFC. To achieve isolation between two sides, energy is temporarily stored in the inductor and then transferred to the battery. In any operating stages, the two sides are isolated by switches’ output capacitances on two rails. During a battery charging profile, the output voltage can be stepped up or down by the buck-boost converter to realize voltage regulation.

As such, ac switches are used for all four switches to allow bi-directional voltage blocking.

S1-S4 function for both differential mode power delivery and common-mode voltage blocking.

CrM PFC, Galvanic Isolation & Voltage Regulation EMI Filter S1 S3 LDM LCM

(Lk) CY1 + Vac CX Cin L Cout + CY2

S2 S4

DM current in the first half switching cycle DM current in the next half switching cycle

Figure 3.7. Circuit diagram of the SGI critical conduction mode Buck-boost converter based vehicle battery charger.

a) Operation mode analysis

The switching frequency is much higher than the line voltage frequency. At any given grid voltage phase angle, the input voltage can be considered as a DC voltage source. The 32

operation principle of this topology is very similar to the traditional buck-boost converter, except that six more semiconductor switches are added for the isolation purpose. As shown in Figure 3.8, devices in a shaded blue function similar as the active device in the traditional buck-boost converter. Devices in a shaded red function resemble the diode in the traditional buck-boost converter. Four devices in shaded green do not withstand any DM voltage during normal power delivery. Instead, they isolate the input and output sides of the circuit during the dead time.

Topology-wise: Similar to Buck-Boost Coss

S11 S12 S31 S32

D DM power delivery + + DC Cin & Galvanic Isolation L Cout RLoad DC Cin L Cout RLoad + + S S S S 21 22 41 42 Galvanic isolation

(a) (b) Figure 3.8. Comparison of (a) SGI buck-boost converter and (b) traditional buck-boost converter

The gate signals of the converter are analyzed to realize DM power delivery, zero-voltage switching (ZVS) of S11 and S22, as well as galvanic isolation, as shown in Figure 3.9. S11 and S22 are grouped together to control the inductor peak current, whose on-time are varying

rd in a line cycle to achieve a sinusoidal peak current. S31 and S42 are conducting in 3 quadrant when the inductor current goes to the right-hand SGI cell. Their on-time can also be extended to expand the ZVS of the S11 and S22, as shown in the shaded yellow area. S12, S21, 33

and S32, S41 are controlled such that they 1) allow DM current and resonance current to conduct, as well as 2) ensure the input and output stage remain disconnected at any time.

As shown in Figure 3.9 (a), the turn-on signal of S12 and S21 aligns with the turn-off S31 and

S42, which allows the resonance current between the inductor and device output capacitance

(Coss) to pass. S12 and S21’s turn-off is aligned with S11 and S22 to cut off the connection from the input to the inductor and output. The control of S32 and S41 follows the same principles.

Vgs_S11 &S22

For ZVS extension t Vgs_S31 &S42 t Vds_S1 Vgs_S12 &S21 S11 S12 S31 S32 t Vgs_S11 Vgs_S32 + DC Cin IL &S41 L Cout RLoad + t IL S21 S22 S41 S42 Iac

t Vds

t1 t2 t3 t4 t5 t6 t

(a) (b)

Figure 3.9. (a) Gate signals and circuit diagram of SGI buck-boost converter. (b) Circuit diagram the signal annotations.

Three typical operation modes, mode 1, mode 2 and mode 3 are shown to illustrate how the required gate signals are derived. The mode 1, [t1, t2], circuit schematic with current flow annotation is shown in Figure 3.10. The left-hand cell should be controlled such that the inductor current in dashed red line can flow. Therefore, S11 and S22 have to be on. S12 and S21 can be either on or off but on is preferred to reduce the body diode conduction loss.

In the right-hand cell, S31 and S42 support the DM voltage stress. S32 and S41 can be either on or off in terms of DM circuit operation. However, they need to be off for the isolation purpose. Results are summarized in Table 3.1.

S11 S12 S31 S32 Required gate signals:

ON + DC Cin Load current IL L C Better to be ON out RLoad + OFF S S S S Does not matter 21 22 41 42

Mode 1:[t t ], S1 ON 1, 2

Figure 3.10. Schematic of the SGI buck-boost CrM PFC in mode 1 [t1, t2].

Table 3.1. Status and control signal of devices in mode 1 [t1, t2]. Device Operation mode Required control signal Preferred control signal st S11 & S22 1 quadrant conduction ON rd. S12 & S21 3 quadrant conduction ON or OFF ON

S31 & S42 Blocking forward voltage OFF

S32 & S41 Not able to block voltage ON or OFF OFF

Mode 2 [t2, t3]. The circuit schematic and required gate signals are shown in Figure 3.11 and Table 3.2. This is dead time mode where the inductor is resonating with the Coss of S11,

S22, S31, and S42. S32 and S41 have to be on to allow the current flow in the right-hand cell.

S12 and S21 are preferred to be on for conduction loss consideration. It should be noted that in this mode, both two cells are conducting. However, this does not break the galvanic isolation because it is just the high-frequency resonance current. The impedance at line frequency or DC is still very high due to the switch output capacitance. This high-frequency current is equivalent to the high-frequency CM current of a transformer-based isolation converter.

S11 S12 S31 S32

Required gate signals: ON + DC Cin IL L Cout RLoad Better to be ON + OFF S21 S22 S41 S42 Does not matter

Mode 2:[t t ], S1 OFF, Dead Time 2, 3

Figure 3.11. Schematic of the SGI buck-boost CrM PFC in mode 2 [t2, t3].

Table 3.2. Status and control signal of devices in mode 2 [t2, t3]. Device Operation mode Required control signal Preferred control signal

S11 & S22 Coss charging up OFF rd. S12 & S21 3 quadrant conduction ON or OFF ON

S31 & S42 Coss discharging OFF st S32 & S41 1 quadrant conduction ON 36

Mode 5 [t5, t6]. The circuit schematic and required gate signals are shown in Figure 3.12 and Table 3.3. This is dead time mode where the voltage of S11 and S22 have dropped to zero and the inductor current continue to flow through their body diodes. So S12 and S21 have to be on before the inductor current flips the direction. The right-hand cell still remains off.

S11 S12 S31 S32

Required gate signals: ON + DC Cin IL L Cout RLoad Better to be ON + OFF S21 S22 S41 S42 Does not matter

Mode 5:[t t ], Dead Time 5, 6

Figure 3.12. Schematic of the SGI buck-boost CrM PFC in mode 5 [t5, t6].

Table 3.3. Status and control signal of devices in mode 5 [t5, t6]. Device Operation mode Required control signal Preferred control signal rd. S11 & S22 3 quadrant conduction ON or OFF ON st S12 & S21 1 quadrant conduction ON

S31 & S42 Blocking forward voltage OFF

S32 & S41 Not able to block voltage ON or OFF

To verify the analysis of circuit operation and gate signals, a simulation is conducted.

The simulation parameters are listed in Table 3.4. The simulation was conducted at Pout =

70 W to be compatible with earlier power loss model developed for power adapter applications. As shown in Figure 3.13 (a), the ac side current Iac has achieved a sinusoidal

profile. The output voltage Vbulk is also realized with a 390 V average value. The zoomed- in views are shown in Figure 3.13 (b). The gates of all devices are controlled based on earlier analysis, the CrM operation of the inductor current is achieved. S11 and S22 also achieve ZCS for the turn-on.

Table 3.4. Simulation parameters for verifying the CrM SGI buck-boost converter operation. Item Description Specifications Vac Line input voltage 120 Vac, rms, 60 Hz Vbulk Output voltage 390 V Pout Output power 70 W fsw Switching frequency 1 – 2 MHz

(a) (b)

Figure 3.13. Simulation results of the SGI buck-boost CrM vehicle charger. (a) Line frequency waveforms. (b) Switching frequency waveforms.

b) Power loss analysis

Being a buck-boost PFC, the proposed circuit can realize both stepping up and stepping down voltage. It essentially combines PFC, voltage regulation, and isolation functions into a single circuit stage. However, the benefits are gained at the expense of higher voltage and current stress, which leads to lower efficiency. Therefore, this system architecture is not suitable for high power vehicle chargers. The inductor current comparison of boost and buck-boost PFC are compared in Figure 3.14. To achieve the same average rectified ac side current (Iac), A boost PFC’s inductor peak current is

III2 (3-1) L__ peak ac L valley

Where IL_valley is the inductor valley current shown in Figure 3.14.

In contrast, the inductor peak current of a buck-boost converter is typically larger, which is

VVin out IIIL__ peak2 ac   L valley (3-2) Vout

The larger inductor peak current means higher RMS current and higher switch turn-off loss. In addition, as shown in Figure 3.15, the DM voltage stress of devices is also higher in the buck-boost converter. However, this is not affecting the circuit design and power losses because the voltage rating the semiconductor devices is typically governed by isolation voltage requirement, which is usually higher than Vin + Vout.

Iac-avg Iac-avg

Inductor Current (IL)

Inductor Current Peak(IL_peak)

Inductor Current Valley (IL_valley)

Rectified Input Current (Iac)

Boost Our Topology VV III2 III2 in out  L__ peak ac L valley L__ peak acV L valley out Figure 3.14. Comparison of inductor waveforms in boost and buck-boost PFCs.

Cj Iac Iac L S11 S12 S31 S32

D IL IL Vds +C DC RL DC in Cx Coss Cbulk L Cout RLoad Vgs +

S21 S22 S41 S42

Voltage stress on Vin S11/S22: (Vin+Vout)/2 main switches

ON: V /L Inductor current (IL) in ON: Vin/L slope OFF: (Vin-Vout)/L OFF: -Vout/L VV Iac and IL in out IIIL__ peak2 ac L valley IIIL__ peak2 ac   L valley relationship Vout C Inductor valley I VV  C L _valley L in out IL _valley Vout  (IL_valley) current L 1 ZVS condition VV VV in2 out in out

Input and switch RMS current increase drastically.

Figure 3.15. Comparison of other key metrics boost and buck-boost PFCs.

To understand the power limitation of the CrM operation in SGI buck-boost PFC topology, a comprehensive power loss model is developed. The conduction and switching loss at each grid voltage angle is first calculated analytically. Then by integrating the losses over a full line cycle numerically, the converter total power loss can be obtained [70], [71].

The conduction loss can be separated into a 1st quadrant and 3rd quadrant devices. Typical current waveforms and switching conducting status are shown in Figure 3.16 and Table 3.5, respectively. Every two devices have been grouped together as they always conduct simultaneously. Majority of current waveform shape is triangular. Thus, at each grid voltage angle θ, the RMS current can be calculated as

f () 22 I1st _ rms I 3 rd _ rms [ t 14 I L _ peak ( )  t 46 I L _ valley ( )] (3-3) 3

Where t14 and t46 are switching mode duration and can be calculated based on mode-by- mode differential equations. More details can be found in [70], [71].

1st Quadrant Conducting Current 3rd Quadrant Conducting Current (Current goes through different switches) (Current goes through different switches)

IL_peak S11/S22 IL_valley S31/S42

S12/S21 -IL_valley t t S32/S41 - IL_peak t1 t2 t3 t4 t5 t6 t1 t2 t3 t4 t5 t6 (a) (b)

Figure 3.16. Current waveforms of SGI buck-boost PFC. (a) First quadrant devices. (b) Third quadrant devices.

Table 3.5. Switches conducting status in CrM SGI buck-boost PFC.

Switches Mode 1 [t1,t2] Mode 2 [t2,t3] Mode 3 [t3,t4] Mode 4 [t4,t5] Mode 5 [t5,t6] S11/S22 1st / / / 3rd S31/S42 / / 3rd / / S12/S21 3rd 3rd / 1st 1st S32/S41 / 1st 1st 3rd /

To determine the switching losses, the transition voltages and currents between each mode are analyzed in Figure 3.17. The analysis shows that 1) S31/S42 have soft turn-on and turn-off, 2) S12/S21 and S32/S41 do not support any noticeable voltage, 3) switches losses distribution among different devices are not uniform as the conduction loss.

S11 S12 S31 S32 Dominant switching loss

I: IL_peak -> 0 L I: almost 0 S21 S22 S41 S42 Vds: 0; ZVS(by Vds: 0 -> VStress resonance)

I: -IL_peak -> 0 I: O ZCS; Vds: 0; ZVS(body diode ) Vds: 0-> VStress; Switches Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 S11/S22 ON OFF OFF OFF ON Turn OFF S31/S42 OFF OFF ON OFF OFF S12/S21 ON ON OFF ON ON Turn ON S32/S41 OFF ON ON ON OFF

I: -IL_peak -> 0 I: almost 0; Vds: almost 0 Vds: almost 0; I: 0 -> IL_peak I: almost 0; Vds: almost 0 Vds: almost 0 Figure 3.17. Switching voltage and current of CrM SGI buck-boost PFC in different mode transitions.

A single case power loss analysis was conducted for a 240 Vac,rms input, and 1.3 kW charger. A 1.7 kV, 45 mΩ SiC MOSFETs from Wolfspeed (C2M0045170D) is used in the study. The inductor current and switching frequency over a half line cycle are shown in

Figure 3.18. To achieve an ac side input peak current of around 7 A, an inductor peak current of around 35 A is required. As mentioned earlier, this is due to the combined effects of buck- boost topology and CrM operation. Major power losses over a half line cycle are shown in

Figure 3.19. The curves of conduction losses in 1st quadrant and 3rd quadrant switches overlap under the orange line. They are the highest ones among all other losses. The average power loss of the entire converter is 89 W, which means the efficiency is 93.58% for the 1.3 kW vehicle charger.

(a) (b)

Figure 3.18. Calculated a) switching frequency and b) inductor current of CrM SGI buck- boost PFC in the half line cycle.

Figure 3.19. Calculated power losses of CrM SGI buck-boost PFC in the half line cycle.

To understand the power limitation of this topology and modulation strategy, a parametric sweeping was conducted for the output power of the CrM SGI buck-boost PFC.

The inductance of the buck-boost converter is adjusted such that a minimum switching frequency of 100 kHz is maintained. The Figure 3.20 (a) shows that the total power loss increases significantly at higher power, which leads to drastically decrease of converter efficiency. For example, it would be difficult for this converter to run at 3.3 kW because each MOSFET need to handle around 35 W of loss and efficiency is lower than the state- of-art chargers at the similar power rating. Again, this is mainly caused by the drastically increased peak and RMS inductor current, as shown in Figure 3.21.

In summary, the CrM SGI buck-boost converter vehicle charger is suitable for AC level

1 charger. It enables simple circuit structure, reduced number of circuit stages and competitive system efficiency.

Efficiency and Total Ploss Ploss Breakdown

1.3 kW

3.3 kW

(a) (b)

Figure 3.20. Parametric study of efficiency and power loss vs. output power of CrM SGI buck-boost PFC. (a) Converter efficiency and total power loss. (b) Breakdown of major power losses.

Figure 3.21. Parametric study of input RMS current and inductor RMS and peak current vs. output power of CrM SGI buck-boost PFC. 45

3.3.2. AC Level 1 and 2 Chargers: SGI Continuous Conduction Mode (CCM) Buck-boost

Converter

As discussed in the previous section, buck-boost PFC has a higher voltage and current stresses on semiconductor devices. And CrM operation makes the current stress even worse.

One approach can be used is to replace CrM with CCM operation, which can reduce the inductor peak current by half. The circuit schematic is shown in Figure 3.22. And an additional pair of free-wheeling current switches S5 is needed.

CCM PFC, Galvanic Isolation & Voltage Regulation EMI Filter S1 D1 D S3 LDM LCM 3

(Lk) CY1 + Vac CX Cin L S5 Cout + CY2

D2 S2 S4 D4

DM current in the first half switching cycle DM current in the next half switching cycle Inductor free-wheeling current during the dead time Figure 3.22. Circuit diagrams of the CCM SGI buck-boost vehicle charger.

a) Operation mode analysis

The two PWM strategies are being compared in terms of the circuit structure, circuit control, power loss, and leakage current.

Circuit structure. With CCM, as shown in Figure 3.22, ac switches in anti-series connection can be simplified into a switch in series with a diode, which directly results in

simpler gate drive circuitry and lower cost. Meanwhile, S5 is needed to work during the dead time to provide a path for inductor free-wheeling current. With CrM, S5 is not needed as the inductor current goes to zero at every switching period, however, two switches in anti-series connection are still needed to allow the bi-directional resonance current.

Gate control. As shown in Figure 3.22, for CCM, only three gate signals with fixed frequency are required. S1 and S2 share the same gate signal. S3 and S4 share the same gate signal. S5’s gate signal is a NOR of the other two signals. For CrM, four pairs of gate signals are needed. Signals are generated based on inductor zero current detection and on-time control, which is a variable frequency and more difficult to generate.

Power loss. To deliver the same power, CCM can achieve much less conduction loss due to the reduced RMS current. However, the excessive turn-on loss limits its switching frequency. On the other hand, CrM can almost eliminate switch turn-on loss thus operates at a higher frequency. A smaller inductance value can be used at the expense of higher peak current and RMS current.

CM leakage current. Essentially the leakage currents of these two modulation strategies are the same. The average TC model to be discussed in the following chapter shows that, due to body impedance network’s filtering effect, leakage current’s average value matters, rather than the peak value. In CrM, due to the ZVS turn-on, the peak leakage current is smaller, however, the average value remains the same due to the same total energy.

The circuit operation principle of a CCM buck-boost PFC is very similar to a CCM buck- boost converter, except that the inductor current has no free-wheeling path during the dead time. Therefore, an additional free-wheeling mode is added, as shown in Figure 3.23 (b).

S11 S12 S31 S32 S5 added for free wheeling purpose.

S11 S12 S31 S32 + S5 Cin L Cout Vin + S11

+ S5 Cin L Cout Vin +

S21 S22 S41 S42 ON S21 S22 S41 S42 OFF Mode 1: [t1, t2] Mode 2: [t2, t3] (a) (b)

S11 S12 S31 S32 S11 S12 S31 S32

+ + S5 S5 Cin L Cout Cin L Cout Vin + Vin +

S21 S22 S41 S42 S21 S22 S41 S42

Mode 3: [t3, t4] Mode 4: [t4, t5] (c) (d)

b) Power loss analysis

A power loss model is also developed for the CCM operation. Based on the circuit operation waveforms shown in Figure 3.24, the switches conduction and switching losses are shown in Figure 3.25. Conduction losses patterns are similar as CrM operation, except

that the RMS current is smaller. For the switching loss, the 1st quadrant devices incur both turn-on and turn-off loss. The 3rd quadrant devices incur reverse recovery loss. The free- wheeling switch S5 incur both turn-on, turn-off and reverse recovery loss.

Vgs S11/S22

Ids S11/S22

Vgs S31/S42

Ids S31/S42

Vgs S5

Ids S5

t1 t2t3 t4 t5

deadtime S31/S42 turn ON delay: discharge Coss to realize ZVS turn on S31/S42 early turn OFF, body diode conducts, RR loss Figure 3.24. Typical waveforms of CCM SGI buck-boost vehicle charger.

t1 - t2 S11 S12 S31 S32

L S5

S21 S22 S41 S42

S11/S22: conduction loss(1st), (hard) switching loss; S12/S21: conduction loss(3rd).

(a) t3 – t4 S11 S12 S31 S32

L S5

S21 S22 S41 S42

S31/S42: conduction loss(3rd), switching loss (ZVS turn-ON, Body diode RR loss); S32/S41: conduction loss(1st).

(b) t2 – t3 S11 S12 S31 S32 t4 – t5 L S5

S21 S22 S41 S42

S5: conduction loss(1st and 3rd), switching loss.

(c) Figure 3.25. Conduction and switching losses in each mode and mode transition. (a) Mode 1. (b) Mode 2. (c) Mode 3 and mode 4.

A case study is evaluated at 3.3 kW, fs = 100 kHz and 15 % inductor current ripple.

Results are shown in Table 3.6. The conduction losses are evenly distributed among different groups of devices, except for the free-wheeling device. Similar to CrM operation, the switching losses are also not the same for different devices. Other losses in the converter are around 50 W, which results in a total power loss of 390 W and an efficiency of 89.42 %.

The power losses and efficiency are compared among CCM with different ripple current as 50

well as CrM operation, as shown in Table 3.7. CrM operation can be considered as an extreme CCM operation with 200% inductor current ripple. The trend shows that, with 100 kHz switching frequency, smaller current ripple means higher efficiency. However, it should be noted that it is at the expense of a higher inductance value.

Table 3.6. Switches power losses in SGI CCM buck-boost vehicle charger. Switches Cond. loss Sw. loss Total S11/S22 37.76 W × 2 21.86 W × 2 59.62 W × 2 S12/S21 37.76 W× 2 / 37.76 W × 2 S31/S42 31.75 W × 2 2.81 W × 2 34.56 W × 2 S32/S41 31.75 W × 2 / 31.75 W × 2 S5** 5.96 W 6.81 W 12.77 W Total 284 W 56.16 W 340.16 W

Table 3.7. Power losses in SGI CCM buck-boost vehicle charger with different inductor ripple current. Op. Cond. Sw. Loss on Other Total η Inductance Mode loss loss switches losses* loss 56.16 390.61 134 uH @ 15% CCM 284 W 340.16 W 50.45 W 89.42% W W ripple 306.26 51.25 415.64 40 uH @ CCM 357.51 W 58.13 W 88.76% W W W 50% ripple 382.81 46.73 516.06 CrM 429.54 W 86.52 W 86.48% 22.5 uH W W W

To understand the power limitation of the SGI CCM buck-boost PFC, a parametric study was conducted for the output power and switching frequency. The inductance of the buck- boost converter is adjusted such that a switching frequency of 100 kHz is maintained. The

Figure 3.26 (a) shows that the total power loss increases at higher power, but not as fast as

the previous CrM case. This is because the average inductor current only increases linearly with respect to the output power, as shown in Figure 3.26 (b). A parametric study of switching frequency at 3.3 kW output power is conducted, show in Figure 3.27. The efficiency drops linearly with respect to the switching frequency. To achieve an efficiency close to 90%, the switching frequency cannot go above 100 kHz that much.

In summary, the CCM SGI buck-boost converter vehicle charger is suitable for AC level

1 and 2 chargers, which switching frequency around and less than 100 kHz to achieve high efficiency. It enables simple circuit structure, reduced number of circuit stages and competitive system efficiency.

500 95 25 500 ) ) A (

H t

94 u n (

400 e ) e r 20 400 ) c r W n u % (

93 a (

C s t

s 300 y c r o c u o n t L d 92 e c 15 300 i n r u c I e

i d

200 f d w f n e o I t

91 E P a e g

10 200 m a 100 i t r

90 s e v E A 0 89 5 100 1000 1500 2000 2500 3000 1000 1500 2000 2500 3000 Output Power (W) Output Power (W)

Total Power Loss Diode Operation: Total Power Loss Avg. Inductor Current Efficiency Estimated Inductance Diode Operation: Efficiency (b) (a)

Figure 3.26. Parametric study of CCM SGI buck-boost PFC. (a) Efficiency and total power loss vs. output power. (b) Inductance and average inductor current vs. output power.

600 89 25 40 ) ) A (

H t u

n 35 (

88 e 24.5 e r ) 550 c r ) n u W % (

30 a ( C t

s c s

87 r 24 y u o c o t d n L

500 c 25 e n i r u I

c e d i d

86 f 23.5 w n e f I o t

E 20 a e P g

450 m a i t 85 r 23 s e 15 v E A 400 84 22.5 10 1 1.5 2 2.5 3 1 1.5 2 2.5 3 Switching Frequenct (Hz) 105 Switching Frequenct (Hz) 105

Total Power Loss Diode Operation: Total Power Loss Avg. Inductor Current Efficiency Estimated Inductance Diode Operation: Efficiency

(a) (b)

Figure 3.27. Parametric study of CCM SGI buck-boost PFC. (a) Efficiency and total power loss vs. switching frequency. (b) Inductance and average inductor current vs. switching frequency.

3.3.3. AC Level 2 and above Chargers: PFC stage and Switched-capacitor Cell

In the earlier two topology candidates. PFC, galvanic isolation and voltage regulation are handled by a single SGI stage, which significantly simplifies the system structure. However, it is not suitable for higher power systems due to the large power loss. This is because the

HV devices need to sustain DM voltage stress during the operation. To solve this problem, a different system architecture is proposed for higher power SGI power conversion systems, as shown in Figure 3.28. In this architecture, the PFC circuit handles the PFC and voltage regulation functions. The SGI DCX circuits handle the galvanic isolation function. This

structure is similar to replacing an LLC resonant converter with an SGI based DCX circuit.

In this case, the SGI DCX stage has no DM voltage stress when the output is floating, which achieves high efficiency during normal operation. When the output is faulted to the ground by a user, the SGI DCX switches sustain the CM voltage.

Bridge/  DCX with Bridgeless Semiconductor- Vac  RLoad PFC Circuit based Isolation

Figure 3.28. System architecture for level 2 and level 3 onboard battery chargers.

When a PFC stage is used, it is possible to combine circuit functions. A boost PFC plus

SGI switched capacitor circuit example is shown in Figure 3.29. In this circuit, the left cell of the SGI cell (S11, S12, S21, and S22) also works as the diode in the boost PFC, which means they sustain the DM voltage. However, the right-hand cell only sustains CM voltage stress when it is presented. As shown in Figure 3.29 (b), in the first mode, energy is transferred from the grid to the inductor. Meanwhile, energy is transferred from Cmid to Cout. In the second mode, energy is transfer from the inductor to the Cmid. A dead time is inserted between these two modes so galvanic isolation is always achieved.

CCM PFC, Galvanic Isolation & Voltage Regulation EMI Filter S11 S12 S31 S32 LDM LCM L

(Lk) CY1 + + + CX SB Cmid Cout Cin CY2

S S22 S41 S42 21 (a)

S11/S22

S12/S21

S31/S42 S32/S41

t t0 t1 t2 t3 t4 t5 6 (b) Figure 3.29. SGI boost PFC with combined circuit functions. (a) Circuit diagram. (b) Gate signals.

When an even higher power charger is required, it is beneficial to fully decouple the PFC stage from the SGI dc/dc stage. An example is shown in Figure 3.30. A GaN-based totem- pole PFC is used to minimize power losses and also to enable high switching frequency.

The SGI dc/dc stage works independently to transfer energy from the Cin to Cout. Meanwhile, there is no DM voltage stress on the SGI dc/dc stage so high efficiency can be achieved.

GaN Based Totem-pole PFC SiC based SGI DC/DC Converter EMI Filter S11 S12 S31 S32 LDM LCM

SHF1 D1 (Lk) CY1 L1 A  V C Cmid ac X Cin B  CY2

SHF2 D2

S21 S22 S41 S42

PFC & Voltage Regualtion Galvanic Isolation Figure 3.30. A battery charger with fully decoupled totem-pole bridgeless PFC stage and SGI dc/dc stage.

A level 3 battery charger can also be achieved by utilizing a three-phase buck-type PFC and a high-power SGI switched capacitor cell, as shown in Figure 3.31. A case study is evaluated for a 50 kW, 40 kHz SGI dc/dc stage, as shown in Table 3.8. With a 1.7 kV, 250

A SiC power modules, an efficiency of 93.52% is expected by the power loss model.

S1 S3

ICf  Step-down three- V in Cf Vout R phase rectifier  Load

S2 S4 Figure 3.31. A level 3 battery charger with a three-phase buck-type PFC and a high- power SGI switched capacitor cell

Table 3.8. Parameters for a case study of a 50 kW SGI switched-capacitor dc/dc stage. Item Description Specifications Vac Line input voltage, three-phase 480 Vac, rms Vout Output voltage 0-587 V Pout Output power 50 kW fsw switching frequency 40 kHz/ hard switching S1 – S4 Power devices Rohm 1.7 kV, 250 A (BSM00015A) Eff Calculated efficiency 93.52%

3.4. Conclusions

The SGI concept can be applied to traditional circuit topologies to realize semiconductor based galvanic isolation. SGI dc/dc building blocks including (a) SGI based buck cell. (b)

SGI based buck-boost cell and (c) SGI based boost cell can be derived from the traditional buck, boost, and buck-boost converter. The traditional switched capacitor can be also easier modified to incorporate the SGI function. Applying the above dc/dc cells to ac/dc and dc/ac topologies, SGI PFC, SGI bridgeless PFC and SGI inverters can be derived.

Using onboard charger as an example, the selection of SGI topologies for different ac/dc power levels is discussed. SGI CrM buck-boost PFC is more suitable to lower power rating due to higher voltage and current stress on the HV devices. Using CCM modulation, the

SGI buck-boost PFC can expand the power level to around 2 – 3 kW, depending on the power device. For power rating higher than 2 kW, it is better to separate the PFC stage and

SGI dc/dc stage for higher efficiency. The PFC can be single phase or three phases,

controlling the power rating and regulating the bus voltage. Without the DM voltage stress, the SGI stage can achieve a higher efficiency.

Chapter 4. Generation Mechanism of CM Leakage Current in Semiconductor-

Based Galvanic Isolation

This chapter discusses an interesting problem, the CM leakage current generated during the high-frequency switching of the SGI power converters. This topic starts from the isolation voltage stress on the SGI stage, which varies for different ac/dc, dc/dc topologies, as well the grounding scheme of the grid. The generation mechanism of the touch current is explained. A high-frequency model and a low-frequency model are developed to describe the behavior of the touch current. Finally, the isolation voltage stress in the scenario where a floating dc output is discussed.

4.1. Overview

Isolated power converters must meet safety standard requirements to validate their galvanic isolation. Touch current test provides an overall evaluation of the effectiveness of galvanic isolation, as shown in Figure 4.1. In UL2202, the touch current is defined as the electric current goes through a human body when it touches one or more accessible parts.

During the touch current test, the circuit is in operation and the TC is measured with an impedance network (ZTC), which simulates a human body. The touch current ITC is

determined by Vout/500, whose limit is 0.5 mA for 2-wire cord or 3-wire plug-connected portable unit and 0.75 mA for 3-wire plug-connected fixed unit.

CCM

+ Semiconductor-  Active/Diode IDM Vac based Isolated  RL + Rectifier DC/DC Converter

CCM B ITC A 1 2 ZTC (Body Impedance) DM current for power delivery 0.22 µF 1.5 k Line-frequency CM touch current A measured by ZTC 10 k

B 22 nF Vbodyout ITC =Vbodyout/500

Figure 4.1. Touch current test of an EV battery charger with SGI-based dc/dc stage.

4.2. Isolation Voltage Stress

In off-line power supplies, the bridge rectifier generates time-varying potentials for the dc/dc primarily side circuit. In the case of a Boost PFC front-stage, the dc-link ground rail at the primary side has the earth potential during the positive half line cycle where the line voltage is positive, as shown in Figure 4.2 (a) and (b). In the negative half-line cycle where the line voltage is negative, the dc-link ground rail has the line voltage, as shown in Figure

4.2 (c) and (d). On the secondary side of the isolated dc/dc stage, depending on where the

ZTC is connected to, the earth potential is applied to either the output positive or negative

rail. The resulting isolation voltage stress across the dc/dc stage is shown in Figure 4.3, which is the same for both the top and bottom rails.

+ Vcm - + Vcm - Vdc Vdc Vdc GND

L (+) L (+)

Isolated  Isolated DC/DC Vac DC/DC Vac  RL RL N Stage N Stage

GND GND GND -Vdc + Vcm - + Vcm -

GND GND

ZTC ZTC (a) (b)

+ V - + V - Vac+Vdc cm Vdc Vac+Vdc cm GND

L (-) Isolated L (-) Isolated

Vac DC/DC RL Vac DC/DC RL N Stage N Stage

Vac (<0) GND Vac (<0) -Vdc + Vcm - + Vcm -

GND GND

ZTC ZTC

(c) (d) Figure 4.2. Isolation voltage across the isolated dc/dc stage in off-line power supplies with a Boost PFC circuit. (a) and (b) are during the positive half line cycle where the line input voltage is positive; (c) and (d) are during the negative half-line cycle where the line input voltage is negative.

Vdc

Vac

Vac VCM 0 t 0 t

VCM -Vdc

(a) (b) Figure 4.3. Isolation voltage across the isolated dc/dc stage in a Boost-PFC based off- line power supply when (a) ZTC is connected to the negative output terminal and (b) ZTC is connected to the positive output terminal 61

The time-varying potentials depend on the AC/DC stage circuit topology, DC/DC stage circuit topology, and AC source grounding configuration. Several examples are illustrated below are show the difference.

4.2.1. Impact of AC/DC Stage Circuit Topology

The front stage circuit topology affects the dc-link capacitor voltages with respect to the ground potential. A Totem-pole PFC stage is used as an example to compare with the Boost

PFC stage shown in Figure 4.2. Potentials of the SGI AC/DC with Totem-pole PFC based off-line power supply at positive line cycle (Vac >0). During the positive line cycle, potentials of the SGI AC/DC with Totem-pole PFC is shown in Figure 4.4. The SLF2 highlighted in red is always conducting, thus the negative rail of the dc bus is tied to the earth. As a result, the positive rail potential is Vdc. A similar analysis can be applied to the case when Vac <0 and when ZTC is connected to the negative output terminal. Therefore, the isolation voltage stress of Totem-Pole PFC based SGI converters is shown in Figure 4.5.

The resulted isolation voltage profile is different from Boost-PFC topology.

EMI Filter Vdc S11 S12 S31 S32 LDM LCM Lf GND + Vbody L SHF1 SHF3 SLF1 (Lk) CY1 L1 A  V Cmid ac CX C  in

CY2 N SHF2 SHF4 SLF2 -Vo + Vbody

S21 S22 S41 S42 GND

Vbody

ZTC Figure 4.4. Potentials of the SGI AC/DC with Totem-pole PFC based off-line power supply at positive line cycle (Vac >0), when ZTC is connected to the positive output terminal.

Vdc

Vac

VCM 0 t 0 t

VCM Vac

-Vdc

(a) (b)

Figure 4.5. Isolation voltage across the isolated dc/dc stage in a Totem-Pole PFC based off-line power supply when (a) ZTC is connected to the negative output terminal and (b) ZTC is connected to the positive output terminal

4.2.2. Impact of AC Source Grounding Configuration

Earlier studies consider the case of a 120 V single-phase TN distribution system, where the neutral line is connected to earth. When a split phase input is used, the circuit node potentials are showed in Figure 4.6. In this case, the negative rail of the dc bus is connected

to half the ac voltage, which is not fixed anymore. Similarly, the isolation voltage profiles can be derived and are shown in Figure 4.7.

+ Vcm - EMI Filter -½ |Vac| +Vdc S11 S12 S31 S32 LDM LCM Lf GND + Vbody SHF1 SHF3 SLF1 (Lk) C ½ Vac Y1 L1  A Cmid CX C V in  dc ½ Vac CY2

SHF2 SHF4 SLF2 -Vo - Vbody

S21 S22 S41 S42 -½ |Vac|

Vbody GND ZTC Figure 4.6. Potentials of the SGI AC/DC with Totem-pole PFC based off-line power supply at positive line cycle (Vac >0), split phase input, when ZTC is connected to the positive output terminal.

Vdc Vdc -½ Vac Vac

t -½ Vac 0 t 0 -½ Vac

Vac

-Vdc ½ Vac - Vdc (a) (b)

4.2.3. Impact of DC/DC Stage Circuit Topology

SGI based buck-boost PFC stage is used here to illustrate the impact. Taking positive line cycle as an example as shown in Figure 4.8, due to the different polarity of CM voltage stress on the top and bottom line, the resulted CM leakage currents are in opposite directions.

It means a certain degree of TC cancellation is realized. This fact can be modeled by considering two lines together to form an equivalent CM circuit, 2VCM = VCMtop + VCMbot. As shown in Figure 4.9, the addition of two CM voltages holds only if output capacitances of two lines are symmetrical. After the analysis, 2VCM is a sinusoidal voltage with an amplitude of Vac, the offset of -Vout, as illustrated with the green curves. A similar analysis can be applied to the case when ZTC is connected to the positive output terminal, as shown in Figure

4.10.

+ Vcm -

S1 S3 LDM LCM |Vac| GND + Vbody

(Lk) CY1 + Cout Vac CX Cin L Vout RLoad +

CY2

GND Vo S2 S4

Vbody

GND ZTC

Figure 4.8. Potentials of the SGI buck-boost PFC based off-line power supply at positive line cycle (Vac >0), split phase input, when ZTC is connected to the positive output terminal.

Vac Vac

t t 0 0 VCMtop -Vout -Vout

VCMbot 2VCM

(a) (b)

Figure 4.9. CM voltage stress of SGI buck-boost PFC based off-line power supply when ZTC is connected to the negative output terminal: a) two lines separated, b) two lines added together.

2VCM Vout Vout VCMtop

Vac

Vac t t 0 0 VCMbot

(a) (b)

Figure 4.10. CM voltage stress of SGI buck-boost PFC based off-line power supply when ZTC is connected to the positive output terminal: a) two lines separated, b) two lines added together.

In summary, this section proves that the isolation voltage stress needs to be analyzed for different AC/DC stage circuit topology, DC/DC stage circuit topology and AC source grounding configuration. The isolation voltage stress profile is critical in determining the

CM leakage current and TC suppression methods.

4.3. Generation Mechanism of the Touch Current

With isolation voltage stress applied across with SGI dc/dc stage, CM leakage current is generated due to the high-frequency switching. The fundamental reason that SGI solutions having a large CM leakage current is that the CM barrier capacitors are changing locations due to high-frequency switching. However, in the magnetic field and electrical-field based solutions, the CM barrier capacitors are at fixed locations.

When one of the dc/dc stage output is connected to ZTC or touched by a human body standing on the earth, the SGI dc/dc stage should sustain almost all the CM voltage. The profile of this CM voltage is analyzed in the previous section.

The Totem-pole PFC and basic switched capacitor 1:1 cell converter in Figure 4.4 is used as an example. This analysis assumes the ZTC is connected to the positive output terminal, as the CM voltage profiles shown in Figure 4.5 (b). The switching mode diagrams covering the conduction of right cell to the left cell are shown in Figure 4.11. The potentials with respect to the earth are highlighted at the input and output terminals in blue. In the mode 1, the right cell is conducting, transferring energy from the middle capacitor to the output. Two left side devices in shaded red are sustaining the CM voltage. In the mode 2, which is also the dead time, the right cell devices are turned off. The DM current becomes zero. And the voltage sustained by the right cell is typically small, being VCmid - Vout.. In the mode 3, the left cell devices are turned on and energy stored in the Coss is dissipated in the device channel.

Meanwhile, the external CM voltage source charges the Coss two right cell devices, in shaded 67

red. As a result, CM leakage current is generated. Generic waveforms of the positive line

Vgs, Vds, touch current is shown in Figure 4.12. A similar analysis is conducted for the transition from left cell to the right cell, as shown in Figure 4.13. The TC generation mechanism is similar that it happens during the turn-on of a pair of devices that used to sustain the CM voltage.

+ Vdc - VdsS31=0 + Vdc - VdsS31=0

S12 S S S Vdc 32 GND Vdc 12 32 GND

S11 S31 S11 S31 

Cmid Cmid

S22 S42 S22 S42

GND -Vo GND -Vo S21 S41 S21 S41

+ Vdc - VdsS41= 0 + Vdc - VdsS41= 0

(a) (b)

VdsS11: Vdc -> 0 VdsS31: 0-> Vdc

S S Vdc 12 32 GND

S11 S31 CM leakage Cmid current

S22 S42

GND -Vo S21 S41

VdsS21: Vdc -> 0 VdsS41: 0-> Vdc

(c) Figure 4.11. Switching mode diagrams of Totem-pole PFC and basic switched capacitor 1:1 cell with ZTC connected to the positive output terminal, transition of the right cell to the left cell (a) Mode 1: right cell conducts and left cell sustains CM voltage. (b) Mode 2: deadtime. Left cell sustains CM voltage. (c) Mode 3: left cell turns on, CM leakage current is generated by charging up the right cell devices’ Coss.

Vac& Vdc Vcm

Vac VCM

0 t Dead time

Vgs_S1

ON ON

Vgs_S3 ON ON ON

Vds_S1 Vdc

S1 ON S1 ON

Vds_S3 Vdc

S3 ON S3 ON

I TC Safety standard: LF RMS to be less than 0.5 mA (UL2202)

Figure 4.12. Leakage current waveforms of an isolated dc/dc stage in a Totem-Pole PFC based off-line power supply when ZTC is connected to the positive output terminal

VdsS11=0 VdsS11=0 + Vdc - + Vdc -

S12 S S12 S32 Vdc 32 GND Vdc GND

S11 S31 S11 S31 

Cmid Cmid

S22 S42 S22 S42

GND -Vo GND -Vo S21 S41 S21 S41

+ Vdc - + Vdc - VdsS21= 0 VdsS21= 0

(a) (b)

VdsS11: 0-> Vdc VdsS31: Vdc -> 0

S12 S Vdc 32 GND

S11 S31

Cmid

S22 S42

GND -Vo S21 S41

VdsS21: 0-> Vdc VdsS41: Vdc -> 0

(c) Figure 4.13. Switching mode diagrams of Totem-pole PFC and basic switched capacitor 1:1 cell with ZTC connected to the positive output terminal, transition of the left cell to the right cell (a) Mode 1: right cell conducts and left cell sustains CM voltage. (b) Mode 2: deadtime. Left cell sustains CM voltage. (c) Mode 3: left cell turns on, CM leakage current is generated by charging up the right cell devices’ Coss.

Based on previous analysis, a generic circuit diagram shown in Figure 4.14 can be used to describe the CM leakage current generated at every turn-on transient. Figure 4.14 (a) assumes a hard-switching on, and the turn-on transient of S3 is shown. The leakage current, highlighted in red, is used to charge up the output capacitance of S1 that is turning off. The energy stored in the output capacitance of S3 gets dissipated when it turns on. A similar 70

process occurs during the turn-on transient of S1. Thus, this CM pulse current repeats at the twice of the switching frequency. The analysis here also applies to the negative rail of the converter that contains S2 and S4. Similar, Figure 4.14 (b) shows of the transient when a third quadrant conducting device is turned on with zero voltage switching (ZVS). The generated touch current profile is smoother than the hard-switching case. However, the average touch current stays the same as the charge needed to charge up the device Coss is the same.

TC TC HS ZVS

COSS discharged C C COSS energy gets C C OSS OSS dissipated OSS OSS by load current

V1 V2

S : OFF S : ON S : OFF S3: delayed 1 Touch Current 3 1 Touch Current for ZVS on Vds_S3 Vds_S1 Vds_S1 Vds_S3 Vds_S3 VCM VCM

ZTC (body Impedance) ZTC (body Impedance)

(a) (b)

Figure 4.14. The CM leakage current generation mechanism at every turn-on event: a) hard turn-on, b) ZVS on (S3 for example).

The high-frequency CM pulse current flows through the body impedance network or a human body. However, high-frequency harmonics are greatly attenuated due to the low bandwidth of the body impedance network, as shown in Figure 4.15. The transfer function of Vbodyout vs. ITC shows a bandwidth of around 700 Hz and a DC gain of 54 dB. Starting from 10 kHz, the gain becomes around 30 dB, which is around 16 times smaller. As a result,

the Vbodyout mainly measures the low-frequency harmonics of the ITC, as the purple shown in Figure 4.16.

ITC B A

ZTC (Body Impedance) ITC 0.22 µF 1.5 k A 10 k

B 500 22 nF Vbodyout

(a)

Transfer Function (Vbodyout vs. ITC)

|ZTC|

Low gain at high frequency e d e u t s i

Phase a n h g P a M

Frequency

(b) Figure 4.15. The body impedance network. (a) Circuit diagram and (b) Transfer function (Vbodyout vs. ITC)

Vac Vbodyout t 0

VCM ITC -Vdc

Figure 4.16. The TC profile of the Totem-pole PFC and basic switched capacitor 1:1 cell with ZTC connected to the negative output terminal

4.4. Modeling of the Touch Current

In this section, high-frequency pulse current model and low-frequency average current model are developed to describe the transient and average behavior of the touch current in

SGI solutions.

4.4.1. High-frequency Pulse Current Model [48]

The CM leakage current generation process can be described by the equivalent circuit shown in Figure 4.17. The Coss of both positive and negative rail devices are charged up by the equivalent CM voltage source VCM. For analyzing the pulse TC (ITC), the loop stray inductance (Lstray) and switch output capacitance (Coss) all have zero initial conditions, and the CM isolation voltage is applied as a step input. The pulse CM leakage current at every turn-on event with an ideal step input voltage is described in (4-1).

Converter equivalent circuit as the TC path

60 nH 30 pF ~3

Lstray Coss Rds_on+Rstray

VDM C2 or C3 60 nH 30 pF ~3

Lstray Coss Rds_on+Rstray

0.22 µF 1.5 k VCM 10 k

ITC 500 22 nF Vbodyout

Human-body impedance (ZTC)

tR    t  2Coss(2CossR  2Lstray) 2V e Lstray  sinh   2C (2C R  2L ) CM  2L C  oss oss stray  stray oss  (4-1) ITC (t)  2C R2  2L oss stray ,

Where VCM is the magnitude of the CM voltage source at the turn-on moment; Lstray is the loop stray inductance; Coss is the switch output capacitance; and R is the total series loop resistance including the loop stray resistance (Rstray), the switch on-resistance (Rds_on), and the 500-Ω resistance in the human body impedance (ZTC).

The plots of the ICM with different values of Coss and Lstray are shown in Figure 4.18. It can be seen that: 1) larger Coss causes larger energy and RMS value of the ICM, and thus is

not preferred; 2) larger Lstray increases the loop CM impedance and thus damps the ICM. It reduces the peak current, but it doesn’t help reducing the RMS value of the ICM, when the switching cycle is much larger than the circuit time constant.

0.35

0.3

0.25 C = 30 pF, L = 60 nH 0.2 oss stray Coss = 300 pF, Lstray = 60 nH

Coss = 3 nF, Lstray = 60 nH (A)

0.15

CM Coss = 30 pF, Lstray = 600 nH I

ITC (A) 0.1 Coss = 30 pF, Lstray = 6 uH Coss = 30 pF, Lstray = 60 uH 0.05

-0.05

-0.1 0 0.5 1 1.5 2 t (s) -7 t (s) x 10

Figure 4.18. The calculated pulse CM leakage current with different values of Coss and Lstray at VCM=170 Vdc.

4.4.2. Low-frequency Average Current Model

The high-frequency pulse current model can accurately describe the high-frequency current profile. However, it is difficult to derive the analytical expression for the Vbodyout’s

RMS value in the line cycle based on this model. As a result, it is difficult to determine the allowed device Coss and switching frequency for meeting the touch current requirement. To overcome this problem, a low-frequency average current model is proposed. This low-

frequency model utilizes equivalent resistance concept of switched capacitor circuits. It is proposed based on the fact that the high-frequency pulse current is filtered by the body impedance network ZTC, which has a bandwidth of around 700 Hz. Therefore, the output voltage Vou is dominated by line frequency components. Only the low-frequency average touch current needs to be considered to calculate Vbodyout. As shown in Figure 4.19, the charging of capacitors at a fixed frequency can be molded as a resistor, ReqCM.

COSS energy COSS dissipated in CM leakage discharged by C C COSS C OSS the channel OSS current OSS load current

V1 V2 V1 V2

S1: ON S3: OFF S1: OFF CM leakage S3: delayed Vds_S1 current for ZVS on Vds_S3

(a) (b)

ReqCM V1 V2

(a) SGI dc/dc stage

ReqCM

ITC

V ZTC (body Impedance) CM (b) Figure 4.19. A model of switched capacitor converters using equivalent resistance concept. (a) Derivation process. (b) Equivalent circuit model.

The derivation process of the low-frequency average current is shown as follows.

Considering one line, two Coss charging process happens in one period. Assuming the same

Coss of two devices, thus the charge required can be calculated as

QCVV 2oss  (12  ). (4-2)

The equivalent average current is

ICVVavg2 oss  fsw  ( 1  2 ). (4-3)

Therefore, the equivalent resistance of CM blocking capacitors is

VV 1 R 12 . eqCMsin gle IC2f (4-4) avg oss sw

If two lines of the converter are considered together, the average TC model is illustrated in the left picture of Figure 4.19. If the same switches are used for top and bottom lines, the

CM model of the left can be simplified into the one on the right, where

RR 1 R eqCMtop eqCMtop (4-5) eqCM 2 2 4C f oss sw

VVCMtop CMbot VCM  (4-6) 2

ReqCMtop ReqCM

ReqCMbot

VCMtop VCMbot ITC1 + ITC2 ITC

ZTC (body Impedance) V ZTC (body Impedance) CM Figure 4.20. TC line frequency equivalent circuit using equivalent resistance concept, assuming ReqCMtop = ReqCMbot

As a result, the high-frequency switching has been averaged to only consider the low- frequency touch current component. It clearly shows that a large ReqCM is required to limit the touch current. Ignoring other CM impedances in the loop, the touch current and ZTC output voltage at any given VCM can be calculated as

V () I ()  CM TC 1 Z(60 Hz )  (4-7) TC 4fC  oss sw V () VI( ) 500  500  CM out TC 1 Z  (4-8) TC 4fC  oss sw

where  is the phase angle of the grid voltage and ZTC (60 Hz ) is body impedance network’s impedance at 60 Hz. The RMS value of Vout can also be easier calculated by plugging in the RMS value of VCM in (4-8).

With the proposed equivalent resistance based TC model, the switching frequency and the main device output capacitance can be determined to meet the TC safety requirement.

For example, given VCM = 400 Vdc. and ITCrms limit of 0.25 mA, the required CM impedance of the dc/dc stage is 1.6 MΩ. This required CM impedance can be translated into the constraints on Coss and fsw using Equation (4-5), as shown in Figure 4.21. Only operating in the shaded red area, the SGI converters are able to meet the touch current requirement. To reduce the touch current, it is preferred to have smaller Coss and fsw. However, such constraints greatly limit the converter power density. Therefore, TC suppression method is preferred.

Meeting TC Requirement

Figure 4.21. Constraints on main power device output capacitance Coss, and maximum switching frequency fsw

Simulation verification is conducted with the buck-boost PFC based SGI converter

(Figure 4.8) with a detailed circuit simulation. Results are shown in Figure 4.22. The results

match well of the analysis in Figure 4.9 and Figure 4.10, in which Vout= 350 V, Vac = 240

Vrms, fsw = 100 kHz, and Coss = 300 pF.

In addition, simulated Vbodyout and Ibody results are compared with the calculated results using the proposed equivalent resistance based low-frequency average current model. A point with Vcm = -292 V is selected for comparison. It can be seen that the calculated Vbodyout and Ibody are reasonably close to the simulated results.

Vcmtop Vcmbot

Vcmtop + Vcmbot

Ibody

Vbodyout

Figure 4.22. Simulation of TC generation mechanism of the battery charger, when ZTC is connected to the negative output terminal

Table 4.1. Verification of The Low-frequency Average Current Model Item Descriptions Simulation Calculation fsw Converter switching frequency 100 kHz The same C Device output capacitance, based on oss 300 pF The same C2M0045170d (1.7 kV, 45 mΩ) VCMt Equivalent CM voltage of top and bottom lines -292 V The same R Equivalent resistance of the CM blocking eqCM N/A 8.33 kΩ capacitors ZTC Impedance of the body impedance network 2 kΩ at 60 2 kΩ at 60 Hz Hz Ratio Impedance ratio of ReqCM / ZTC 4.17 Vbodyout Output voltage of the body impedance network -15.3 V -14.1 V I Average touch current goes through the body body -32.0 mA -28.4 mA impedance network

4.5. Output Voltage Potentials and CM Leakage Current with Floating Outputs

Earlier discussions assume that the SGI converter outputs are connected to the body impedance network or touched by a user. In that case, certain isolation voltage will be applied to the SGI DC/DC stage and CM leakage current will be generated. However, when the output terminals are floating, things become different.

As shown in Figure 4.23, the SGI AC/DC stage’s output terminals are floating. Two parasitic capacitance Cp1 and Cp2 are used to represent the capacitance between outputs and the earth. A voltage divider is formed by the SGI DC/DC stage and the two parasitic capacitances to share the total CM voltage, as shown in Figure 4.24.

EMI Filter Vdc S11 S12 S31 S32 L LCM DM Lf L SHF1 SHF3 SLF1 (Lk) CY1 L1 A  V Cmid ac CX C  in

CY2 N SHF2 SHF4 SLF2

Cp1 Cp2 S21 S22 S41 GND

Figure 4.23. Potentials of the SGI AC/DC with Totem-pole PFC based off-line power supply at positive line cycle (Vac >0), when the output is floating

ReqCM

Icm

V CM Cp1+Cp2

Figure 4.24. CM equivalent circuit of the SGI AC/DC stage when the output is floating

For verification, a case study is conducted for fsw = 120 kHz, Coss= 200 pF, Cp1 and Cp2

= 100 x 2 pF. So ReqCM = 20.8 kΩ and ZCP= 13.3 MΩ at 60 Hz. The large impedance ratio means Vcm almost all drops on Cp1 and Cp2 and the CM leakage current is 16.8 uA. At 450

V, the energy stored at Cp1 and Cp2 is just 20 uJ. The simulation results showed in Figure

4.25 matches with the calculation results.

Pri+ Sec+

L (-) SGI  Vac DC/DC C1 RL N Stage

Pri- Sec- Cp1 Cp2 GND I_GND

(a)

(b) Figure 4.25. Simulation verification of CM voltage distribution of the SGI AC/DC stage when the output is floating

4.6. Conclusions

The touch current is generated due to 1) isolation voltage stress across the dc/dc stage and 2) high-frequency switches cause capacitive current between two isolated sides. The isolation voltage stress varies for different ac/dc, dc/dc topologies, as well the grounding scheme of the grid. A high-frequency TC current model is presented to describe the transient behavior based on the circuit parameters. A low-frequency average current is developed to easily calculate the human body output voltage, which is extremely useful in determining whether a certain combination of grounding, switch output capacitance and switching frequency can meet the safety requirements. For a given SGI topology, it is preferred to have smaller Coss and fsw to reduce the touch current. When the dc outputs are floating at low frequency, the CM voltage stress is not on the SGI dc/dc stage. The output potentials to the ground are varying vs. time.

Chapter 5. Touch Current Suppression Methods

To reduce the touch current, it is preferred to have smaller Coss and fsw. However, such constraints greatly limit the converter power density and efficiency. Therefore, TC suppression method is preferred. To reduce the touch current, several passive suppressions methods are discussed first. To implement a more effective TC compensation, a systematic discussion of active compensation methods is presented. A design example is shown.

5.1. Requirements of Touch Current Suppressions

In the previous chapter, comprehensive analysis and modeling of touch current generation mechanism have been conducted. Essentially, in SGI solutions, the touch current is generated mainly because the CM barrier used to block the CM voltage is not fixed.

Therefore, whenever a new set of devices start to sustain the CM voltage, CM leakage current is needed to charge up the output capacitance to the target CM voltage. On the safety standard side, the voltage drop of the touch current on the body impedance network needs to be below 250 mVrms for 2-wire systems, which mainly concerns the low-frequency components of the touch current. As a result, passive filter techniques are not very effective

in suppressing the low-frequency touch current. Active compensation methods are more viable.

On the implementation side, it is would be beneficial that the main controller does not need to handle the touch current compensation, but rather the TC compensation needs to be controlled locally by high-speed circuitry within the SGI dc/dc stage, as shown in Figure

5.1. Such a local intelligence should be able to detect CM leakage current, initiate and control the local compensation circuit to ensure user safety.

Like a solid-state transformer

Vgs x 8 PWM 1&2 TC Compensation Vds x 8

DSP SGI DC/DC VDD(+20 V) x 4 Local Sensing and Vbat Power Stage Control

Signal VEE(-5 V) x 4 (Analog) Ibat Conditioning ITCC x 8

Figure 5.1. System diagram of the desired active TC compensation structure.

5.2. Passive TC Suppressions Methods

Passive TC suppression methods are investigated first due to their simplicity, as shown in Figure 5.2 However, the previous analysis in [46]-[48] show that they are not very effective. Here in-depth analyses are provided to explain why those approaches are not helpful in reducing the low-frequency touch current.

Softswitching for CM voltage exchange

COSS COSS

COSS energy -> loss

S1: OFF ITC S3: ON

Series attenuation Bypassing

VCM

Z (body Impedance) TC Figure 5.2. A system diagram of passive TC suppression methods.

5.2.1. Increasing the CM Impedance by CM chokes

This idea is to increase the CM impedance in the TC loop and CM chokes is one way to implement it. Series inductance can easily reduce the peak value of the TC. However, it is quite difficult to reduce the low-frequency TC, which is at line frequency. This fact can also be explained by the proposed equivalent resistance based low-frequency TC model, as shown in Figure 5.3. For example, even for a small CM impedance increase such as 10 kΩ at 60 Hz, the required LCM is 26.5 H. A case study results shown in Figure 5.4 further illustrates that adding extra CM chokes with reasonable values (up to multi mH) into the

TC loop does not cause any significant change of the low-frequency TC.

LCM ReqCM

ICM (ITC)

V ZTC (body Impedance) CM Figure 5.3. Low-frequency TC equivalent circuit with a CM choke.

IEC60950 limit for hand-held equipment with ZTC connected to protective earth conductor (if any)

Simulation result of the equipment without the protective earth conductor

IEC60950 limit for all equipment with accessible parts not connected to protective earth

Figure 5.4. RMS values of the ZTC output voltage in the simulation of the basic SC isolation cell circuit.

5.2.2. Bypassing the TC with Y capacitors

The idea of this approach is to bypass the TC from the ZTC with a passive shunt path, which has lower CM impedance so that the TC sensed by the ZTC can be reduced. Y capacitors can be added between the output ends and the earth ground. This is, however,

infeasible for equipment without the protective earthing conductor. In addition, there also exists a regulation on the ground fault current level, which sets a limit on the Y capacitance.

Furthermore, very large Y capacitors are needed to realize a reasonable attenuation of the low-frequency touch current. This fact can be explained by the equivalent circuit in Figure

5.5 and transfer function in Figure 5.6. For a typical Y capacitance limit of 100 nF per line, it can be seen that it gives very small attenuation at 60 Hz, compared with the case without

Y capacitors. Therefore, adding Y capacitors is not an effective approach to reduce the touch current.

ReqCM

ICM (ITC)

V ZTC (body Impedance) CM Figure 5.5. Low-frequency TC equivalent circuit with Y capacitors.

Transfer Function (Vbodyout vs. ITC)

CY = 0

CY = 200 nF

CY = 8 uF

Figure 5.6. The transfer function of Vbodyout vs. ITC with Y capacitors. 89

5.2.3. Soft-switching Techniques

This approach aims to enable the natural CM voltage exchange during the switching transients by utilizing the load current. The principle is the same as the ZVS operation of traditional power converters, however, it is CM voltage ZVS rather than DM voltage ZVS.

In the SC isolated cell circuit, if the ZVS operation can be achieved during the dead time as shown in Fig. 5. 20 (b), the Coss energy can be transferred to the complementary switches.

Nevertheless, the CM voltage ZVS is difficult to achieve with the load current. As shown in Figure 5.8, CM voltage needs to be transferred from the switch group #2 to #4 before the turn-on of the left cell. The CM voltage on both the top and bottom lines are in the same direction. Meanwhile, for DM current, it is a different direction for the top and bottom line.

Therefore, it is impossible to charge up the two devices in the group #4 together, without the help of additional axillary soft-switching circuitry.

Vds_S3 & Vds_S4 VCM

S1 & S2 Dead S3 & S4 Dead S1 & S2 ON band ON band ON 0 (a)

Vds_S3 & Vds_S4 ZVS VCM S1 & S2 Dead S3 & S4 Dead S1 & S2 ON band ON band ON 0 ZVS (b)

Figure 5.7. Operation waveforms (a) before and (b) after implementing the ZVS operation to prevent the TC generation [49]. 90

Goal

- ½ |Vac| +

S12 S32 -½ |Vac| +Vdc Vo

S11 S31

S22 S42

-½ |Vac| GND S21 S41 - ½ |Vac| + #1 #2 #3 #4 Goal

Figure 5.8. Circuit diagram for the goal of CM voltage transfer through soft-switching technique.

5.3. Active Touch Current Compensation

5.3.1. Overview

The earlier discussion shows that passive TC suppression techniques are not very effective. The main reason is that TC component concerned is at line frequency, which is very difficult to be filtered out by passive components without impacting the converters power density. Active compensation or active filter method would be better choices.

The concerned TC is at line frequency; however, the active compensation should be conducted at switching frequency. This is because the compensation current is only able to flow through the SGI dc/dc stage during the switching transients of two cells. When only one of the cell is conducting, the injected compensation current has no the path to flow.

Thus, the active TC compensation needs to be synchronized with the switching of the dc/dc stage.

The active TC compensation is realized by providing energy to charge up the Coss of the switch that needs to support the VCM. Thus, it no longer draws energy from the CM voltage source and therefore, the pulse TC can be reduced. Figure 5.9 illustrates this idea during the turn-on transient of S3, with both centralized and distributed TC compensation. Taking distributed TC compensation method as an example. When S3 turns on, its Coss is discharged to zero. At this moment, the TC compensation circuit of S1 provides energy to charge up

S1’s Coss to the target VCM, thus the TC highlighted in red can be reduced significantly. The two TC compensation circuits supply energy to their main power device alternatively, as shown in Figure 5.10. When VCM is zero, both TC compensation circuit is in the standby mode. In the case of centralized TC compensation, the compensating current is injected at turn-on transients of both S1 and S3.

Centralized TC comp

Distributed TC comp TC TC

comp,S1 comp,S3

ITCcom COSS COSS Vds_S1

COSS energy -> loss

S1: OFF ITC S3: ON Reduced Touch Current Vds_S3

VCM

ZTC (body Impedance)

Figure 5.9. Active TC compensation techniques at every turn-on event (S3 for example). 92

Vcm

When VCM is not zero When VCM IS zero

0 Dead time t

Vds_S1 VCM

S1 ON S1 ON

Vds_S3 VCM

S3 ON S3 ON

ITC

TC compensation TCC,S1 & TCC,S3 TCC,S1 TCC,S3 TCC,S1 TCC,S3 TCC,S1 TCC,S3 ITCcom

Reduced ITC

Figure 5.10. Waveforms and timing sequence of the active touch current compensation.

As shown in Figure 5.11, the active compensation approach consists of the following six aspects. The compensation circuit can be either centralized or distributed. The compensation current can be realized by a switching circuit or a linear circuit. Compensation energy source is supplying energy to the compensation circuit. Temporary energy storage is the element used to supply pulse current. Utilizing channel sharing, the component count can be reduced for the distributed compensation approach. The control of the TC compensation involves when to initiate the compensation, how to control the amount of injected current and how to synchronize with the main power devices. As discussed in the previous chapter, the CM voltage source is determined by the circuit topology and the grounding system of the grid.

Figure 5.11. Overview of elements in active touch current suppressions methods.

5.3.2. Centralized or Distributed Architecture

Applying the active touch current compensation technique to the SGI SC basic cell, the circuit diagrams are shown in Figure 5.12. In the distributed TC compensation approach, each main device is equipped with its own compensation circuit, integrated with each gate drive circuitry. While for the centralized one, the TC compensation is realized by a standalone unit, bridging the two isolated sides of the circuit. A comparison is shown in

Table 5.1. Generally, centralized compensation approach poses higher requirement of voltage, current capability than the distributed one. The benefit of the centralized approach is the fewer components counts and system complexity.

Distributed shunt TC C compensation ITCcom Centralized shunt TC compensation TCC S11 TCC S12 TCC S31 TCC S32 S1 S3 S11 S12 S31 S32  

Vin C1 C2 C3 Vout V C C2 C3 V  in  1 out TCC S11 TCC S12 TCC S31 TCC S32

S21 S22 S41 S42

S2 S4

VCM ICM (ITC) VCM ICM (ITC)

ZTC ZTC

(a) (b) Figure 5.12. Shunt active touch current compensation methods. (a) Centralized compensation. (b) Distributed compensation.

Table 5.1. Comparison between centralized and distributed active TC compensation System Current Integration with Components Voltage rating structure direction gate drive count Insulation voltage requirement, Bi- Centralized difficult Small bi-directional directional ½ of the Insulation voltage Uni- distributed easy Large requirement, uni-directional directional

5.3.3. Detection of the CM Leakage Current

The CM leakage current needs to be detected to start the active compensation circuit.

Meanwhile, the channel selection and amount of compensation charge needed need to be properly controlled. There are typically two approaches, as shown in Figure 5.13. The first approach uses high impedance resistive divider to measure the voltage across a pair of common source MOFSETs. A capacitor can be added to at the lower arm to act as a quasi- peak detector or to filter out the switching frequency voltage ripple. If no user touches the

output of the charger, the CM voltage across the SGI DC/DC stage would be zero. Thus, the measured voltages V1 and V2 are zero. However, if any CM voltage drops on the semiconductors device, depending on the voltage polarity, either V1 or V2 becomes logic high. The analog signals V1 and V2 are processed by the local digital circuitry, as shown in

Figure 5.14. Signals are used to answer these three questions. 1) Is compensation needed?

2) What’s the direction of the CM voltage? 3) What’s the target CM voltage? Similarly, CM leakage current can be sensed with CM current transducer and current transformer. If the sensing circuit is voltage output, then feedforward control can be used to directly control the compensation voltage. If a CM current based sensing method is applied, a feedback based closed-loop control on the compensation current is needed.

1 Scom1 &Scom2 1 Based on CM Voltage Detection

Channel select Logic circuit . Large voltage amplitude V1 V2 . Quasi-peak voltage detection . Simple open-loop implementation

S11 S12 S31 S32

CT sensing ITC  Cmid C  in 2 2 Based on CM Current Detection

. Small CM current (0.25 mA) measurement S21 S22 S41 S42 . Low frequency CT (60 Hz): 16 mH to achieve 3 V Channel select Logic circuit VIcm . Closed loop control is needed

S S com1 & com2 Figure 5.13. CM leakage current detection methods.

Logic circuit

Scom1 &Scom2 V1 + Left Scom Vth - Comp.

V2 R S + com Vth - Comp. To MCU: enable Scom Figure 5.14. Compensation logic control circuit based on the sensed CM voltage.

5.3.4. Compensation Current Injection Methods

The required TC compensating current shown in Figure 5.10 could be generated by either linear-type or switching-type compensation circuits.

With linear-type compensation, a linear-type current source circuit can be designed based on BJTs operating in their saturation region [49]. An example of a unidirectional linear current source using PSSI2021SAY is shown in Fig. 5.27. It can be switched on or off by controlling the enable pin (i.e., the IN/OUT pin). However, the linear current source only works when the input voltage is higher than the output voltage, so it is impossible to use the gate drive power supply (~20 V) to charge the switch Coss up to the line input voltage. As a result, it is not quite feasible to implement this idea.

Coss

Figure 5.15. Example of a unidirectional, linear-type current source circuit [49].

A similar linear-type compensation method used in active EMI filtering is also investigated. This concept was earlier designed for active EMI filter in [76]. The compensation concept based on current-sense-feedforward control is illustrated in Figure

5.16. The idea is to sense the output side CM current and to use a linear-type current source to provide the pulse current. Therefore, the CM current will be circulating inside the converter without going out to the user (body impedance network). The implementation of this idea is shown in Figure 5.17. The CM current sensing can be realized by a third winding on the output side CM choke. It functions as a current transformer (CT). The CT is loaded by a burden resistor R1. After that, a high bandwidth operational amplifier followed by a buffer stage is used to drive the Y capacitor connected to the ground.

A simulation comparison is conducted for the CM leakage current without compensation and with the current-sense-feedforward compensation, as shown in Figure 5.18. It can be seen that the Vbodyout (body impedance output voltage) is significantly lower in the

compensated case and it passes the UL2202 safety standards. The compensation current,

Isource is able to follow and provide the CM leakage current to charge up the device output capacitance quickly.

S11 S S S VCM (s) ZCM (s) 12 31 32

C1 C3  Cmid A(s) A(s) C  in GND1 GND2

Icancel(s)

Icancel(s) C2 C4

Z (body Impedance) S21 S22 S41 S42 TC (a) (b)

S11 S12 S31 S32 +Vcc 2×Lp 2×R5 R1

CT Ls +  1/n Op-amp Cmid - Cin GND  1 R2

C -Vcc GND2 GND2 GND1 S21 S22 S41 S42 Op-amp Buffer (a) (b)

Figure 5.17. The implementation of leakage current compensation based on current- sense-feedforward control. (a) CM current sensing using the common-mode choke. (b) Implementation of the linear-type compensation circuit.

Vbody_rms = 13 V > 250 mV (UL2202) Vbody_rms = 190 mV < 250 mV (UL2202)

(a) (b)

Figure 5.18. Simulation results of the CM leakage current (a) without compensation and (b) with current-sense-feedforward compensation.

However, there are some challenges in this current injection methods.

. For the majority of the SGI topologies, the CM voltage has a dc offset. That

means the CM leakage current also has a dc offset. This is problematic because

the current injection is done through a Y capacitor connected to the ground.

Charge balance of the capacitor cannot be maintained.

. A buffer stage with high voltage rating (Vdc), high bandwidth, and high pulse

current capability is required to support the high-frequency pulse CM leakage

current.

100

So far, all the investigated linear-type current injection method cannot be easily implemented. Two switching-type compensation methods have been investigated. As shown in Figure 5.19, the first type of method uses existing gate drive power supply as the energy source. The low voltage is boosted up by an inductor based boost-type circuit to provide charges to the switching output capacitance Coss at switching transients. It is typically a high boost ratio from gate drive voltage to the CM voltage. Accurate feedback control is needed to provide suitable energy through the inductor current. The charging of the compensation inductor is conducted during the dead time, which poses a minimum dead time requirement to the main switched capacitor circuit.

On the other hand, the capacitor based energy transfer method stores energy in a capacitor. The capacitor voltage is controlled to be the target CM voltage. Whenever compensation is required, an enable switch short the compensation capacitor with the device

Coss. This method is usually easier to implement and control than the inductor based energy transfer. It eliminates the inductor charging time in the dead time, thus the DM operation and CM leakage current compensation are decoupled. Moreover, for totem-pole PFC circuits, the CM voltage is fixed at DM DC bus voltage. Thus, an open-loop 1:1 ratio isolated dc/dc converter can be used to generate the compensation voltage from the converter dc bus.

101

Gate drive power supply Vcc

Isolated dc/dc Enable Vdc Vcom Coss Boost-type Converter swtich Coss Vcom circuit 1:1 i.e. 450 V -> 450 V Vcom -> Vdc i.e. 30 V -> 450 V (b) (a)

Figure 5.19. Switching-type active compensation methods (a) inductor based circuits with gate drive power supply. (b) Capacitor based energy transfer with HV DC power supply.

For the boost-type circuit, a buck-boost converter is shown in Figure 5.20 as an example.

The circuit principle is that the low-voltage source first store energy in the inductor, Lcom11, when Scom11 is on. And then when Scom11 is off, the inductor energy is transfer to the Coss to boost up the voltage across the main device. The input is supplied by a negative low voltage source generated by the gate drive power supply. The compensation switch Scom11 ‘s source shares the same ground as the negative power supply, which simplifies the gate drive power supply design. Scom11’s voltage rating should be the highest DM voltage in the circuit. Dcom11

‘s voltage rating is much higher, which is the same the main device, at the CM isolation voltage.

Scom11 Dcom11

Icom C + Lcom11 oss

Figure 5.20. An example of boost-type compensation circuit: a buck-boost converter. 102

The capacitor-based energy transfer method is more suitable for PFC topologies that have a fairly constant CM voltage, like totem-pole PFC. Then the key is to design a low power isolated dc/dc converter with 1:1 DC gain. Several circuit candidates are listed in

Table 5.2. Based on the circuit characteristics, there is a tradeoff between the transformer turns ratio, switching, diode voltage stress and practical duty ratio. But all of them are able to deliver an isolated HV dc output at the dc bus voltage.

Table 5.2. Isolated dc/dc topologies suitable for low-power and1:1 transfer ratio.

Topology Schematic Transfer Switching Diode Practical Function Voltage Voltage Duty 푉표푢푡/푉푖푛 Stress Stress Ratio

Forward 푁푠 ퟐ 푽 ퟐ 푽 0.45 ∗ 퐷 풊풏 풊풏 푁푝

Push-Pull 푁푠 ퟐ 푽 ퟐ 푽 0.45 ∗ 퐷 풊풏 풊풏 푁푝 ∗ 2

2-Switching 푁푠 푽 푽 0.45 ∗ 퐷 풊풏 풊풏 Forward 푁푝

Half-Bridge 푁푠 푽 푽 0.45 ∗ 퐷 풊풏 풊풏 With 푁푝 Rectifier

103

5.3.5. Channel Sharing

In earlier sections, it has been discussed that the compensation circuit can be either a centralized and distributed structure. If a distributed structure is used, it does not mean each main device needs a dedicated compensation circuit. This is because, at any given moment, the CM voltage is only one direction. Only of the common source device needs TC compensation. Therefore, channel sharing can be applied to decrease the number of compensation channels needed, as shown in Figure 5.21 (b). The two switches S11 and S12 share the same TC compensation circuit. Meanwhile, a channel select switch is added to direct compensation current to the right device.

TC Comp Circuit TC Comp Vcom1 Coss Circuit S11 Coss Vcom S11

Vcom2 Coss S12 TC Comp Coss S12 Circuit

(a) (b)

Figure 5.21. Channel sharing structure of compensation circuits. (a) Dedicated compensation circuit. (b) Shared compensation circuit.

For some cases, it may not beneficial to share compensation circuits for two common- source devices. This is because the channel select switch needs to have the same voltage rating as the main switch and also has bi-directional voltage blocking capability. Two

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examples are shown in Figure 5.22. For the buck-boost converter in Figure 5.22 (a), two

HV rated MOSFET Scs1 and Scs1 are required to realize the channel selection. Also, two isolated gate drives are needed. Compared with two dedicated compensation circuits, the shared channel solution replaces one LV MOSFET, one HV diode, one inductor with two

HV MOSFET and two isolated gate drives. Therefore, the benefit is not very significant.

However, for the capacitor-based energy transfer circuit in Figure 5.22 (b), it directly reduces one output from the isolated dc/dc converter. This is because the HV diode and the

MOSFET needed for the channel is the same for both dedicated and a shared compensation circuit.

Scs1 Scom11 Dcom11

Icom Coss Coss Scs2 S11 Vcom S + Lcom11 11 ks Coss Coss

S S 12 12 (a) (b)

Figure 5.22. Shared TC compensation circuit for (a) boost-type inductor based energy transfer circuit and (b) capacitor based energy transfer circuit.

5.3.6. Control of the TC Compensation Circuits

The control of TC compensation mainly consists of four aspects. 1) Decide if active TC compensation is needed. 2) Select a channel to provide the right compensation current direction. 3) Accurately synchronize the TC compensation to the main devices’ switching

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events to avoid over or lack of compensation. 4) Realize the TC control with local intelligence, without the involvement of the main controller.

Decide if active TC compensation is needed. This decision is based either CM voltage or CM current detection as discussed in 5.3.3. For example, if a totem-pole topology is used for the PFC stage, as shown in Figure 4.5, there is only CM voltage and leakage current during half of the line cycle, assuming a user has touch either the positive or negative outputs.

Based on the sensed CM voltage or current, the local controller should be able to select the right half line cycle to activate the compensation circuit. However, if nobody has touched the outputs, the local controller should be put in the standby mode and be able to start right away when a CM voltage is sensed.

Select a channel to provide the right compensation current direction. As shown in

Figure 4.5, depending on the CM voltage direction, the CM leakage current flow direction varies. Thus, the right compensation channel has to be determined right initially, otherwise, it may result in even more CM leakage current.

Accurately synchronize the TC compensation to the main devices’ switching events to avoid over or lack of compensation. As the compensation requirement stated in 5.3.1, the compensation current has to be synchronized with the turn-on of its complimentary device. The TC compensation circuits need to be controlled to charge the main power device’s Coss to the target CM voltage level. Depending on the current injection methods,

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the timing control is slightly different, which will be discussed in the design implementation section.

5.3.7. Implementation of the Active TC Compensation

The buck-boost based distributed TC compensation solution has been discussed earlier in 5.3.4. The circuit diagram and operation waveforms are shown in Figure 5.23 and Figure 5.24. The Vcc is generated by the gate drive power supply. The compensation inductor current is always in discontinuous mode. The buck-boost converter steps up the voltage to charge the Coss to the target CM voltage.

Generated from gate drive S1 power supply Turn-on transient Scom Dcom

Icom + ITC V Coss VDS CC Lcom -

S3 Distributed Buck-boost based Already off TC Compensation

Figure 5.23. Buck-boost circuit for TC compensation of the Coss’s charge at turn-on transients.

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DB S3 ON

S1 ON

S12&12_COM ON DB

S32&42_COM ON

Zoomed-in View

Ton

SCOM ON t

S1 ON t

ITC

Icom

t 0

VCM VDS t 0 t1 t2

Figure 5.24. Operation of waveforms of the buck-boost TC compensation circuit.

The required gate signals, S32&42_COM and S12&22_COM, for the buck-boost TC compensation circuits are shown in Figure 5.25. There are two things to be controlled: 1) starting time of the charging process and 2) duration of the charging process. First, the turn-off of the compensation switch needs to be synchronized with its complimentary main switch. Second, the on-time, Ton, of the gate signal needs to be adjusted based on the target common mode voltage (typically 200 ns to 1 us). These two things together determine the starting time of the charging process.

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Aligned Aligned

S1&2 ON

S3&4 ON

Ton S32&42_COM ON

Ton S12&22_COM ON

Figure 5.25. Required gate drive signals for the buck-boost based distributed TC compensation circuits.

If the TC compensation circuit is also generated by the main DSP, as shown in Figure

5.26, the gate signal control be realized by configuring the TI DSP’s registers in Figure

5.27.

Ton VCOSS: 0 -> Vdc SCOM ON t TC S1 ON comp t COSS COSS Vds_S1 ITC Vdc Icom DSP Ton COSS energy -> loss

VCM direction Ton =f (Vdc, Coss) t S2: OFF S4: ON 0 Reduced Touch Current Vds_S3

VCM VCM VDS Z (body Impedance) t TC 0 t1 t2

Figure 5.26. System diagram TC compensation control with the Main MCU.

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PRD

CMPA DB S1&2 ON

PRD/2 DB S3&4 ON

Ton S32&42_COM ON

PRD/2 Ton S12&22_COM ON

Figure 5.27. DSP registers configuration for generating TC compensation gate signals.

The on time, Ton, can be calculated as in (5-1), where LCOM and VCC are compensation inductance and bus voltage of the compensation circuit. Eoss is the energy stored in the output capacitance of the main power device, which is voltage dependent and usually available in the datasheet.

2LCOM Eoss t1  (5-1) VCC

However, it is preferred to operate the SGI based converter just as a traditional isolated converter, or a solid-state transformer, as shown in Figure 5.1. It means the control command of TC compensation circuit needs to be generated locally such that the main DSP only sends out PWM signals for the main power switches. The main design challenges are

1) to realize low propagation (less than 50 ns) in the PWM generation and 2) to adjust the on-time (Ton) based on the isolation voltage stress.

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The signal and function diagram for local compensation control signal generation are showed in Figure 5.28 and Figure 5.29, respectively. The synchronization of compensation switch signal (SCOM) and main power device gate signal (S3) can be realized by a flip-flop.

However, to implement a variable pulse width, an intermediate pulse in purple is needed.

This pulse is triggered by the falling edge of S1. Its pulse width is controlled by the feedback

CM voltage to the variable pulse generator. When the purple pulse ends, the falling edge sets the SCOM. And the rising edge of S3 resets the SCOM.

To implement this approach, analog circuit implementation is more feasible due to the stringent timing requirement. As the Ton is typically varying from 100 ns to 1 us. A pulse resolution and propagation delay less than 30 ns are preferred. The rising and falling edge detection and RS latch can achieve a propagation of less than 10 ns easily. However, the variable pulse width generator usually comes with a quite large delay. For example,

LMC555 exhibits a typical propagation delay of 100 ns. Monostable vibrator IC such as

SN74LVC1G123 can realize a sub 10 ns propagation delay, however, its pulse width is usually fixed by external R and C components. Some monostable vibrator such as LTC6993 allows a voltage controller pulse width, however, the 1 us minimum pulse width cannot meet the requirement. In summary, it is quite difficult to realize the local generation of a variable pulse width with low propagation delay and high pulse width resolution. Further study is still needed.

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Aligned

Pulse width t controlled by w S3 rising edge reset SCOM pin 5, Control tw

Ton SCOM

Figure 5.28. Signal diagram for generating SCOM with local intelligence.

Clear PWM 1&2 Rising and Falling RS Edge Detection Latch SGI DC/DC Trigger Trigger Power Stage

CM voltage

Tw Variable Pulse Generator 1

Figure 5.29. Block diagram for generating SCOM with local intelligence.

Another perspective is to realize low propagation delay and high pulse width accuracy locally while leaving the variable pulse width control to the main DSP. One way to realize this approach is to encode the Ton into the dead time of main power switches, as shown in

Figure 5.30 and Figure 5.31. The TC local control circuit uses the main power device gate signals to generate compensation switch gate signals. The dead time is adjusted by the main

DSP based on the CM voltage. The larger the CM voltage, the longer the dead time. This is

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a compromise of local TC control. However, it still can maintain the same number of PWM signal sent from the main DSP.

Aligned Aligned

S1&2 ON

S3&4 ON

Ton S32&42_COM ON

Ton S12&12_COM ON

Figure 5.30. Signal diagram of PWM generation by encoding pulse width into the deadtime of main power device PWM signals.

PWM 1&2 Rising and Falling Edge Detection SGI DC/DC Power Stage Set Reset RS Latch

Figure 5.31. Block diagram of PWM generation by encoding pulse width into the deadtime of main power device PWM signals.

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5.4. Conclusions

Touch current compensation is an approach to mitigate the tradeoff between satisfying safety standards and achieving high power density and high efficiency. Because the touch current test evaluates the low-frequency RMS current, which goes through the human body impedance, the passive filtering techniques are not very effective. Instead, active compensation methods are explored. A comprehensive discussion is presented on various aspects of active compensation methods, including system architecture, TC detection, compensation current injection methods, channel sharing and the timing control. At the end, a buck-boost based distribution method with local control is presented to illustrate the design process. It is highly preferred that the TC control can be handled without the intervention of the main controller.

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Chapter 6. Design Guidelines of SGI based Power Converters

This chapter presents the design considerations of SGI based power converters. With onboard battery charger as a target application, design guidelines of galvanic isolation and differential-mode power delivery are discussed. A 2 kW SGI based battery charger prototype is presented. Test results of DM power delivery and touch current tests are shown.

6.1. Overview

The design procedure of SGI based power converters is different from the traditional transformer-based isolated converters because semiconductor devices handle both DM power delivery and galvanic isolation. As shown in Figure 6.1, the SGI power converter design consists of DM power delivery and galvanic isolation. And two aspects are highly coupled to each other. DM power delivery mainly poses requirements on the switch on- resistance (Rdson), switching losses and filter capacitance. Galvanic isolation defines the switching voltage rating and output capacitance. The converter switching frequency is influenced by both DM power delivery and the touch current requirement.

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Design Procedure of SGI based Converters

Design of Design of Galvanic isolation DM power delivery

Switch voltage rating based on Switch Rdson and Eon, Eoff based on Insulation voltage requirement power rating and target efficiency

Device output capacitance Capacitance in SC circuts based on and switching frequency switching frequency and target efficeicny based on touch current limit

Increase f Meet sw Active touch No power density current suppression target?

Yes

END

Figure 6.1. The design procedure of SGI based power converters.

In this section, the design procedure is illustrated with a 2-kW onboard battery charger, with Vin = 120 Vrms, Vout = 240 V - 450 V. This converter is realized by a totem-pole PFC stage and an SGI based 1:1 switched capacitor cell, as shown in Figure 3.30. The design of

GaN-based totem-pole PFC stage remains the same as the traditional practice. A CCM operation is selected. The isolation design of the converter refers to UL2202. As shown in

Figure 6.2, the totem-pole PFC stage takes care of the PFC and voltage regulation functions.

Meanwhile, the SGI based 1:1 switched capacitor circuit realizes galvanic isolation and delivers DM power to the battery.

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S11 S12 S31 S32 LDM LCM

SHF1 D1 (Lk) CY1 L1 A  C Cmid Vac X Cin B  CY2

SHF2 D2

S21 S S41 S V 22 42 ac Gate signals Fixed 0.48 duty ratio

IL - Vbulk

- Ibat

CCM PFC control GV + GC + Vbulk_ref Ibat_ref CC, CP Charging

Vbat

- Vbat HV + V >V bat bat_ref Vbat_ref PFC: SGI DC/DC  PFC function & CCM operation  Charging profile (current & power regulation)  DC-link voltage regulation

Figure 6.2. Control diagram of a battery charger with fully decoupled totem-pole bridgeless PFC stage and SGI dc/dc stage.

6.2. Design of Galvanic Isolation

The switching device voltage rating is decided by dielectric voltage-withstand test

required by safety standards. The test voltage specified in UL2202 is (1000 2UVn ) a. c .(rms) ,

where U n the maximum rated voltage of the converter is. With 450 V being the highest voltage, the test voltage is 1.64 kVac, rms. The scenario illustrated in Figure 6.3 shows the instance when a peak positive voltage is applied to node 1 and 3. With the same switches for S11 through S42, all switches in red sustain half of the test voltage. The conclusion is the same when the test voltage is flipped direction or when the test voltage is applied between two other nodes. Therefore, the voltage rating of S11 through S42 is at least 1.16 kV.

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Vcm = 2.32 kV

EMI Filter S11 S12 S31 S32 LDM LCM 1 SHF1 SHF3 SLF1 3 (Lk) CY1 L1  A Cmid CX C  in

CY2 2 SHF2 SHF4 SLF2 4

S21 S22 S41 S42

Sustaining CM voltage Conducting CM current

Figure 6.3. Voltage stress of switches in the dielectric voltage-withstand test when a maximum positive voltage is applied to node 1 and 3.

As discussed in Chapter 4, during the converter operation, if a user touches either the positive or negative of the output terminal, a CM voltage will be developed across the SGI dc/dc stage, as shown Figure 4.4. The CM voltage profile over a line cycle is shown in

Figure 4.5. Basically, the CM voltage equals the DM bus voltage over a half line cycle and becomes zero in the other half line cycle, depending on where the user touches. With CM voltage, the high-frequency switching of the SGI dc/dc stage generates CM leakage current, which can be calculated using the proposed low-frequency average current model in 4.4.2.

For a given topology and switching frequency, the larger the switch output capacitance, the larger the CM leakage current will be. In order to achieve high-efficiency and high-power- density, it typically requires switches with low on-resistance and output capacitance, which

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is difficult to achieve at the same time. Therefore, active touch current compensation circuit can be used to overcome this dilemma.

The buck-boost based distributed compensation circuit is applied, as shown in Figure 6.4.

The hardware design procedure is discussed in Chapter 5. All the compensation circuits are located on a daughter board that can access the main switch’s Vds, Vgs and gate drive power supplies. The TC compensation circuits are controlled by a local intelligence formed by analog and digital circuits, as shown in Figure 6.5. A CM voltage sensing circuit is placed at S31 and S32. The two sensed voltages are sent to two comparators.

A detailed view of the local logic processing circuit is shown in Figure 6.6. The sensed voltage V1 and V2 first go through separate voltage follower and decouple the large source impedance from the voltage divider. Then these two voltages are added together to form V1

+ V2. V1 and V2 are fed to separate comparator with the same threshold. This means when

CM voltage is presented, the comparator would output a high signal. V1 + V2 signal is also fed to a comparator with a threshold Vth2, slightly larger than Vth1. The XOR gate ensures that only one of the switches sustains CM voltage. And the AND gate is another level of verification to see if V1 + V2 is high enough. These two logic circuits are designed to rule out the following possibility. When there is no CM voltage presented in the circuit, if accidentally the compensation starts, both V1 and V2 would become high because the terminal CM voltage is zero. This mist rigger can generate additional TC current and cause power losses. 119

The local PWM generate is based on the discussion in Figure 5.30 and Figure 5.31. Two rising and falling edge detectors find out the turn-on and turn-off of main devices. The set and reset signals are sent to two RS-latch to generate Scom1 and Scom2. When ScomEN is high, then compensation PWM signal will be passed to all compensation switches.

Distributed shunt TC C compensation

TCC S11 TCC S12 TCC S31 TCC S32

S11 S12 S31 S32

Generated from gate drive S1 power supply Turn-on transient  Scom V C C2 C3 V Dcom in  1 out TCC S11 TCC S12 TCC S31 TCC S32 Icom + ITC S S V Coss VDS 21 22 S41 S42 CC Lcom -

S3 Distributed Buck-boost based Already off VCM ICM (ITC) TC Compensation

ZTC (a) (b) Figure 6.4. SGI switched-capacitor cell with buck-boost based distributed compensation circuit. (a) Overal circuit diagram. (b) Each TC compensation circuit.

Figure 6.5. TC local control based on CM voltage sensing and buck-boost compensation circuits. 120

V1 + V1 + Select left Scom - Vth1 - Comp. V2 + V2 + Enable Scom - Vth1 - Comp.

+ V1+V2 + - Vth2 - Comp.

Source Figure 6.6. TC logic circuit to enable and select the compensation channel.

6.3. Design of Differential Power Delivery

The design principle of the SGI based SC 1:1 cell is similar to other SC circuits.

Depending on the circuit parameters, the DM current waveforms can be configured into the following three patterns: (a) a hard-switching current with a time constant much smaller than the switching cycle, (b) a hard-switching current with a time constant much larger than the switching cycle, and (c) soft charging with resonance frequency equaling the switching frequency, as shown in Figure 6.7. To achieve high efficiency, it is preferred to operate the

SC circuit in mode (b) or (c). The conduction loss usually dominates and it can be described using the equivalent-circuit-based average models [77], as shown in (6-1). The power loss overviews of hard-switching and soft charging operation are shown Figure 6.8 and Figure

6.9, respectively.

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(a) (b) (c)

(6-1) t R  C 1  e22  t e 2 1 r f  f Pcond I avg 4R   2 ,  fs  tr21 R  C f   e  t f e 

 ton   (Rsf ESR) C where  ,  R 4R dson ESR  1  ton  t r  t f  2 fs

Iavg is the average output current. ton is the on-time of the switch. C f is the capacitance

of the middle filter capacitor. tr and t f are the rising and falling time of the switch current,

respectively. fs is the switching frequency. Rdson is the on-resistance of each switch and

ESR is the parasitic resistance of the middle capacitorC2 .

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Switching loss can be modeled by considering switch voltage and current overlap loss,

Coss loss and gate driving loss, which is the same as other topologies. The converter’s switching frequency, efficiency, and capacitance can be selected based on the target power density and touch current limit. With a target switching frequency, a proper capacitance can be selected based on the target efficiency. The main constraints of switching frequency are the output capacitance of the selected switches and the TC limit in industrial safety standards.

When an active TC compensation is implemented, the switching frequency can be increased dramatically, however, it would still be limited due to the power rating of the compensation circuit.

22 1 tr R  C f 1  e  t f e Conventional 2   Pcond I avg 4R   2 conduction loss  fs t21 R  C   e  t e r f  f Conduction Losses 1 Cap charging and RRs ESR Rs 4R dson ton  t r  t f discharging loss t 2 fs   on (Rsf ESR) C I 1 VV   avg IV overlap loss P I  V () t  t  f ds  swIV d ds r f s fCsf (1  e ) 2 V I  d R Switching Losses Coss loss PswCoss Eoss f s Eoss f (Vds )

Gate driving loss PswGD V g  Q g  f s

Figure 6.8. Power loss model of an SGI 1:1 SC cell in hard-switching mode.

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1 Operating at damped resonance frequency: Cf  2 22 R 4  fLsr 4Lr 1 Small Qualify Factor, 0.53

Icf Icf

1  Conventional R  tanh(d ) Conduction Losses conduction loss e fs C f 2

R  22 ; dd ;  0    2  fs 2L d 1 L Q  (Rsf ESR Rind ) C Switching Losses Gate driving loss PswGD V g  Q g  f s

Figure 6.9. Power loss model of an SGI 1:1 SC cell in soft-charging mode.

In the prototype, the switching frequency is selected to be 120 kHz, which requires a filter capacitor of 3.15 uF and a resonate inductor of 400 nH. The resulted efficiency is around 98 %. As shown in Figure 6.10, the power loss is dominated by conduction loss, which is mainly contributed of the Rdson and sinusoidal resonant current. The switching loss is negligible due to the soft switching. The power rating of the active compensation circuit limits the further increase of switching frequency. Meanwhile, the filter capacitor and resonant inductor are relatively small compared to eight To-247 MOSFET. Therefore, to further increase the switching frequency does not have a significant benefit of power density.

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37.4 W

0.13 W

120 kHz

(a)

120 kHz

(b) Figure 6.10. DM power delivery design of a 2 kW 1:1 SC cell. (a) Power loss vs. switching frequency. (b) Efficiency and filter capacitance vs. switching frequency.

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6.4. Prototype and Experimental Verifications

A 2 kW SGI based onboard battery charger is shown in Figure 6.11. The prototype consists of three sub-systems: 1) a GaN-based totem-pole PFC stage, 2) a SiC-based SGI dc/dc stage with local touch current compensation and 3) a low cost and compact control and sensing system. The specifications of the charger are shown in Table 6.1. This prototype complies with UL 2202 safety standards on the insulation and leakage current requirements.

SiC Based SGI Dc/dc Stage

C2M0045170D SiC MOSFET 1700 V/90 mΩ (150°C)

GaN Based Totem-pole PFC Stage

Control and Sensing Boards TI F28027

GS66516T GaN HEMT 650 V/70 mΩ (150°C)

Figure 6.11. A 2 kW SGI based onboard battery charger prototype.

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Table 6.1. Specifications of the 2 kW SGI based onboard battery charger prototype. Item Description Specifications Vac Line input voltage 120 Vac, rms, 60 Hz Vdc Charger output voltage 250 V - 450 V Pout Output power 2 kW fsw, PFC PFC switching frequency 150 kHz fsw, dc/dc SGI DC/DC switching frequency 120 kHz Eff System efficiency 94% - 96%

The Totem-pole PFC stage is using 650 V, 70 mΩ GaN devices from GaN System. The system runs with continuous conduction mode with a switching frequency of 150 kHz.

Comprehensive protection functions have been included, such as under voltage lockout, over voltage lockout, desaturation protection and active miller clamping functions. The PFC subsystem consists of two boards. The bottom layer contains the power stage and gate drivers. The top layer daughter provides isolated gate drive power and PWM signals.

The SGI DC-DC stage is based on1.7 kV SiC devices. The board assembly consists of three boards. Pictures of the bottom and middle layer PCBs are shown in Figure 6.12. The bottom board is the power stage of the SGI SC circuit. The middle layer contains isolated gate drive power for driving the main device and also for the TC compensation. The middle layer also hosts eight channels of buck-boost TC compensation circuits. The top layer is the

TC local sensing and control circuitry. The SGI dc/dc converter runs at 120 kHz with soft- charging control.

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(a) (b)

Figure 6.12. (a) Power stage (bottom layer) and (b) TC compensation circuit board (middle layer) of the SGI dc/dc stage.

The sensing and control subsystem contains three boards. The bottom layer is the analog signal sensing board, as shown in Figure 6.13. This is a compact system with five isolated voltage and current sensing channels, as well as signal conditioning circuitries. The design features very small coupling capacitances between two isolated sides, geared towards WBG device with high dv/dt. The analog output signals are 0-3 V and directly fed into the analog- to-digital (ADC) of a TI 28027 Launchpad. The second layer of this system is the DSP board. The first layer is the digital signal interface board. It converts 0-3 V PWM signals to

0-5 V and also scales down 5 V digital signal to 3 V for the DSP. Coaxial cables are used for better noise immunity.

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CH5: Battery Current CH4: Battery Voltage CH3: DC Bus Voltage CH2: Grid Voltage CH1: Grid Current

Analog Interface to DSP

Figure 6.13. Isolated analog signal sensing board.

6.4.1. Differential-mode Power Delivery Test

The charger has been tested at the rated voltage and power with a resistive load. The ac side waveforms at 120 Vrms, 60 Hz, and 1.58 kW are shown in Figure 6.14. The power factor is 0.994 and the system efficiency is 94.3%. The SGI dc/dc stage waveforms are shown in

Figure 6.15. The dc/dc stage runs at 110 kHz with the soft-charging mode. The capacitor charging current is sinusoidal, which eliminates most of switching losses. At 450 V and 2 kW, the tested efficiency of the dc/dc stage alone is 98.1 %. The tested full range efficiency of the entire charger system, as well as two stages alone, are shown in Figure 6.16. The measured efficiency meets the design targets.

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Vgrid: 50 V/div

IL: 10 A/div

Vds_S2: 100 V/div

2 ms/div

Figure 6.14. Waveforms of the charger at the ac side.

V : 10 V/div S11 S12 S31 S32 Vgs_s1: 10 V/div gs_s3  Cmid C Cin out  Vds_S3: 2.5 V/div ICmid: 10 A/div

2 us V/div S21 S22 S41 S42

(a) (b)

Figure 6.15. (a) Dc/dc power stage circuit schematic. (b) Test waveforms at 450 V, 2 kW.

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SGI Vehicle Charger: Efficiency Curve 100%

99%

98%

97% SGI DC/DC Stage 96% PFC Stage

EFFICIENCY Two Stages 95%

94% 0 500 1000 1500 2000 2500 OUTPUT POWER (W)

Figure 6.16. Measured full range efficiency of the entire charger system, as well as two stages alone.

6.4.2. Touch Current Test

A system level TC test is conducted with the SGI charger, as shown in Figure 6.17.

The experimental comparison of the body impedance output (Vbodyout) with and without the active TC compensation are shown in Figure 6.18. The TC compensation is able to reduce the Vbodyout by 23 times from 4.5 Vrms to 0.23 Vrms, which meets the UL2202 requirement of 0.25 Vrms.

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CCM

+ Semiconductor-  Active/Diode IDM Vac based Isolated  RL + Rectifier DC/DC Converter

CCM B ITC A 1 2 ZTC (Body Impedance) DM current for power delivery 0.22 µF 1.5 k Line-frequency CM touch current A measured by ZTC 10 k B 22 nF Vbodyout ITC =Vbodyout/500 < 0.5 mArms (UL2202)

Figure 6.17. TC test of SGI charger prototype with a human body impedance network.

UL2202 Requirement: 0.25 V rms RMS: 5.4 V 23 Times of Reduction! Passed the Standard! RMS: 0.23 V

Figure 6.18. Experimental results of the TC measurement with and without the active TC compensation. With TC compensation, the Vbodyout is 0.23 Vrms, which meet the UL2202 requirement of 0.25 Vrms.

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The response of the TC local control circuit is also tested. Waveforms are shown in

Figure 6.5. The waveforms are captured during the grid voltage zero crossing, where the

CM jumps from 0 V to the bus voltage. The green signal Vds_S11 indicates the CM voltage stress across the SGI dc/dc stage. It can be seen when the grid voltage is negative, there is no CM voltage and it sudden jumps at the grid voltage zero crossing point. The blue signal

Vgs_Scom is the gate signal of the compensation circuit. The TC compensation circuit can start working within a switching cycle of the SGI dc/dc stage, which is 5 us. The fast response ensures that the TC compensation can start whenever a CM voltage is detected and also stop the compensation when the CM voltage is gone. This is extremely important to avoid over and lack of TC compensation, which eventually ensure the user safety.

Vgrid zero crossing Vgrid zero crossing TC comp. starts: no delay

CM voltage stress

No CM voltage: No CM voltage: V = 0 Vds_S11 = 0 ds_S11

20 us /div 4 us/div

V : 50 V/div V : 50 V/div V : 50 V/div V : 2.5 V/div grid ds_PFC ds_S11 gs_Scom (a) (b) Figure 6.19. Experimental results of the TC local control circuit response around grid voltage zero crossing. (a) 20 us/div view. (b) Zoomed in view of 4 us/ div.

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6.5. Conclusions

The design procedure of SGI based power converters is different from the traditional transformer-based isolated converters because semiconductor devices handle both DM power delivery and galvanic isolation. The initial design can be separated into galvanic isolation and differential mode power delivery. Galvanic isolation determines the voltage rating of the main devices. It also sets a limit a switching frequency and device output capacitance if a TC compensation is not applied. DM power delivery sets the requirements of the main device on-resistance, switching losses, circuit topology, and energy storage component size. With an effective TC compensation, the switching frequency constraint can be alleviated from the touch current requirement. A 2-kW SGI based onboard battery charger is prototyped. The PFC stage is realized by a GaN-based totem-pole topology. The dc/dc stage is an SGI based 1:1 switching capacitor circuit. A compact sensing and control system is developed based on TI 28027 and SMT isolated voltage and current sensors. The system efficiency is 94% - 96%. The system is able to pass the UL2202 touch current test.

The fast response of the proposed TC control ensures user safety by initiating and stopping the TC compensation whenever it is needed.

134

Chapter 7. Conclusions and Future Work

7.1. Conclusions

This dissertation conducts a comprehensive study of the principle, safety requirement, suitable circuit topologies, the touch current issue, the touch current compensation methods, and design guidelines of SGI based power converters. It is evident that the power electronics industry is moving towards higher power-density and higher efficiency at a lower cost and a smaller footprint. Being a fundamentally different approach, semiconductor-based galvanic isolation could utilize the unprecedented properties of WBG devices to achieve the above goals. However, there are still several challenges in this new technology. Onboard vehicle battery charger is used for a target application for a system demonstration.

The main contributions of the dissertation are summarized as follows.

. A thorough review of safety standards for the battery charger of electrical

vehicles.

. A family of SGI based circuit topologies and power loss models.

. Suitable modulation and SGI circuit topologies for different power ratings.

. A systematic analysis method of CM leakage current in SGI power converters.

135

. Low-frequency average current model for predicting the SGI power converters’

CM leakage current.

. Theatrical evaluation of passive based touch current suppression methods.

. A systematic analysis and design guideline of active touch compensation

methods.

. Implementation of the active touch current compensation method with fast

response as well as localized sensing and control.

. A design guideline of SGI based power converter, both differential power

delivery and galvanic isolation.

. A system-level demonstration of a SGI based battery charger system with high

power density and high efficiency. The system also satisfies the industrial safety

standard UL2202.

The main content of each chapter is summarized as below.

The discussion starts with a review of safety standards on galvanic isolation. The insulation requirement is that two isolated sides of the converter need to sustain several kV voltages. Moreover, the touch current test is used to evaluate the converter’s CM leakage current during operation, assuming a user touches the output. Therefore, if a converter can pass these two tests, it can be called as an isolated converter.

136

The fundamental principle of the semiconductor-based galvanic isolation is explained. It uses semiconductor switches’ output capacitance to isolate two sides of the circuit when the switches are off. When they are on, DM power can still be delivered from the primary side to the secondary side circuit. It means both the CM current block and DM power delivery are handled by the semiconductor switch. Benefits of SGI include 1) simpler system structure, 2) the potential for significant improvement of power density and easier for integration and better manufacturability. In summary, SGI based power converters can potentially achieve better performance, higher power density, higher efficiency and better manufacturability with a lower cost. However, there are still several challenges including 1)

CM leakage current, 2) narrow voltage transfer ratio and weak voltage regulation, 3) as well as requirements of high-performance high-voltage devices.

The SGI circuit topologies can be applied for most traditional inductor-based and capacitor-based power converters. SGI dc/dc building blocks, including (a) SGI based buck cell, (b) SGI based buck-boost cell and (c) SGI based boost cell, can be derived from the traditional buck, boost, and buck-boost converter. The traditional switched capacitor can be also easier modified to incorporate the SGI function. Applying the above dc/dc cells to ac/dc and dc/ac topologies, SGI PFC, SGI bridgeless PFC and SGI inverters can be derived.

Using onboard charger as an example, the selection of SGI topologies for different ac/dc power levels is discussed. A general conclusion is that for higher power systems, it is better to use capacitor-based SGI topologies, in which it only provides the galvanic isolation 137

function. The PFC and voltage regulation functions should be realized by the front-stage inductor-based power converters. Without DM voltage stress, the SGI stage can achieve very high efficiency. This situation is very similar to a resonant converter, which only realizes galvanic isolation and a narrow range of voltage regulation.

The touch current issue is one of the key challenges of SGI power converters. The TC is generated due to 1) isolation voltage stress across the dc/dc stage. Meanwhile, 2) high- frequency switches causes capacitive current between two isolated sides. A systematic method is proposed to analyze the isolation voltage stress and the touch current generation.

Moreover, a high-frequency TC current model is presented to describe the transient behavior based on the circuit parameters. A low-frequency average current is developed to easily calculate the human body output voltage, which is extremely useful in determining whether a certain combination of grounding, switch output capacitance and switching frequency can meet the safety requirements. The analysis shows that for a given SGI topology, it is preferred to have smaller Coss and fsw to reduce the touch current. When the dc outputs are floating at low frequency, the CM voltage stress is not on the SGI dc/dc stage.

The output potentials to the ground are varying with time.

The TC issue greatly limits the power density and efficiency of SGI power converters, which requires low switching frequency and devices with lower output capacitance. TC compensation is an approach to mitigate the tradeoff between satisfying safety standards and achieving high power density and high efficiency. Several passive and active TC 138

compensation approaches have been investigated. The passive filtering techniques are not very effective due to the low-frequency nature of the touch current. Instead, active compensation methods are far more effective. However, it is also more complex and more difficult to implement. A comprehensive discussion is presented on various aspects of active compensation methods, including system architecture, TC detection, compensation current injection methods, channel sharing and the timing control. At the end, a buck-boost based distribution method with local control is presented to illustrate the design process. Several local detection and control methods are explored to realize a local control of the TC compensation circuit so that the main controller does not need to concern about this issue.

The initial design can be separated into galvanic isolation and differential mode power delivery. Galvanic isolation determines the voltage rating of the main devices. It also sets a limit a switching frequency and device output capacitance if a TC compensation is not applied. DM power delivery sets the requirements of the main device on-resistance, switching losses, circuit topology, and energy storage component size. With an effective TC compensation, the switching frequency constraint can be alleviated from the touch current requirement. To validate the analysis, a 2-kW SGI based onboard battery charger is prototyped. The PFC stage is realized by a GaN-based totem-pole topology. The dc/dc stage

139

is an SGI based 1:1 switching capacitor circuit. The system efficiency is 94% - 96%. The system is able to pass the UL2202 touch current test. The fast response of the proposed TC control ensures user safety by initiating and stopping the TC compensation whenever it is needed.

7.2. Recommendations for Future Work

The following directions are recommended for the further study of semiconductor- based galvanic isolation.

On the component level, further improvement of these two technologies would greatly benefit the SGI implementation. 1) Bidirectional WBG power devices with high voltage rating, low Coss, and low on-resistance. 2) Film and ceramic capacitors having high capacitance and current rating with a small package for resonating current applications. On the power module level, power modules with common-source packaged devices would further improve the power density of SGI power converters.

Regarding the active touch current compensation methods, the capacitor-based TC compensation method should be further explored and validated in experiments. Such a compensation architecture can reduce the size of isolated power supplies for the TC compensation, which can help increase the supply power rating with a smaller size. With active compensation, the power rating of the compensation power supply is now the bottleneck of the further increase of switching frequency. Also, the centralized TC 140

compensation architecture should be further explored, which may help simplify the compensation circuits and reduce the component counts.

Also, it would be interesting to explore if the galvanic isolation can be disabled for certain circumstances. In that case, all switches in an SGI dc/dc stage remains on until a

CM voltage or CM leakage current is detected. Earlier test result always shows that the TC compensation can start and stop within a switching cycle. So, there is no safety hazard. The benefit can be gained is an over 50% reduction of the SGI dc/dc stage conduction loss and the elimination of switching losses. That means the 2 kW SGI dc/dc stage efficiency can be increased from 98.2% to 99.3%. Such a feature provides SGI a competitive edge in being able to activate the isolation function whenever it is needed.

CM noise performance of the SGI power converters needs to be evaluated. Galvanic isolation evaluated by the touch current test essentially evaluates the low-frequency CM current. It is related but not quite the same. It is expected that the high-frequency CM noise performance of SGI converters may be worse than transformer based isolated converters.

This is because 1) semiconductor device’s Coss is typically larger than the isolation capacitance of a well-designed transformer and 2) at each switching transient, the swapping of two Coss could further lower the CM impedance. One possible solution is to expand the functions of active compensation. The concept of active EMI filter can be incorporated into the existing active TC compensation hardware.

141

Being a fundamentally different approach to realize galvanic isolation, SGI is a very promising technology. It may become more competitive once the above topics and issues are addressed.

142

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