Master of Science Thesis Lund, spring 2010 Load balancing in a tiling rendering pipeline for a many-core CPU Rasmus Barringer* Engineering Physics, Lund University Supervisor: Tomas Akenine-Möller†, Lund University/Intel Corporation Examiner: Michael Doggett‡, Lund University Abstract A tiling rendering architecture subdivides a computer graphics image into smaller parts to be rendered separately. This approach extracts parallelism since different tiles can be processed independently. It also allows for efficient cache utilization for localized data, such as a tile’s portion of the frame buffer. These are all important properties to allow efficient execution on a highly parallel many-core CPU. This master thesis evaluates the traditional two-stage pipeline, consisting of a front-end and a back-end, and discusses several drawbacks of this approach. In an attempt to remedy these drawbacks, two new schemes are introduced; one that is based on conservative screen-space bounds of geometry and another that splits expensive tiles into smaller sub-tiles. *
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[email protected] Acknowledgements I would like to thank my supervisor, Tomas Akenine-Möller, for the opp- ortunity to work on this project as well as giving me valuable guidance and supervision along the way. Further thanks goes to the people at Intel for a lot of help and valuable discussions: thanks Jacob, Jon, Petrik and Robert! I would also like to thank my examiner, Michael Doggett. 1 Table of Contents 1 Introduction, aim and scope ...................................................................... 3 2 Background ................................................................................................ 4 2.1 Overview of the rasterization pipeline ............................................ 4 2.2 GPUs, CPUs and many-core architectures ....................................