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(12) United States Patent (10) Patent No.: US 8,787,364 B2 II

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(12) United States Patent (10) Patent No.: US 8,787,364 B2 II US008787364B2 (12) United States Patent (10) Patent No.: US 8,787,364 B2 Sharma et al. (45) Date of Patent: *Jul. 22, 2014 (54) SERIAL MEMORY AND IO ACCESS (51) Int. Cl. ARCHITECTURE AND SYSTEM FOR H04L 2/50 (2006.01) SWITCHED TELECOMMUNICATION AND (52) U.S. Cl. COMPUTING PLATFORMS USPC ........................................... 370/366:370/463 (58) Field of Classification Search (75) Inventors: Viswa Nath Sharma, San Ramon, CA None (US); Barton W. Stuck, Westport, CT See application file for complete search history. (US); Ching-Tai Hu, Fremont, CA (US); Yi-chang Chou, Fremont, CA (US); (56) References Cited William Chu, Elmsford, NY (US) U.S. PATENT DOCUMENTS (73) Assignee: Psimast, Inc 7.917,682 B2 * 3/2011 Bakthavathsalam .......... T10,315 - 7,929,565 B2 * 4/2011 Winter ............... ... 370/466 (*) Notice: Subject to any disclaimer, the term of this 2002/009 1884 A1* 7/2002 Chang et al. .................... 71 Of 58 patent is extended or adjusted under 35 2006/0206647 A1* 9, 2006 Stahl et al. ..... ... 710,301 U.S.C. 154(b) by 0 days. 2007/O124529 A1 5/2007 Carr et al. ..................... 710,317 This patent is Subject to a terminal dis- * cited by examiner laimer. Ca1 Primary Examiner — Clemence Han (21) Appl. No.: 13/421,826 (57) ABSTRACT 22) Filed1C Marar, 15,15, 2012 A computingCOmputing and COmmun1Cat1On arch1tecturehi ult11ZeSili a Ser1aial protocol based Switched fabric among circuit cards housed in 65 Priorrior Publication DData packagingackaging arrangement.9. IIn One embodiment,bodi eachh circuiC1rCu1t card connected to the serial protocol based switched fabric in US 2012/O 170492 A1 Jul. 5, 2012 the packaging arrangement is provided with a protocol pro cessor that enables all of the circuit cards to efficiently pro O O vide packet-based serial self-clocked communications at line Related U.S. Application Data speed. As a result, it is not necessary to arrange the circuit (62) Division of application No. 1 1/828,329, filed on Jul. cards in a hierarchical manner in order to address the prob 25, 2007, now Pat No. 8165,111. lems of Switch blocking and related traffic congestion issues s s s u wa- s that would otherwise limit the implementation of the serial (60) Provisional application No. 60/820.243, filed on Jul. protocol based backplane arrangement for housing circuit 25, 2006, provisional application No. 60/822,171, cards. filed on Aug. 11, 2006, provisional application No. 60/887,989, filed on Feb. 2, 2007. 11 Claims, 6 Drawing Sheets UEUING's CONTROL 2 is 45 - - 4 GRSS ATP NCASUATN TRAFFIC PARALLEL NGINE SCHELDULERENCAPSULATED picro ENCAPSULATE SERIAL DATA ENCAPsulATED ATA TRANSATor DATA DATA EGRESS TRAFFIC NAGER ACKET s 50 TAG UNIQUE ID) SAC 41 ADDRESSX Tas - v, NT SAC *S SAC PRC DATA 10 eBETO BUS 46 40+ 43 48 8. y - - & w 50 4. CNTRL UEUING w 5 NNE 2 DECAPSLATO NNN SCHELULER INRESS FAtre capsulate TRAFFIC ENCAPSULATE) SRAL RecTOR ATA PARALLE NGRESS DATA TRANSLATOr TRAFFIC PACKET ANAGER ADDRESS TAG KuNicued SAC rINT SAC DATA SAC BUS 44a II DATA INTRoc RSOURCE RAC TA MANAGER BUS UNICUEI SAC ) ADDRESS NSTATO coMTRLLER R INTERNAL LA CoNTRL RAM U.S. Patent Jul. 22, 2014 Sheet 1 of 6 US 8,787,364 B2 ETITQIQIWUNWE 0 ¡OTEICINE_LXE ARHOWIEWNIV/W CT-IV/C) 07 U.S. Patent Jul. 22, 2014 Sheet 3 of 6 US 8,787,364 B2 U.S. Patent Jul. 22, 2014 Sheet 4 of 6 US 8,787,364 B2 y‘61-I ZI, U.S. Patent Jul. 22, 2014 Sheet 5 of 6 US 8,787,364 B2 - U.S. Patent Jul. 22, 2014 Sheet 6 of 6 US 8,787,364 B2 LL O 2. H - US 8,787,364 B2 1. 2 SERIAL MEMORY AND OACCESS puter (PC) architecture as an example of one of the many ARCHITECTURE AND SYSTEM FOR kinds of computer architectures. SWITCHED TELECOMMUNICATION AND The Personal Computer (PC) represents the most success COMPUTING PLATFORMS ful and widely used computer architecture. Architecturally, not much has changed since the PC was first introduced in the CROSS-REFERENCE TO RELATED 1980s. From a system organization perspective, a typical PC APPLICATIONS is comprised of a single circuit board, referred to as a moth erboard, that includes a microprocessor which acts as the The present application is a divisional application of non central processing unit (CPU), a system memory and a local provisional application Ser. No. 1 1/828,329 filed Jul. 25. 10 or system bus that provides the interconnection between the 2007, now U.S. Pat. No. 8,165,111 which claims priority to CPU and the system memory and I/O ports that are typically U.S. Provisional Application Ser. No. 60/820,243, filed Jul. defined by connectors along an edge of the motherboard. One 25, 2006, entitled “Telecommunication and Computer Plat of the key reasons for the success of the PC architecture is the forms Having AdvancedTCA Based Packaging and Ethernet standardized manner by which the components are intercon Switched Fabric.” Ser. No. 60/822,171, filed Aug. 11, 2006, 15 nected. entitled “Enhanced Ethernet Protocol for Shortened Data A more recent example of another computer architecture Frames Within a Constrained Neighborhood Based on based industry standards is the server blade based system Unique ID,” and Ser. No. 60/887,989, filed Feb. 2, 2007, architecture popular in the high performance computing entitled “Processor Chip Architecture Having Integrated (HPC) arena. The server blade architecture is based upon a High-Speed Packet Switched Serial Interface, the disclosure computer organization where circuit boards or cards contain of each of which is hereby incorporated by reference. ing circuitry, referred to as blades, are adapted to deliver specialized functionality and are co-located within a unitary FIELD OF THE INVENTION housing and coupled together by a backplane. Typically, the blades can be replaced during operation, but without inter The present invention relates generally to the field of com 25 ruption of the computer's operation, by other blades of the puter architectures, and more specifically to industry stan same or different functionality. Exemplary blades may dards compliant telecommunication and computing plat include serverblades, memory blades, I/O blades, PC blades, forms that utilize a serial packet protocol over a switched management blades, and storage blades. The backplane fabric among circuit cards housed in a packaging arrange routes large amounts of data among different blades. In most ment. 30 of these HPC blade configurations, the backplane fabric is implemented by a standardized parallel bus interconnection BACKGROUND OF THE INVENTION technology such as the PCI bus. The fundamental operational blocks of a computer system In essence, a conventional computer system that realizes may be organized in the form of multiprocessor based, multi the Von Neumann Architecture comprises a core set of com 35 core based, single-instruction-multiple-data (SIMD) or mul municatively interconnected functional units which may be tiple-instruction-multiple-data (MIMD) capable parallel pro viewed as the fundamental operational blocks of a computer cessor interconnections, message passing structures and system. The functional units, singly or in combination with other arrangements well known in the art. Each Such com other functional units, are capable of performing one or more puter organization Supports a computerarchitecture requiring operations. The interconnections can be physical, logical or 40 data operations involving one or more central-processing both. The core functional units include a processing Sub units (CPUs) and a general-purpose “main memory.” Any system that executes instructions and acts upon data, a computer organization is likely to include at least a few basic memory Subsystem that cooperates with the processing Sub arithmetic logic units as part of the at least one CPU that are system to enable selected data and instructions to be stored configured to communicate with memory using a memory and transferred between the two Subsystems, an input/output 45 access operation(s) generally transparent to the program run (I/O) Subsystem that allows at least the processing Subsystem ning on the CPU. to exchange data and instructions with the network and The technology enabling the memory access operation is peripheral environment external to the computer and a bus often referred to as memory access technology (MAT) and is system over which the data and instruction interchange occur. transparent to the program or code executing on the CPU. The This set of functional units can be configured into different 50 term “memory itself conventionally denotes a plurality of computer system structures using various communication memories forming a memory hierarchy to allow the CPU the interconnection arrangements that govern the interchange of fastest access possible to the largest amount of memory and communications and the interactions between the functional the fastest transfer rate. The memory hierarchy includes at units. Each Such structure has associated with a computer least one general-purpose, relatively low-cost “main system architecture and a computer system organization. Sys 55 memory. Memories in the memory hierarchy that are above tem architecture represents those attributes of the structure the main memory are typically small, high-cost memories that are related to the logical execution of a given program on that provide relatively fast access and transfer times than the the system. The instruction set, the word length, data types, main memory. General purpose registers and the various lev bus protocol, memory addressing, I/O modalities and other els of cache memories comprising, Static RAM (SRAM) for attributes that factor into the design of software for the par 60 example, are fast memories. Fast memories are generally ticular system may be considered features of a specific system co-located with the arithmetic logic unit (ALU) within the architecture.
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