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Stress Analysis in Bipolar Transistors By Stress Analysis in Bipolar Transistors by Parameshwaran Gnanachchelvi A dissertation submitted to the Graduate Faculty of Auburn University in partial fulfillment of the requirements for the Degree of Doctor of Philosophy Auburn, Alabama May 7, 2016 Approved by Bogdan M. Wilamowski, Chair, Professor, Electrical and Computer Engineering Richard C. Jaeger, Co-chair, Distinguished University Professor (Emeritus), Electrical and Computer Engineering Jeffrey C. Suhling, Quina Distinguished Professor, Mechanical Engineering Michael Hamilton, Associate Professor, Electrical and Computer Engineering Vishwani Agrawal, James J. Danaher Professor, Electrical and Computer Engineering Abstract Stress effects in semiconductor devices have gained significant attention in semiconductor industry nowadays. Stress effect in semiconductor devices is used as a beneficial effect in sensor applications and strain engineering and efforts are taken to increase these effects. Strain engineering is widely used for MOSFETs. Performance of SiGe based heterostructure bipolar transistors (HBTs) is improved by bandgap and strain engineering. However this approach is not fully developed for Si bipolar junction transistors (BJTs). While stress effects are useful in some areas there are some unwanted stress effects as well. The unintentional stresses developed during fabrication, processing and packaging are harmful in semiconductor devices and efforts are taken to mitigate these stress effects. In this research work, stress-induced changes were investigated in the perspective of improvement for strain engineering in Si BJTs as well as mitigation of stress effects in precision analog circuits. npn and pnp BJTs on (100) and (111) planes were studied using experimental and modeling approaches. Modeling approach was mainly used for this study in order to overcome the practical difficulties associated with fabrication of devices with different orientation and sizes and controlled application of stress in various orientations for measurements. Measurements were taken for in-plane normal stress and the validity of the model was verified. A new one-dimensional numerical model was developed in Matlab in order to make the stress analysis easier and more in-depth with short running time. Simulation results of the 1-D model and Sentaurus TCAD tool were compared and both results showed very good ii agreement. While commercial TCAD tools usually takes tens of minutes for 2-D or hours for 3- D simulations for this type of stress analysis, the newly developed 1-D model gives comparable results in seconds and without any loss of information generated. This model can be used for fast stress analysis/prediction in vertical or lateral npn/pnp BJTs in any plane and will help in developing optimal design for strain engineering in BJTs or stress mitigation in analog circuits. The stress induced changes in vertical and lateral bipolar transistors on (100) plane were quantitatively analyzed for different stress orientations. Our analysis revealed that for a vertical npn transistor substantial enhancement in collector current (IC), dc current gain (), cutoff frequency (fT), and maximum oscillation frequency (fmax) can be achieved using an uniaxial in- plane compressive or an out-of-plane tensile stress. In a vertical pnp considerable improvement in IC can be achieved with an in-plane or an out-of-plane compressive stress while the changes in , fT and fmax are minimal. Lateral pnp BJTs showed much higher improvement for in-plane longitudinal compressive stress. In addition, lateral npn BJTs showed higher improvement for out-of-plane compressive stress. These results revealed a promising opportunity for strain engineering in both vertical and lateral Si BJTs. This study also revealed that the transport limited BJTs are less sensitive to stress than injection limited BJTs. In addition, vertical pnp on (100) silicon is less sensitive to stress than the vertical npn on (100) plane or vertical npn or pnp on (111) plane. On (111) silicon vertical npn BJTs are less sensitive than the vertical pnp BJTs. Finally, stress effects in precision analog circuits have been explored with the help of Spice simulations incorporating the 1-D theoretical model. Some methods for stress mitigation in precision analog circuits are also suggested including usage of less sensitive BJTs whenever possible, keeping the matching BJTs in close iii proximity to avoid stress gradients, avoiding high stress regions in chips, usage of enclosed lateral devices for stress compensation. iv Acknowledgement I am always thankful to Auburn University and the Department of Electrical and Computer Engineering for providing me a good environment for my graduate studies. First, I would like to express my sincere gratitude to my major advisor, Dr. Bogdan Wilamowski, for providing me an opportunity for PhD study at Auburn University, and for his guidance, encouragement, understanding and support throughout my study. Without his full support I would have not achieved this success in my life. I am grateful for his enthusiasm for Electrical Engineering and his belief in me as a researcher. I would also like to specifically thank my Co- advisor, Dr. Richard Jaeger, for providing me continuous support and patient guidance for my research work and the publications. I also would like to express my heartfelt gratitude to my graduate committee members Dr. Jeffrey Suhling, Dr. Michael Hamilton, Dr. Viswani Agrawal and the University reader of this dissertation Dr. Vitaly Vodyanoy for their constructive inputs, support and guidance. I would like to thank Dr. Guofu Niu for his help in Sentaurus simulations, radio frequency analysis and great support in providing valuable input for my research publication. I would like to thank Dr. Safina Hussain for helping and training me in 4-point bending fixture measurements, for developing flex connector for measurements, and also proving me some experimental data for comparison with the simulation results. I also would like to thank Dr. Wu Xing for his extended help in solving any programming issues throughout my research work. v I also express my sincere thanks to my fellow graduate students Dr. Michael Pukish, Jordan Richardson, Dr. Philip Reiner, Jiao Yu, Dr. Hao Yu, Dr. Tiantian Xie and Tim Brown for their support and for making work hours pleasant and motivating. I am also thankful to Charles Ellis, Mike Palmer and all other staff in Electrical and Computer Engineering Department for their support. I would like to thank my family members who provided moral support during the pursuit of this academic goal. I would like to thank my mother Kanagambikai Thirunavukkarasu and my brothers Kathirvel Thirunavukkarasu, Dr. Gnanavel Thirunavukkarasu and Thangavel Thirunavukkarasu for their encouragement. I dedicate my success to my late father Velupillai Thirunavukkarasu who was always proud of my achievements. I also would like to thank my husband Dr. Kodeeswaran Parameshwaran for his continuous inspiration. Finally, but not least, I am also greatly thankful for my lovely son Mayooran Selliah who always been a ray of hope and happiness in my life, for his understanding, unwavering love and help, during my doctoral studies. This research work was supported by the Semiconductor Research Corporation (SRC), The Center for Advanced Vehicle and Extreme Environment Electronics (CAVE3) and Alabama Microelectronics Science and Technology Center (AMNSTC). vi Table of Contents Abstract …………………………………………………………………………………………..ii Acknowledgments …………………………………...………………………………………….. v List of Tables…..……………………………….………………….………………………..…....xi List of Figures…………………………………………………………..…………………...…...xii INTRODUCTION ................................................................................................................................ 1 1.1 Stress effects in semiconductor devices ............................................................................................................. 1 1.2 Previous research works on stress effects in bipolar transistors and analog circuits ......................................... 6 1.3 Scope of the research ......................................................................................................................................... 9 1.4 Structure of this dissertation ............................................................................................................................ 10 A REVIEW ON STRESS EFFECTS ON SEMICONDUCTOR BAND STRUCTURE AND CARRIER MOBILITY ...................................................................................................................... 12 2.1 Introduction...................................................................................................................................................... 12 2.2 Stress, strain and tensors .................................................................................................................................. 12 2.3 Stress effects on semiconductor band structure ............................................................................................... 15 2.4 Deformation potential theory ........................................................................................................................... 16 2.5 Stress effect in mobility ................................................................................................................................... 19 2.6 Piezoresistive concept development ...............................................................................................................
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