Automatic Microprocessor Performance Bug Detection Erick Carvajal Barboza∗, Sara Jacob∗, Mahesh Ketkary, Michael Kishinevskyy, Paul Gratz∗, Jiang Hu∗ ∗Texas A&M University fecarvajal, sarajacob 96,
[email protected],
[email protected] yIntel Corportation fmahesh.c.ketkar,
[email protected] Abstract—Processor design validation and debug is a difficult snoop filter eviction bug [42]. Here the performance regression and complex task, which consumes the lion’s share of the was > 10% on several benchmarks. The bug took several design process. Design bugs that affect processor performance months of debugging effort before being fully characterized. rather than its functionality are especially difficult to catch, particularly in new microarchitectures. This is because, unlike In a competitive environment where time to market and functional bugs, the correct processor performance of new performance are essential, there is a critical need for new, microarchitectures on complex, long-running benchmarks is more automated mechanisms for performance debugging. typically not deterministically known. Thus, when performance To date, little prior research in performance debugging exists, benchmarking new microarchitectures, performance teams may despite its importance and difficulty. The few existing works [9], assume that the design is correct when the performance of the new microarchitecture exceeds that of the previous generation, [51], [53] take an approach of manually constructing a reference despite significant performance regressions existing in the design. model for comparison. However, as described by Ho et al. [26], In this work we present a two-stage, machine learning-based the same bug can be repeated in the model and thus cannot be methodology that is able to detect the existence of performance detected.