DOCSLIB.ORG

FDTD) Algorithms on a Selection of High Performance Multiprocessor Computing Systems

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
FDTD) Algorithms on a Selection of High Performance Multiprocessor Computing Systems A comparative analysis of the performance and deployment overhead of parallelized Finite Difference Time Domain (FDTD) algorithms on a selection of high performance multiprocessor computing systems by RG Ilgner Dissertation presented in fulfilment of the requirements for the degree Doctor of Philosophy in the Faculty of Engineering at Stellenbosch University Promoter: Prof DB Davidson Department of Electrical & Electronic Engineering December 2013 Stellenbosch University http://scholar.sun.ac.za Declaration By submitting this thesis electronically, I declare that the entirety of the work contained therein is my own, original work, that I am the sole author thereof (save to the extent explicitly otherwise stated), that reproduction and publication thereof by Stellenbosch University will not infringe any third party rights and that I have not previously in its entirety or in part submitted it for obtaining any qualification. December 2013 Copyright © 2013 Stellenbosch University All rights reserved Stellenbosch University http://scholar.sun.ac.za Abstract The parallel FDTD method as used in computational electromagnetics is implemented on a variety of different high performance computing platforms. These parallel FDTD implementations have regularly been compared in terms of performance or purchase cost, but very little systematic consideration has been given to how much effort has been used to create the parallel FDTD for a specific computing architecture. The deployment effort for these platforms has changed dramatically with time, the deployment time span used to create FDTD implementations in 1980 ranging from months, to the contemporary scenario where parallel FDTD methods can be implemented on a supercomputer in a matter of hours. This thesis compares the effort required to deploy the parallel FDTD on selected computing platforms from the constituents that make up the deployment effort, such as coding complexity and time of coding. It uses the deployment and performance of the serial FDTD method on a single personal computer as a benchmark and examines the deployments of the parallel FDTD using different parallelisation techniques. These FDTD deployments are then analysed and compared against one another in order to determine the common characteristics between the FDTD implementations on various computing platforms with differing parallelisation techniques. Although subjective in some instances, these characteristics are quantified and compared in tabular form, by using the research information created by the parallel FDTD implementations. The deployment effort is of interest to scientists and engineers considering the creation or purchase of an FDTD-like solution on a high performance computing platform. Although the FDTD method has been considered to be a brute force approach to solving computational electromagnetic problems in the past, this was very probably a factor of the relatively weak computing platforms which took very long periods to process small model sizes. This thesis will describe the current implementations of the parallel FDTD method, made up of a combination of several techniques. These techniques can be easily deployed in a relatively quick time frame on computing architectures ranging from IBM’s Bluegene/P to the amalgamation of multicore processor and graphics processing unit, known as an accelerated processing unit. i Stellenbosch University http://scholar.sun.ac.za Opsomming Die parallel Eindige Verskil Tyd Domein (Eng: FDTD) metode word gebruik in numeriese elektromagnetika en kan op verskeie hoë werkverrigting rekenaars geïmplementeer word. Hierdie parallele FDTD implementasies word gereeld in terme van werkverrigting of aankoop koste vergelyk, maar word bitter min sistematies oorweeg in terme van die hoeveelheid moeite wat dit geverg het om die parallele FDTD vir 'n spesifieke rekenaar argitektuur te skep. Mettertyd het die moeite om die platforms te ontplooi dramaties verander, in the 1980's het die ontplooings tyd tipies maande beloop waarteenoor dit vandag binne 'n kwessie van ure gedoen kan word. Hierdie tesis vergelyk die inspanning wat nodig is om die parallelle FDTD op geselekteerde rekenaar platforms te ontplooi deur te kyk na faktore soos die kompleksiteit van kodering en die tyd wat dit vat om 'n kode te implementeer. Die werkverrigting van die serie FDTD metode, geïmplementeer op 'n enkele persoonlike rekenaar word gebruik as 'n maatstaf om die ontplooing van die parallel FDTD met verskeie parallelisasie tegnieke te evalueer. Deur hierdie FDTD ontplooiings met verskillende parallelisasie tegnieke te ontleed en te vergelyk word die gemeenskaplike eienskappe bepaal vir verskeie rekenaar platforms. Alhoewel sommige gevalle subjektief is, is hierdie eienskappe gekwantifiseer en vergelyk in tabelvorm deur gebruik te maak van die navorsings inligting geskep deur die parallel FDTD implementasies. Die ontplooiings moeite is belangrik vir wetenskaplikes en ingenieurs wat moet besluit tussen die ontwikkeling of aankoop van 'n FDTD tipe oplossing op 'n höe werkverrigting rekenaar. Hoewel die FDTD metode in die verlede beskou was as 'n brute krag benadering tot die oplossing van elektromagnetiese probleme was dit waarskynlik weens die relatiewe swak rekenaar platforms wat lank gevat het om klein modelle te verwerk. Hierdie tesis beskryf die moderne implementering van die parallele FDTD metode, bestaande uit 'n kombinasie van verskeie tegnieke. Hierdie tegnieke kan maklik in 'n relatiewe kort tydsbestek ontplooi word op rekenaar argitekture wat wissel van IBM se BlueGene / P tot die samesmelting van multikern verwerkers en grafiese verwerkings eenhede, beter bekend as 'n versnelde verwerkings eenheid. ii Stellenbosch University http://scholar.sun.ac.za Acknowledgments I would like to thank supervisor Professor David Davidson for his assistance and motivation in the writing of this of dissertation and the lengthy path of enlightenment that has led me here. Thank you to Neilen Marais, Evan Lezar, and Kevin Colville, for their valuable reviews or input. Very many thanks to the helpful technical support crew from the Centre for High Performance Computing for their technical assistance and interesting discussions about High Performance Computing. My gratitude to my family for giving me the time to do the thesis; in particular my thanks to Marie- Claire for her constant support and helping with the formatting and checking of the thesis. There are many others that I am grateful to, but am avoiding writing a lengthy list in case I omit someone. My final acknowledgment is to all of the people who have assisted via articles and discussions in internet forums, blogs and newsgroups. I have been both encouraged by these original interactions, and humbled by the selfless contributions and experience by others. I have found this a source of motivation in completing several part of this thesis. iii Glossary & Acronyms Stellenbosch University http://scholar.sun.ac.za Glossary & Acronyms The reader is reminded that this thesis contains many domain specific acronyms and that these are written out in full at the first mention in every chapter. The Glossary compiled below should serve as a fall-back to identify all the acronyms, some of which are used in the chapter description below. ABC Absorbing Boundary Conditions ALU Arithmetic Logic Unit AMD Advanced Micro Devices; Manufacturer of computer processors API Application Programming Interface APU Accelerated Processing Unit ARM Advanced RISC Machines; Manufacturer of RISC based computer processors ASP Associative String Processor ASIC Application Specific Integrated Circuit ATI Array Technologies Industry; GPU division for AMD processors AUTOCAD Commercial Computer Aided Design software AVX Advanced Vector eXtensions Blade A high performance process board consisting of closely coupled processors C Higher level computing language C++ Higher level computing language using class structures CAD Computer Aided Design CHPC Centre for High Performance Computing in Cape Town CISC Complex Instruction Set Computing CMP Chip-Multiprocessors CMU Computer Memory Unit: A high performance board containing several processors and associated memory; Used in the SUN M9000 Core A core is considered to be a physical component of a processor performing at least one program thread CPU Computer Processing Unit CUDA Compute Unified Device Architecture DirectCompute Application programming interface that supports General Purpose computing on graphical processors DirectX11 Application programming interface for graphics and games programming DRAM Dynamic Random Access Memory DSMP Distributed Shared Memory Processor Dxf Drawing eXchange Format; an AUTOCAD data exchange file format FDTD Finite Difference Time Domain FEKO Electromagnetic modelling software based on MOM FEM Finite Element Method FMA Fused Multiply Add, a hardware based acceleration combining the multiplication and the addition instruction iv Glossary & Acronyms Stellenbosch University http://scholar.sun.ac.za FORTRAN FORmula TRANslation; a higher level computing language FPGA Field Programmable Gate Array FPU Floating Point Unit GB Giga Byte GEMS Electromagnetic modelling software based on FDTD GFLOP Giga Floating point Operations GPGPU General Purpose GPU GPS Global Positioning System; a system of satellites used for global navigation GPU Graphical Processing Unit GPUDirect A technology from Nvidia that will allow the exchange of data between dedicated GPU memories without having to access the Host computer Hadoop High performance
Load more

Recommended publications
  • Slicing (Draft)
    Handling Parallelism in a Concurrency Model Mischael Schill, Sebastian Nanz, and Bertrand Meyer ETH Zurich, Switzerland [email protected] Abstract. Programming models for concurrency are optimized for deal- ing with nondeterminism, for example to handle asynchronously arriving events. To shield the developer from data race errors effectively, such models may prevent shared access to data altogether. However, this re- striction also makes them unsuitable for applications that require data parallelism. We present a library-based approach for permitting parallel access to arrays while preserving the safety guarantees of the original model. When applied to SCOOP, an object-oriented concurrency model, the approach exhibits a negligible performance overhead compared to or- dinary threaded implementations of two parallel benchmark programs. 1 Introduction Writing a multithreaded program can have a variety of very different motiva- tions [1]. Oftentimes, multithreading is a functional requirement: it enables ap- plications to remain responsive to input, for example when using a graphical user interface. Furthermore, it is also an effective program structuring technique that makes it possible to handle nondeterministic events in a modular way; develop- ers take advantage of this fact when designing reactive and event-based systems. In all these cases, multithreading is said to provide concurrency. In contrast to this, the multicore revolution has accentuated the use of multithreading for im- proving performance when executing programs on a multicore machine. In this case, multithreading is said to provide parallelism. Programming models for multithreaded programming generally support ei- ther concurrency or parallelism. For example, the Actor model [2] or Simple Con- current Object-Oriented Programming (SCOOP) [3,4] are typical concurrency models: they are optimized for coordination and event handling, and provide safety guarantees such as absence of data races.
    [Show full text]
  • Assessing Gains from Parallel Computation on a Supercomputer
    Volume 35, Issue 1 Assessing gains from parallel computation on a supercomputer Lilia Maliar Stanford University Abstract We assess gains from parallel computation on Backlight supercomputer. The information transfers are expensive. We find that to make parallel computation efficient, a task per core must be sufficiently large, ranging from few seconds to one minute depending on the number of cores employed. For small problems, the shared memory programming (OpenMP) and a hybrid of shared and distributive memory programming (OpenMP&MPI) leads to a higher efficiency of parallelization than the distributive memory programming (MPI) alone. I acknowledge XSEDE grant TG-ASC120048, and I thank Roberto Gomez, Phillip Blood and Rick Costa, scientific specialists from the Pittsburgh Supercomputing Center, for technical support. I also acknowledge support from the Hoover Institution and Department of Economics at Stanford University, University of Alicante, Ivie, and the Spanish Ministry of Science and Innovation under the grant ECO2012- 36719. I thank the editor, two anonymous referees, and Eric Aldrich, Yongyang Cai, Kenneth L. Judd, Serguei Maliar and Rafael Valero for useful comments. Citation: Lilia Maliar, (2015) ''Assessing gains from parallel computation on a supercomputer'', Economics Bulletin, Volume 35, Issue 1, pages 159-167 Contact: Lilia Maliar - [email protected]. Submitted: September 17, 2014. Published: March 11, 2015. 1 Introduction The speed of processors was steadily growing over the last few decades. However, this growth has a natural limit (because the speed of electricity along the conducting material is limited and because a thickness and length of the conducting material is limited). The recent progress in solving computationally intense problems is related to parallel computation.
    [Show full text]
  • Instruction Level Parallelism Example
    Instruction Level Parallelism Example Is Jule peaty or weak-minded when highlighting some heckles foreground thenceforth? Homoerotic and commendatory Shelby still pinks his pronephros inly. Overneat Kermit never beams so quaveringly or fecundated any academicians effectively. Summary of parallelism create readable and as with a bit says if we currently being considered to resolve these two machine of a pretty cool explanation. Once plug, it book the parallel grammatical structure which creates a truly memorable phrase. In order to accomplish whereas, a hybrid approach is designed to whatever advantage of streaming SIMD instructions for each faction the awful that executes in parallel on independent cores. For the ILPA, there is one more type of instruction possible, which is the special instruction type for the dedicated hardware units. Advantages and high for example? Two which is already present data is, to process includes comprehensive career related services that instruction level parallelism example how many diverse influences on. Simple uses of parallelism create readable and understandable passages. Also note that a data dependent elements that has to be imported from another core in another processor is much higher than either of the previous two costs. Why the charge of the proton does not transfer to the neutron in the nuclei? The OPENMP code is implemented in advance way leaving each thread can climb up an element from first vector and compare after all the elements in you second vector and forth thread will appear able to execute simultaneously in parallel. To be ready to instruction level parallelism in this allows enormous reduction in memory.
    [Show full text]
  • Minimizing Startup Costs for Performance-Critical Threading
    Minimizing Startup Costs for Performance-Critical Threading Anthony M. Castaldo R. Clint Whaley Department of Computer Science Department of Computer Science University of Texas at San Antonio University of Texas at San Antonio San Antonio, TX 78249 San Antonio, TX 78249 Email : [email protected] Email : [email protected] Abstract—Using the well-known ATLAS and LAPACK dense on several eight core systems running a standard Linux OS, linear algebra libraries, we demonstrate that the parallel manage- ATLAS produced alarmingly poor parallel performance even ment overhead (PMO) can grow with problem size on even stati- on compute bound, highly parallelizable problems such as cally scheduled parallel programs with minimal task interaction. Therefore, the widely held view that these thread management matrix multiply. issues can be ignored in such computationally intensive libraries is wrong, and leads to substantial slowdown on today’s machines. Dense linear algebra libraries like ATLAS and LAPACK [2] We survey several methods for reducing this overhead, the are almost ideal targets for parallelism: the problems are best of which we have not seen in the literature. Finally, we regular and often easily decomposed into subproblems of equal demonstrate that by applying these techniques at the kernel level, performance in applications such as LU and QR factorizations complexity, minimizing any need for dynamic task scheduling, can be improved by almost 40% for small problems, and as load balancing or coordination. Many have high data reuse much as 15% for large O(N 3) computations. These techniques and therefore require relatively modest data movement. Until are completely general, and should yield significant speedup in recently, ATLAS achieved good parallel speedup using simple almost any performance-critical operation.
    [Show full text]
  • 18-447 Lecture 21: Parallelism – ILP to Multicores Parallel
    CMU 18‐447 S’10 L21‐1 © 2010 J. C. Hoe J. F. Martínez 18‐447 Lecture 21: Parallelism –ILP to Multicores James C. Hoe Dept of ECE, CMU April 7, 2010 Announcements: Lab 4 due this week Optional reading assignments below. Handouts: The Microarchitecture of Superscalar Processors, Smith and Sohi, Proceedings of IEEE, 12/1995. (on Blackboard) The MIPS R10000 Superscalar Microprocessor, Yeager, IEEE Micro, 4/1996. (on Blackboard) Design Challenges of Technology Scaling, Shekhar Borkar, IEEE Micro, 1999. (on Blackboard) CMU 18‐447 S’10 L21‐2 © 2010 J. C. Hoe Parallel Processing 101 J. F. Martínez Assume you have N units of work and each unit of work takes 1 unit‐time on 1 processing element (PE) ‐ with 1 PE, it will take N unit‐time to complete the N units of work ‐ with p PEs, how long does it take to complete the same N units of work? “Ideally”, speedup is “linear” with p runtime speedup runtime speedup= sequential runtimeparalle l N/p 1 p= 1 2 3 4 5 . p= 1 2 3 4 5 . CMU 18‐447 S’10 L21‐3 © 2010 J. C. Hoe It may be linear, but . J. F. Martínez S 4 3 2 1 32 64 p How could this be? CMU 18‐447 S’10 L21‐4 © 2010 J. C. Hoe Parallelization Overhead J. F. Martínez The cheapest algorithm may not be the most scalable, s.t., runtimeparalle l@p=1 = Kruntimesequential and K>1 and speedup = p/K K is known facetiously as the “parallel slowdown” Communications between PEs are not free ‐ a PE may spend extra instructions/time in the act of sending or receiving data ‐ a PE may spend extra time waiting for data to arrive from another PEa function of latency and bandwidth ‐ a PE may spend extra time waiting for another PE to get to a particular point of the computation (a.k.a.
    [Show full text]
  • Performance of Physics-Driven Procedural Animation of Character Locomotion for Bipedal and Quadrupedal Gait
    Thesis no: MECS-2015-03 Performance of Physics-Driven Procedural Animation of Character Locomotion For Bipedal and Quadrupedal Gait Jarl Larsson Faculty of Computing Blekinge Institute of Technology SE371 79 Karlskrona, Sweden This thesis is submitted to the Faculty of Computing at Blekinge Institute of Technology in partial fulllment of the requirements for the degree of Master of Science in Engineering: Game and Software Engineering. The thesis is equivalent to 20 weeks of full-time studies. Contact Information: Author: Jarl Larsson E-mail: [email protected] University advisors: Ph.D. Veronica Sundstedt Ph.D. Martin Fredriksson Department of Creative Technologies Faculty of Computing Internet : www.bth.se Blekinge Institute of Technology Phone : +46 455 38 50 00 SE371 79 Karlskrona, Sweden Fax : +46 455 38 50 57 Abstract Context. Animation of character locomotion is an important part of computer animation and games. It is a vital aspect in achieving be- lievable behaviour and articulation for virtual characters. For games there is also often a need for supporting real-time reactive behaviour in an animation as a response to direct or indirect user interaction, which have given rise to procedural solutions to generate animation of locomotion. Objectives. In this thesis the performance aspects for procedurally generating animation of locomotion within real-time constraints is evaluated, for bipeds and quadrupeds, and for simulations of sev- eral characters. A general pose-driven feedback algorithm for physics- driven character locomotion is implemented for this purpose. Methods. The execution time of the locomotion algorithm is evalu- ated using an automated experiment process, in which real-time gait simulations of incrementing character population count are instanti- ated and measured, for the bipedal and quadrupedal gaits.
    [Show full text]
  • Easy Dataflow Programming in Clusters with UPC++ Depspawn
    This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TPDS.2018.2884716 IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1 Easy Dataflow Programming in Clusters with UPC++ DepSpawn Basilio B. Fraguela, Diego Andrade Abstract—The Partitioned Global Address Space (PGAS) programming model is one of the most relevant proposals to improve the ability of developers to exploit distributed memory systems. However, despite its important advantages with respect to the traditional message-passing paradigm, PGAS has not been yet widely adopted. We think that PGAS libraries are more promising than languages because they avoid the requirement to (re)write the applications using them, with the implied uncertainties related to portability and interoperability with the vast amount of APIs and libraries that exist for widespread languages. Nevertheless, the need to embed these libraries within a host language can limit their expressiveness and very useful features can be missing. This paper contributes to the advance of PGAS by enabling the simple development of arbitrarily complex task-parallel codes following a dataflow approach on top of the PGAS UPC++ library, implemented in C++. In addition, our proposal, called UPC++ DepSpawn, relies on an optimized multithreaded runtime that provides very competitive performance, as our experimental evaluation shows. Index Terms—libraries, parallel programming models, distributed memory, multithreading, programmability, dataflow F 1 INTRODUCTION HILE the exploitation of parallelism is never trivial, Namely, the private space is always the one that can be more W this is particularly true in the case of distributed efficiently accessed and the shared local space is accessible memory systems such as clusters.
    [Show full text]
  • Econstor Wirtschaft Leibniz Information Centre Make Your Publications Visible
    A Service of Leibniz-Informationszentrum econstor Wirtschaft Leibniz Information Centre Make Your Publications Visible. zbw for Economics Kuchen, Herbert (Ed.); Majchrzak, Tim A. (Ed.); Müller-Olm, Markus (Ed.) Working Paper Tagungsband 16. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS'11): 26. bis 28. September 2011, Schloss Raesfeld, Münsterland Arbeitsberichte des Instituts für Wirtschaftsinformatik, No. 132 Provided in Cooperation with: University of Münster, Department of Information Systems Suggested Citation: Kuchen, Herbert (Ed.); Majchrzak, Tim A. (Ed.); Müller-Olm, Markus (Ed.) (2011) : Tagungsband 16. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS'11): 26. bis 28. September 2011, Schloss Raesfeld, Münsterland, Arbeitsberichte des Instituts für Wirtschaftsinformatik, No. 132, Westfälische Wilhelms- Universität Münster, Institut für Wirtschaftsinformatik, Münster This Version is available at: http://hdl.handle.net/10419/59558 Standard-Nutzungsbedingungen: Terms of use: Die Dokumente auf EconStor dürfen zu eigenen wissenschaftlichen Documents in EconStor may be saved and copied for your Zwecken und zum Privatgebrauch gespeichert und kopiert werden. personal and scholarly purposes. Sie dürfen die Dokumente nicht für öffentliche oder kommerzielle You are not to copy documents for public or commercial Zwecke vervielfältigen, öffentlich ausstellen, öffentlich zugänglich purposes, to exhibit the documents publicly, to make them machen, vertreiben oder anderweitig nutzen. publicly available on the internet, or to distribute or otherwise use the documents in public. Sofern die Verfasser die Dokumente unter Open-Content-Lizenzen (insbesondere CC-Lizenzen) zur Verfügung gestellt haben sollten, If the documents have been made available under an Open gelten abweichend von diesen Nutzungsbedingungen die in der dort Content Licence (especially Creative Commons Licences), you genannten Lizenz gewährten Nutzungsrechte.
    [Show full text]
  • Extracting Parallelism from Legacy Sequential Code Using Transactional Memory
    Extracting Parallelism from Legacy Sequential Code Using Transactional Memory Mohamed M. Saad Dissertation submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Engineering Binoy Ravindran, Chair Anil Kumar S. Vullikanti Paul E. Plassmann Robert P. Broadwater Roberto Palmieri Sedki Mohamed Riad May 25, 2016 Blacksburg, Virginia Keywords: Transaction Memory, Automatic Parallelization, Low-Level Virtual Machine, Optimistic Concurrency, Speculative Execution, Legacy Systems, Age Commitment Order, Low-Level TM Semantics, TM Friendly Semantics Copyright 2016, Mohamed M. Saad Extracting Parallelism from Legacy Sequential Code Using Transactional Memory Mohamed M. Saad (ABSTRACT) Increasing the number of processors has become the mainstream for the modern chip design approaches. However, most applications are designed or written for single core processors; so they do not benefit from the numerous underlying computation resources. Moreover, there exists a large base of legacy software which requires an immense effort and cost of rewriting and re-engineering to be made parallel. In the past decades, there has been a growing interest in automatic parallelization. This is to relieve programmers from the painful and error-prone manual parallelization process, and to cope with new architecture trend of multi-core and many-core CPUs. Automatic parallelization techniques vary in properties such as: the level of paraellism (e.g., instructions, loops, traces, tasks); the need for custom hardware support; using optimistic execution or relying on conservative decisions; online, offline or both; and the level of source code exposure. Transactional Memory (TM) has emerged as a powerful concurrency control abstraction.
    [Show full text]
  • Optimization Techniques for Efficient HTA Programs
    Parallel Computing 38 (2012) 465–484 Contents lists available at SciVerse ScienceDirect Parallel Computing journal homepage: www.elsevier.com/locate/parco Optimization techniques for efficient HTA programs ⇑ Basilio B. Fraguela a, , Ganesh Bikshandi b, Jia Guo c, María J. Garzarán c, David Padua c, Christoph von Praun d a Depto. de Electrónica e Sistemas, Universidade da Coruña, Facultade de Informática, Campus de Elviña, S/N, 15071 A Coruña, Spain b Intel Labs, Intel Technology India Pvt. Ltd., Bangalore 560 103, Karnataka, India c Dept. of Computer Science, University of Illinois at Urbana-Champaign, 201 North Goodwin Avenue, Urbana, 61801 IL, USA d Fakultät Informatik, Georg-Simon-Ohm Hochschule, Postfach 210320, 90121 Nuremberg, Germany article info abstract Article history: Object oriented languages can be easily extended with new data types, which facilitate Received 20 May 2011 prototyping new language extensions. A very challenging problem is the development of Received in revised form 11 May 2012 data types encapsulating data parallel operations, which could improve parallel program- Accepted 14 May 2012 ming productivity. However, the use of class libraries to implement data types, particularly Available online 22 May 2012 when they encapsulate parallelism, comes at the expense of performance overhead. This paper describes our experience with the implementation of a C++ data type called Keywords: hierarchically tiled array (HTA). This object includes data parallel operations and allows Parallel programming the manipulation of tiles to facilitate developing efficient parallel codes and codes with Optimization Programmability high degree of locality. The initial performance of the HTA programs we wrote was lower Libraries than that of their conventional MPI-based counterparts.
    [Show full text]
  • Introduction to MPI
    Introduction to MPI Jerome Vienne Texas Advanced Computing Center September 19th, 2013 Email: [email protected] 1 Course Objectives & Assumptions • Objectives – Teach basics of MPI-Programming – Share information related to running MPI programs on Stampede • Assumptions – The audience has the basic understanding of C or Fortran programming – The audience has access to MPI installation either locally or remotely 2 Content Overview • Basic concepts related to MPI • Environment Management MPI routines • Compiling and running MPI programs • Types of communication – Point-to-Point communication routines – Collective communication routines • Examples • Summary 3 Content Overview • Basic concepts related to MPI • Environment Management MPI routines • Compiling and running MPI programs • Types of communication – Point-to-Point communication routines – Collective communication routines • Examples • Summary 4 Different Programming Models P0 P1 P0 P1 P0 P1 Logical shared memory Shared Memory Memory Memory Memory Memory Shared Memory Model Distributed Memory Model Partitioned Global Address Space SHMEM, DSM MPI Global Arrays, UPC, CAF • OpenMP falls under the category of Shared Memory Model • MPI (Message Passing Interface) falls under the category of Distributed Memory Model 5 History of Message Passing Interface (MPI) • Before 1989, no portable message passing library – Code on nCUBE/10 code doesn’t work on Intel iPSC • Standardization was needed – Efficiency, portability and flexibility was desired • Result of this effort: MPI – MPI is a
    [Show full text]
  • Performance Loss Between Concept and Keyboard
    Performance loss between concept and keyboard Andr´asZ. Salamon1;2 and Vashti Galpin3 1 Computing Laboratory, University of Oxford 2 Oxford-Man Institute of Quantitative Finance 3 LFCS, School of Informatics, University of Edinburgh Abstract. Standards bodies and commercial software vendors have defined parallel constructs to harness the parallelism in computations. Using the task graph model of parallel program execution, we show how common programming constructs that impose series-parallel task dependencies can lead to unbounded slowdown compared to the inherent parallelism in the algorithm. We describe various ways in which this slowdown can be avoided. Inexpensive multicore processors have brought parallelism to the desktop computer [2] and users would like to take advantage of this parallelism for faster program execution. Standards for multiple-processor programming such as OpenCL [7] and commercial numeri- cal software such as Matlab4 and Mathematica5 include language constructs for parallelism. Our position is that these constructs may limit the amount of parallelism, causing slowdown, but we also argue that there are ways to avoid this unnecessary loss in performance. With the projected progression from multicore computing (2-8 cores) to manycore computing (hundreds of cores) [10], we believe that parallel computing systems should avoid slowdown at the point of expressing the intention of the programmer, between the concept and the keyboard. We focus on a specific structure on the dependencies between program tasks which some constructs impose. This structure is called series-parallel and can be most easily expressed as those task graphs generated by the language P ::= seq(P; P ) j par(P; P ) j a where a is a task or activity which represents some amount of program code (possibly as small as a single arithmetic operation) to be executed on one processor.
    [Show full text]