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Ultra-Low-Power 2.4 Ghz Hartley Oscillator

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Ultra-Low-Power 2.4 Ghz Hartley Oscillator Ultra-low-power 2.4 GHz Hartley oscillator R. M. da Ponte and F. R. Sousa RFIC Research Group - Electrical Engineering Department Federal University of Santa Catarina Florianopolis, SC, Brazil Email: [email protected], [email protected] Abstract—This paper reports a design of an oscillator Undoubtedly, the current state-of-art of LC oscillators for ultra-low-power applications. The circuit was designed present an amount of techniques that upgrades the overall in a standard IBM 0.18 µm process and is based on the performance which is generally compared through the classical Hartley oscillator topology. Monte Carlo results showed that the oscillations are sustained with only 88 µW of DC power expression of figure-of-merit (FoM): consumption from 1-V supply voltage and with a phase noise fo PDC of -106.7 dBc/Hz at 1 MHz offset frequency, resulting in a F oM = 20 log − 10 log − L(∆f) (1) FoM of 184.5 - which is suitable for ultra-low power applications. ∆f 1mW where fo is the oscillation frequency, PDC is the DC power consumption and L(∆f) is the phase noise at a ∆f off- I. INTRODUCTION set frequency. Nevertheless, the DC power consumption still The increasing demand in applications with limited power revolves around a few miliwatts which could be unsuitable budget - such as implantable medical devices - requires circuits for some rigorous applications. This paper presents a design designed for ultra-low-power consumption with reasonable implementation of an ultra-low-power oscillator at 2.4 GHz levels of signal integrity. Usually, these circuits have a radio- which is suitable for demands that requires a DC power frequency system at the front-end in order to provide com- consumption under 100 µW. The oscillator is based on the munication with the devices connected to a Wireless Body classical Hartley topology and a prototype was designed in a Area Network (WBAN) [1]. Oscillators are blocks that play standard 0.18 µm CMOS technology to verify the results. Post a key role in a radio communication system, since they have layout simulation outcomes indicate that the circuit oscilates to provide reference signals trading off high spectral purity at a frequency of 2.32 GHz reaching a DC power consumption and low power consumption. Thereby, in order to attend those of 88 µW from 1-V supply voltage and phase noise of -106.7 particular demands, these circuits must be designed to best at 1 MHz offset frequency, which results in a figure-of-merit match with the aforementioned trade-offs. (FoM) of 184.5 dBc/Hz. Even though the phase noise has Several former reports have discussed topologies and tech- not presented the best result, which contributes to degrade the niques to shrink both phase noise and power consumption in overall figure-of-merit, it is sufficient to comply with ZigBee order to enhance the overall oscillator performance. In [2], specifications that require at least a -88 dBc/Hz phase noise an approach that consists in the optimizing of capacitor ratio at a frequency offset of 1 MHz from the carrier [8]. is presented, which allows the circuit to work with supply The rest of this paper is organized as follows: in section II, voltages at only 20 mV. In [3], they employ a noise filter it is introduced a general circuit analysis; section III presents to reduce the phase noise of voltage controlled oscillators a design procedure focused on the passive network; section IV (VCOs) to its fundamental minimum according to the res- presents the circuit design; section V presents Monte Carlo and onator quality factor and power consumption. The oscillators corners simulations in order to best estimate the sensibility designed in [4] make use of a tail capacitance for filtering of the design; and finally, section VI summarizes the most the current source noise altogether with a DC level shift relevant contributions of this paper. that enables a large oscillation amplitude, while the core transistors operate in the saturation region. [5] presents a II. CIRCUIT ANALYSIS transformer-feedback VCO based on the concept of dual signal There are many different approaches to realize the circuit swings, allowing the output signals to swing above the supply analysis of an oscillator that can comprise negative resistance voltage and below the ground potential, which increases the analysis and positive feedback loop, for instance. Irrespective carrier power and decreases the phase noise. A similar idea of which analysis is chosen, all of them may converge for is shown in [6], in which they replace the tail current of a the simple Barkhausen criteria which dictates the required traditional differential Colpitts VCO by inductors to augment oscillation conditions for any feedback system. the maximum attainable amplitude. In [7], the author uses a Usually, the Hartley oscillator can be analysed by a general cross-coupled MOSFET pair with forward-body bias to boost three-point oscillator approach presented by Figures 1(a) and the negative conductance of a millimeter-wave differential 1(b). At this point of view, its small-signal equivalent circuit Colpitts oscillattor. can be represented as showed in Figure 2 - in a very first order VDD Goal: Minimize PDC L L 2 Cf 1 1 Maximize inductors R p Z1 Z3 Calculate necessary 3 g m Ibias AC_short Z2 2 Set proper ID and W to attend gm (a) (b) Check actual β( jω) Fig. 1. Schematic diagram of designed oscillators: (a): Classical topology modified due parasitics of Hartley oscillator; (b): Three-point oscillator equivalent circuit No A v( jω)β( jω)>1 Z3 + + + Yes vgs gmvgs rd vo Z2 Z1 vf − − − Suceed! ZL Fig. 3. Ultra-low-power oscillator design procedure flow chart Fig. 2. Small-signal equivalent circuit Where Leq represents the equivalent inductance composed L L C analisys. In this figure, rd represents the output resistance at by 1, 2 and mutual inductances and eq the equivalent C the drain, vf the feedback voltage and ZL the input impedance capacitance composed mainly by the feedback capacitor f C of the passive network composed by Z1, Z2 and Z3. For vf = of the passive network and the intrinsic capacitance gd. vgs, the direct and feedback gain can be expressed as: III. DESIGN PROCEDURE vo(j!) −gmrdZL Av(j!) = = (2) vgs(j!) ZL + rd As denoted in [7], it is necessary lower the equivalent par- v (j!) Z allel conductance of the passive network in order to reduce the β(j!) = f = 1 (3) vo(j!) Z1 + Z3 power consumption. By this point of view, it is interesting to design inductors with the larger equivalent parallel resistance. Hence, the loop gain is given by: Thus, the design procedure to be presented here has focused gmrdZLZ1 to maximize the equivalent parallel resistance Rp of inductors, Av(j!)β(j!) = − = (ZL + rd)(Z1 + Z3) in order to shrink the overall DC power. Since reaching large values for R is not a effortless task, it was chosen the same gmrdZ1Z2 p = − (4) inductor value for L1 and L2. Once the equivalent Rp of the rd(Z1 + Z2 + Z3) + Z2(Z1 + Z3) tank is set, a proper gm transconductance must be calculated in Assuming that impedances Z1, Z2 and Z3 are purely reactives order to cancel tank losses and start oscilations. A proper drain and the phase of loop gain must be zero to sustain oscillations current ID and a transistor width size W shall be set in order (i.e. X (! ) + X (! ) + X (! ) = 0) , it can be shown that 1 0 2 0 3 0 to attend the necessary gm through the following relationship, the loop gain can be expressed by: assuming saturation regime: gmrdX1(!0) gmrdX1(!0) p Av(j!0)β(j!0) = − = (5) 2IS( 1 + if − 1) X1(!0) + X3(!0) X2(!0) g = (9) m nφ The loop gain must be greater than 1 to start oscillations, thus: t Where i =∼ I =I is the inversion coefficient at the mosfet gmrdX1(!0) L1 f D S > 1 =) gmrd > (6) I X (! ) L source terminal and S is the specific current which is directly 2 0 2 proportional to the aspect ratio (W/L) and other technological In other words, a transistor must be designed with a transcon- parameters, n is the so-called slope factor and φt the thermal dutance that complies with the following requirement: voltage [9]. At this point, some recursive iterations may be L1 necessary since the mosfet might load in the node at L2 gm > (Gp + go) (7) L2 with the intrinsic capacitances Cgb and Cgs which can slighty modify the feedback gain β(j!). Once the modified feedback Where g represents the output conductance and G the overall o p gain β(j!) is checked and the product A (j! )β(j! ) is parallel loss of the passive network at the drain node. The v 0 0 greater than 1, an oscillation can be sustained and a target oscillation frequency can be expressed as: reached. Figure 3 summarizes the ultra-low-power oscillator p !0 = 1= LeqCeq (8) design through a simplified flowchart. VDD Bias Tee circuit was designed in Virtuoso Spectre Circuit Simulator VDD RFC from Cadence and sent to fabrication. Phase noise simulation DCblock was performed at 1 MHz offset frequency through the periodic L2 Cf L1 DCblock Spectrum steady state (PSS) analysis from Virtuoso Spectre Simulator. VDD Analyser M5 Table II and III shows the Monte Carlo and corner simulation I M1 bias VDD R results. Monte carlo simulation results were performed for M3 M2 Ibias2 100 samples and include the maximum, minimum, mean and standard deviation for the figure-of-merit (FoM), oscillation M 1:1 4 frequency (fo), DC power consumption (PDC ) and phase- noise at 1 MHz offset frequency.
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