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RISC-V Bitmanip Extension Document Version 0.90
RISC-V Bitmanip Extension Document Version 0.90 Editor: Clifford Wolf Symbiotic GmbH [email protected] June 10, 2019 Contributors to all versions of the spec in alphabetical order (please contact editors to suggest corrections): Jacob Bachmeyer, Allen Baum, Alex Bradbury, Steven Braeger, Rogier Brussee, Michael Clark, Ken Dockser, Paul Donahue, Dennis Ferguson, Fabian Giesen, John Hauser, Robert Henry, Bruce Hoult, Po-wei Huang, Rex McCrary, Lee Moore, Jiˇr´ıMoravec, Samuel Neves, Markus Oberhumer, Nils Pipenbrinck, Xue Saw, Tommy Thorn, Andrew Waterman, Thomas Wicki, and Clifford Wolf. This document is released under a Creative Commons Attribution 4.0 International License. Contents 1 Introduction 1 1.1 ISA Extension Proposal Design Criteria . .1 1.2 B Extension Adoption Strategy . .2 1.3 Next steps . .2 2 RISC-V Bitmanip Extension 3 2.1 Basic bit manipulation instructions . .4 2.1.1 Count Leading/Trailing Zeros (clz, ctz)....................4 2.1.2 Count Bits Set (pcnt)...............................5 2.1.3 Logic-with-negate (andn, orn, xnor).......................5 2.1.4 Pack two XLEN/2 words in one register (pack).................6 2.1.5 Min/max instructions (min, max, minu, maxu)................7 2.1.6 Single-bit instructions (sbset, sbclr, sbinv, sbext)............8 2.1.7 Shift Ones (Left/Right) (slo, sloi, sro, sroi)...............9 2.2 Bit permutation instructions . 10 2.2.1 Rotate (Left/Right) (rol, ror, rori)..................... 10 2.2.2 Generalized Reverse (grev, grevi)....................... 11 2.2.3 Generalized Shuffleshfl ( , unshfl, shfli, unshfli).............. 14 2.3 Bit Extract/Deposit (bext, bdep)............................ 22 2.4 Carry-less multiply (clmul, clmulh, clmulr).................... -
SPARC Enterprise Oracle VM Server for SPARC Important Information
SPARC Enterprise Oracle VM Server for SPARC Important Information C120-E618-06EN October 2012 Copyright © 2007, 2012, Oracle and/or its affiliates and FUJITSU LIMITED. All rights reserved. Oracle and/or its affiliates and Fujitsu Limited each own or control intellectual property rights relating to products and technology described in this document, and such products, technology and this document are protected by copyright laws, patents, and other intellectual property laws and international treaties. This document and the product and technology to which it pertains are distributed under licenses restricting their use, copying, distribution, and decompilation. No part of such product or technology, or of this document, may be reproduced in any form by any means without prior written authorization of Oracle and/or its affiliates and Fujitsu Limited, and their applicable licensors, if any. The furnishings of this document to you does not give you any rights or licenses, express or implied, with respect to the product or technology to which it pertains, and this document does not contain or represent any commitment of any kind on the part of Oracle or Fujitsu Limited, or any affiliate of either of them. This document and the product and technology described in this document may incorporate third-party intellectual property copyrighted by and/or licensed from the suppliers to Oracle and/or its affiliates and Fujitsu Limited, including software and font technology. Per the terms of the GPL or LGPL, a copy of the source code governed by the GPL or LGPL, as applicable, is available upon request by the End User. -
Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server Architecture Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server Architecture
An Oracle White Paper February 2014 Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server Architecture Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server Architecture Introduction ....................................................................................... 1 Comparison of SPARC T5–Based Server Features........................... 2 SPARC T5 Processor ........................................................................ 3 Taking Oracle’s Multicore/Multithreaded Design to the Next Level 5 SPARC T5 Processor Architecture ................................................ 6 SPARC T5 Processor Cache Architecture ..................................... 8 SPARC T5 Core Architecture ........................................................ 9 Oracle Solaris for Multicore Scalability............................................. 16 Oracle Solaris 11 Operating System ................................................ 18 Oracle Solaris Predictive Self Healing, Fault Management Architecture, and Service Management Facility ....................................................... 19 Oracle Solaris Cryptographic Frameworks................................... 19 End-to-End Virtualization Technology .............................................. 19 A Multithreaded Hypervisor ......................................................... 20 Oracle VM Server for SPARC ...................................................... 20 Oracle Solaris Zones ................................................................... 21 Enterprise-Class -
Exploiting Simple Analytical Models for Modeling Hardware Accelerators
Exploiting Simple Analytical Models for Modeling Hardware Accelerators by Muhammad Shoaib Bin Altaf A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Electrical & Computer Engineering) at the UNIVERSITY OF WISCONSIN–MADISON 2016 Date of final oral examination: 12/08/2016 The dissertation is approved by the following members of the Final Oral Committee: Mark Hill, Professor, Computer Science Mikko Lipasti, Professor, Electrical & Computer Engineering Karthikeyan Sankaralingam, Associate Professor, Computer Science Michael Swift, Associate Professor, Computer Science David Wood, Professor, Computer Science © Copyright by Muhammad Shoaib Bin Altaf 2016 All Rights Reserved i To my parents Tehseen Kausar and Sheikh Altaf Hussain, and my wife Iram Majeed for their love and support. ii acknowledgments I consider myself fortunate enough to work under the guidance of my advisor, David Wood. I would not have completed my thesis without his support. Working with David, can be a challenge in the beginning and you take time in getting settled with his unique style of mentoring. He gave me the freedom to choose a problem of my own choice but made sure that I stayed on the right path. He has a knack for communicating ideas succinctly, and expects (and forces) his students to develop the same. Thanks to David, I consider myself a better writer and researcher. Thanks David. I am also thankful to my committee members for providing useful feedback and com- ments on my work. Mark Hill encouraged and showed excitement about the modeling framework right form the beginning. His advice on making slides has helped me become a better presenter. -
Oracle VM Server for SPARC 2.1 Release Notes
Oracle®VM Server for SPARC 2.1 Release Notes Part No: 821–2856–12 February 2012 Copyright © 2007, 2012, Oracle and/or its affiliates. All rights reserved. This software and related documentation are provided under a license agreement containing restrictions on use and disclosure and are protected by intellectual property laws. Except as expressly permitted in your license agreement or allowed by law, you may not use, copy, reproduce, translate, broadcast, modify, license, transmit, distribute, exhibit, perform, publish or display any part, in any form, or by any means. Reverse engineering, disassembly, or decompilation of this software, unless required by law for interoperability, is prohibited. The information contained herein is subject to change without notice and is not warranted to be error-free. If you find any errors, please report them to us in writing. If this is software or related documentation that is delivered to the U.S. Government or anyone licensing it on behalf of the U.S. Government, the following notice is applicable: U.S. GOVERNMENT RIGHTS. Programs, software, databases, and related documentation and technical data delivered to U.S. Government customers are "commercial computer software" or "commercial technical data" pursuant to the applicable Federal Acquisition Regulation and agency-specific supplemental regulations. As such, the use, duplication, disclosure, modification, and adaptation shall be subject to the restrictions and license terms setforth in the applicable Government contract, and, to the extent applicable by the terms of the Government contract, the additional rights set forth in FAR 52.227-19, Commercial Computer Software License (December 2007). Oracle America, Inc., 500 Oracle Parkway, Redwood City, CA 94065. -
Table of Contents
1 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. Safe Harbor Statement The following is intended to outline our general product direction. It is intended for information purposes only, and may not be incorporated into any contract. It is not a commitment to deliver any material, code, or functionality, and should not be relied upon in making purchasing decisions. The development, release, and timing of any features or functionality described for Oracle’s products remains at the sole discretion of Oracle. 2 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. Eine phatastische Reise ins Innere der Hardware Franz Haberhauer Stefan Hinker Oracle Hardware in 3D 5 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. T5 and M5 PCIe Carrier Card . Supports standard low-profile PCIe cards Air Flow PCIe Retimer x16 Connector (x8 electrical) 6 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. PCIe Data Paths: Full System . Two root complexes per T5 processor . Each PCIe port on a T5 processor controls a single PCIe slot 7 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. T5-2 Block Diagram DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB T5-0 T5-1 CPU CPU TPM Host & CPU PCIe Debug CPU PCIe Debug Data Flash DC/DCs 0 1 Port DC/DCs 0 1 Port x8 x8 FPGA x8 x4 x8 x1 HDD0 DBG SAS/SATA x1 HDD0 IO Controller x4 x4 PCIe PCIe SP Module HDD0 get rid of all inside x8 x8 SAS/SATA smallSwitch boxes 0 Switch 1 FRUID HDD0 IO Controller Sideband Mgmt DRAM HDD0 USB 1.1 Keyboard Mouse Service SPI x8 USB 3.0 x8 USB 2.0 Storage Flash HDD0 Host Processor SATA DVD NAND USB 2.0 Hub USB USB 3.0 USB Internal USB Hub VGA VGA REAR IO Board USB2 USB3 VGA USB0 USB1 VGA Serial Enet Quad 10Gig Enet DB15 Mgmt Mgmt Slot 2 (8) 2 Slot (8) 3 Slot (8) 4 Slot (8) 5 Slot (8) 6 Slot (8) 7 Slot (8) 8 Slot Slot 1 (8) 1 Slot 10/100 FAN BOARD REAR IO 8 Copyright © 2013, Oracle and/or its affiliates. -
Computer Architectures an Overview
Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements. -
Oracle Hardware ECCN Matrix Last Updated: May 21, 2019
Oracle Hardware ECCN Matrix Last Updated: May 21, 2019 This information is provided for guidance only. Oracle Corporation ("Oracle") makes the trade information available for informational purposes only. It may not reflect the most current legal developments. The information is provided "AS IS," and Oracle does not represent, warrant or guarantee that the information is complete, accurate, or up-to- date. This document is subject to change without notice. The information is not intended to constitute legal advice or to be used as a substitute for specific legal advice from a licensed attorney. You should not act (or refrain from acting) based on information provided without obtaining professional advice regarding your particular facts and circumstances. Any use of the information by you is without recourse to Oracle and is at your own risk. IN NO EVENT SHALL ORACLE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES INCURRED BY YOU OR ANY THIRD PARTY, WHETHER IN AN ACTION IN CONTRACT OR TORT, ARISING FROM YOUR USE OF THE INFORMATION If you cannot find an ECCN for an Oracle product, please contact [email protected]. Oracle Cloud at Customer Hardware . Oracle Exadata Database Machine . Oracle Exadata Storage Expansion Rack . Oracle Exalogic Elastic Cloud . Oracle Private Cloud Appliance . Oracle Big Data Appliance . Oracle Zero Data Loss Recovery Appliance . Oracle Database Appliance . Oracle SuperCluster . Oracle MiniCluster . Oracle Exalytics In-Memory Machine . Oracle x86 Servers . SPARC Servers . -
Computer Architecture
Computer Architecture Adrian Crăciun January 9, 2018 1 Contents 1 Computer Architecture - Overview and Motivation 6 1.1 The Structured Organization of Computers . 6 1.2 Milestones in Computer Architecture . 14 1.3 The Computer Zoo . 21 1.4 Computer Families . 26 2 Computer Systems Organization 30 2.1 Processors . 31 2.2 Primary Memory / Secondary Memory / Input/Output (Old Slides) 40 3 The Digital Logic Level 73 3.1 Gates and Boolean Algebra . 73 3.2 Basic Digital Logic Circuits . 80 3.3 Memory . 88 3.4 CPU Chips and Buses . 96 3.5 Example CPUs . 102 4 The Microarchitecture Level 109 4.1 An Example Microarchitecture . 109 4.2 An Example ISA: IJVM . 116 4.3 Implementation of the Instruction Set . 122 4.4 Designing the Microarchitecture Level . 127 4.5 Improving Performance . 135 4.6 Example Microarchitectures . 141 5 The Instruction Set Architecture Level 144 5.1 Overview of the Instruction Set Architecture Level . 144 5.2 Memory models . 146 5.3 Registers . 147 5.4 Data Types . 150 5.5 Instruction Formats . 152 5.6 Addressing . 155 5.7 Instruction types . 158 5.8 Flow of control . 162 5.9 Example ISAs . 166 5.10 Comparison of the Instruction Sets . 167 6 The Operating System Machine Level 170 6.1 Virtual Memory . 170 6.2 Virtual I/O Instructions . 172 6.3 Virtual Instructions for Parallel Processes . 173 6.4 Example Operating Systems . 175 7 The Assembly Language Level 177 2 List of Figures 1 Moving between language levels. 7 2 A multilevel machine. 9 3 A multilevel machine with 6 levels. -
Oracle VM Server for SPARC 2.0 Release Notes
Oracle®VM Server for SPARC 2.0 Release Notes Part No: 821–1487–12 February 2011 Copyright © 2007, 2011, Oracle and/or its affiliates. All rights reserved. This software and related documentation are provided under a license agreement containing restrictions on use and disclosure and are protected by intellectual property laws. Except as expressly permitted in your license agreement or allowed by law, you may not use, copy, reproduce, translate, broadcast, modify, license, transmit, distribute, exhibit, perform, publish, or display any part, in any form, or by any means. Reverse engineering, disassembly, or decompilation of this software, unless required by law for interoperability, is prohibited. The information contained herein is subject to change without notice and is not warranted to be error-free. If you find any errors, please report them to us in writing. If this is software or related software documentation that is delivered to the U.S. Government or anyone licensing it on behalf of the U.S. Government, the following notice is applicable: U.S. GOVERNMENT RIGHTS Programs, software, databases, and related documentation and technical data delivered to U.S. Government customers are “commercial computer software” or “commercial technical data” pursuant to the applicable Federal Acquisition Regulation and agency-specific supplemental regulations. As such, the use, duplication, disclosure, modification, and adaptation shall be subject to the restrictions and license terms setforth in the applicable Government contract, and, to the extent applicable by the terms of the Government contract, the additional rights set forth in FAR 52.227-19, Commercial Computer Software License (December 2007). Oracle America, Inc., 500 Oracle Parkway, Redwood City, CA 94065. -
Netra SPARC T4-2 Server Data Sheet
ORACLE DATA SHEET NETRA SPARC T4-2 Designed to meet the EXTREME SCALABILITY AND most demanding DENSITY WITH CARRIER-GRADE telecommunication AVAILABILITY applications, like KEY FEATURES NEBS Level 3 certification and OSS/BSS workloads, ETSI compliance the Netra SPARC T4-2 SPARC T4 processor is the server is the right industry’s first processor designed choice for consolidating your telecommunication datacenter applications. As for application network infrastructure the highest-density Netra SPARC T4 server available in a rack mount form workloads factor, the Netra SPARC T4-2 delivers massive throughput, scalability, security, Redundant hot-swappable AC or and built-in no-cost virtualization DC power supplies and hot- pluggable disk drives Massive I/O performance and Product Overview expandability The Netra SPARC T4-2 will help maximize the ROI and create new enhancement to complex KEY BENEFITS datacenters. The re-emergence of the telecom industry provides a number of opportunities for Reliable operation in severe environmental conditions growth on a foundation of open-standards-based technology. Built in no-cost virtualization The multi-socket Netra SPARC T4-2 is designed to support a multi-core, multithreaded server technology with Oracle VM Server on a chip design that increase reliability and performance as it minimizes cost, power demand for SPARC and Oracle Solaris Zone and components required- reducing overall operating costs. Integrated on-chip cryptographic acceleration offers security for The SPARC T4 processor delivers five times single-threaded performance improvement over telecommunications data centers the previous generation SPARC T3 processor, making the Netra SPARC T4-2 ideal for broad Onboard 10 Gigabit Ethernet (GbE) range of telecommunication network infrastructure workloads. -
SPARC Enterprise Oracle VM Server for SPARC Guide
SPARC Enterprise Oracle VM Server for SPARC Guide C120-E534-13EN February 2012 Copyright © 2007, 2012, Oracle and/or its affiliates and FUJITSU LIMITED. All rights reserved. Oracle and/or its affiliates and Fujitsu Limited each own or control intellectual property rights relating to products and technology described in this document, and such products, technology and this document are protected by copyright laws, patents, and other intellectual property laws and international treaties. This document and the product and technology to which it pertains are distributed under licenses restricting their use, copying, distribution, and decompilation. No part of such product or technology, or of this document, may be reproduced in any form by any means without prior written authorization of Oracle and/or its affiliates and Fujitsu Limited, and their applicable licensors, if any. The furnishings of this document to you does not give you any rights or licenses, express or implied, with respect to the product or technology to which it pertains, and this document does not contain or represent any commitment of any kind on the part of Oracle or Fujitsu Limited, or any affiliate of either of them. This document and the product and technology described in this document may incorporate third-party intellectual property copyrighted by and/or licensed from the suppliers to Oracle and/or its affiliates and Fujitsu Limited, including software and font technology. Per the terms of the GPL or LGPL, a copy of the source code governed by the GPL or LGPL, as applicable, is available upon request by the End User. Please contact Oracle and/or its affiliates or Fujitsu Limited.