Tema III – Microcontrollers and Microprocessors
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1 Tema III – Microcontrollers and Microprocessors Roberto Gutiérrez Mazón 2 ¨ Introduction ¨ Processor Architectural Features. Datapath & pipeline. ¨ Data Representation: Fixed-point vs Floating-point ¨ Interrupts, Exceptions, Watch-Dog, … ¨ 32-bit microcontroller. ARM Cortex-M3 ¤ ARM Cortex-M3 Architecture. Programmers Model. ¨ 32/64bit microprocessor. ¤ Intel x86, UltraSparc Architecture. Programmers Model Processor Architectural Features 3 What is “Computer Architecture”?? Applications Operating System Compiler Firmware Instruction Set Architecture Instr. Set Proc. I/O system Datapath & Control Digital Design Circuit Design Layout & fab Semiconductor Materials Introduction 4 ¨ Moore`s Law ¨ “Cramming More Components onto Integrated Circuits” ¤ Gordon Moore, Electronics, 1965 ¨ Nº on transistors on cost-effective integrated circuit double every 18 months Introduction 5 ¨ Prehistoric Computer Architecture: ¤ The Z1 was the first mechanical freely programmable computer in the world which used Boolean logic and binary floating point numbers ¤ Memory: 64 words of 22bits. ¤ Clock Frequency: 1Hz ¤ Registers: two 22bits floating-point registers. ¤ ALU: add (5 seg), sub, mult. (16 seg) ,div (18seg). ¤ Weight: 1000 kg Introduction 6 ¨ The zEC12 Zseries IBM Microprocessor: ¤ 5.5 GHz in IBM 32nm PD-SOI CMOS technology ¤ 2.75 billion transistors in 597 mm2 ¤ 64-bit virtual addressing n original S/360 was 24-bit, and S/370 was 31-bit extension ¤ Six-core design ¤ Three-issue out-of-order superscalar pipeline ¤ Out-of-order memory accesses ¤ Redundant datapaths n every instruction performed in two parallel datapaths and results compared ¤ 64KB L1 I-cache, 128KB L1 D-cache on-chip ¤ 1MB private L2 unified instruction and data cache per core, on-chip ¤ On-Chip 48MB eDRAM L3 cache ¤ Scales to 120-core multiprocessor with 384MB of shared L4 eDRAM Introduction 7 IC 4004 Intel (1971) IC 486DX2 Intel (1989) 1er Transistor (Shokley, ENIAC(1946) Bardeen,Brattain) (1947) Maquina Diferencias Baggage (1832) Nanotecnología (¿?) Intel Quad (2007) Procesadores opticos (¿?) Cell (2005) MEMS(2000) Introduction 8 Battery Solar Cells Wireless Sensor Network Sensors, timers Cortex-M0 +16KB RAM 65nm UWB Radio antenna 10 kB Storage memory ~3fW/bit 12µAh Li-ion Battery A B C Processor, SRAM and PMU Wirelessly networked into large scale sensor arrays University of Michigan Cortex-M0; 65¢ Introduction 9 4200 ARM powered Neutrino Detectors 70 bore holes 2.5km deep 1km 60 detectors per string 2.5km starting 1.5km down 1km3 of active telescope Work supported by the National Science Foundation and University of Wisconsin-Madison Introduction 10 11 ¨ Introduction ¨ Processor Architectural Features. Datapath & pipeline. ¨ Data Representation: Fixed-point vs Floating-point ¨ Interrupts, Exceptions, Watch-Dog, … ¨ 32-bit microcontroller. ARM Cortex-M3 ¤ ARM Cortex-M3 Architecture. Programmers Model. ¨ 32/64bit microprocessor. ¤ Intel x86, UltraSparc Architecture. Programmers Model Processor Architectural Features 12 Programming Model ¨ Microprocessors can be High-Level Language Level 5 programmed directly using an assembly language. Assembly Language Level 4 ¨ Differences with high-level languages: Operating System ¤ Use commands to execute data Level 3 movements, arithmetic, logic and program control operations. Instruction Set ¤ Use registers to hold data for Architecture Level 2 operation. ¨ Programmers need to know not Microarchitecture Level 1 only the assembly language for the microprocessor, but also the internal configuration of the Digital Logic Level 0 microprocessor. Processor Architectural Features 13 A Basic Processor Processor ¨ The basic components: core ¤ Processor with its associate temporary memory (registers and cache if available) for code execution Cache/SRAM Registers Registers memory ¤ Main memory and secondary memory where code and data are temporary and permanently stored Main ¤ Input and output modules that provide memory interface between the processor and the I/O user Interface Storage ¨ Connected through an interface bus consists of memory ¤ Address, Data, and Control signals. Address bus, data e.g. AMBA bus for the ARM-based bus, and bus processor control signals Processor Architectural Features 14 The gap widens between DRAM, disk, and CPU speeds. 100,000,000 10,000,000 1,000,000 100,000 Disk seek time DRAM access time ns 10,000 SRAM access time 1,000 CPU cycle time 100 10 1 1980 1985 1990 1995 2000 ye ar register cache memory disk Access time 1 1-10 50-100 20,000,000 (cycles) Processor Architectural Features 15 Memory Hierarchy ¨ A typical processor is supported by: L0: registers ¤ on-board main memory (e.g. SDRAM up to GB) Smaller, faster, and more expensive (per L1: on-chip L1 ¤ on-chip or on-die cache memory (e.g. SRAM byte) storage devices cache (SRAM) KB to MB) off-chip L2 ¤ L2: on-die registers cache (SRAM) ¨ Some processors also provide general purpose on-chip L3: main memory (DRAM) ¤ SRAM (e.g. embedded processor) which may be configured as SRAM/Cache combination (e.g. Larger, slower, and TI’s DSP) cheaper (per byte) storage devices L4: local secondary storage (virtual memory) (local disks) ¨ Typically, a processor also utilizes secondary non-volatile memory ¤ For permanent code and data storage like Flash- L5: remote secondary storage based memory and hard disk (tapes, distributed file systems, Web servers) Processor Architectural Features 16 ¨ Multiple machine cycles are required when reading from memory, because it responds much more slowly than the CPU (e.g.33 MHz). The wasted clock cycles are called wait states. L1 Data 1 cycle latency Regs. 16 KB L2 Unified 4-way assoc 128KB--2 MB Main Write-through 4-way assoc 32B lines Write-back Memory Write allocate Up to 4GB L1 Instruction 32B lines 16 KB, 4-way 32B lines Processor Chip Pentium III cache hierarchy Processor Architectural Features 17 Address Space ¨ Address space of a processor depends on its address decoding mechanism. ¤ Size will depend on the number of address bit used. ¨ Depending on the processor design, there may be two types of address space: ¤ One is used by normal memory access. ¤ Another one is reserved for I/O peripheral registers (control, status, and data). ¤ Need extra control signal or special means of accessing the alternate address space. Processor Architectural Features 18 Address Space ¨ Refer to the range of address that can be accessed by the processor determined by the number of address bit utilized in the processor architecture. ¨ Some processor families (e.g. ARM) utilize only one address space for both memory and I/O devices ¤ i.e. everything is mapped in the same address space 0xFFFFFFFF I/O Reg I/O I/O Reg Processor Data Memory Code 0x00000000 Processor Architectural Features 19 Memory mapped vs I/O mapped ¨ Some processor families have two address spaces. ¨ E.g., for the x86 processor, memory and I/O devices can be mapped in two different address spaces: ¤ Memory address space and I/O address space 0xFFFF 0xFFFFFFFF Data I/O Reg Code Processor I/O Reg Data 0x0000 Code 0x00000000 I/O Address Memory Address Space Space Processor Architectural Features 20 Memory system Architectures ¨ Two types of information are found in a typical program code: ¤ Instruction codes for execution ¤ Data that is used by the instruction codes ¨ Two classes of memory system design to store these information: ¤ Von Neumann architecture ¤ Harvard architecture FFFFh FFFFh Separate bus for Code Data Data & Data Table Von Neumann Data Data Data 8000h Processor Code Processor 7FFFh Code Single path (bus) for both Data Code & Data Code Code Code 0000h Harvard 0000h Processor Architectural Features 21 Processor Size ¨ The processor size is described in terms of ‘bits’ (e.g. an 8 bit, 32-bit processor). ¤ Corresponds to the data size that can be manipulated at a time by the processor. ¤ Typically reflected in the size of the processor (internal) data path and register bank. ¨ Hence an 8-bit processor can only manipulate byte size data at a time, while a 32-bit processor can handle 32-bit double word size data at a time. • Even though the data content may only be of single byte size. Processor Architectural Features 22 Registers program counter ¨ The most fundamental storage area instruction queue in the processor is closely located to PC the processor provides very fast program I-1 I-2 I-3 I-4 access, operating at the processor fetch clock but is of limited amount (less memory op1 read than 100 typical) op2 registers registers ¨ Most are of the general purpose type instruction and can store any type of I-1 register information: decode ¤ data – e.g. timer value, constants ¤ address – e.g. ASCII table, stack write write ¨ Some are reserved for specific flags ALU purpose execute ¤ program counter (IP). (output) ¤ program status register (SR). Processor Architectural Features 23 Data Organization in Memory ¨ A typical memory contains a storage location that can store data of a certain fixed size (most commonly of the 8-bit (byte) size). Each location is provided with a unique address. ¨ Depending on the data path size of the processor. The memory content is accessible in the size of an 8-bit byte, a 16-bit half word, a 32-bit word, and even a 64-bit double word. ¨ A 32-bit data consists of four bytes of data, and are stored in four successive memory locations. Data and code must be aligned to the respective address size boundary. ¤ E.g. for a 32-bit system, align to the word boundary, with the lowest two address bits equal to zero ¨ But what is the order of the four bytes of data?. Depends on the Endianness adopted Processor Architectural Features 24 Data Endianness ¨ In the Little Endian format, the least significant byte (LSB) is stored in the lowest address of the memory, with the most significant byte (MSB) stored in the highest address location of the memory. ¨ In the Big Endian format, the least significant byte (LSB) is stored in the highest address of the memory, with the most significant byte (MSB) stored in the lowest address location of the memory.