Exploiting Simple Analytical Models for Modeling Hardware Accelerators
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Installation and Upgrade General Checklist Report
VeritasTM Services and Operations Readiness Tools Installation and Upgrade Checklist Report for Storage Foundation for Sybase 5.1, Solaris 10, SPARC Index Back to top Important Notes System requirements Product documentation Patches for Storage Foundation for Sybase and Platform Platform configuration Host bus adapter (HBA) parameters and switch parameters Operations Manager Array Support Libraries (ASLs) Additional tasks to consider Important Notes Back to top Array Support Libraries (ASLs) When installing Veritas products, please be aware that ASLs updates are not included in the patches update bundle. Please go to the Array Support Libraries (ASLs) to get the latest updates for your disk arrays. System requirements Back to top Required number of CPUs: 1 Required disk space: Partitions Minimum space required Maximum space required Recommended space /opt 102 MB 441 MB 327 MB /root 52 MB 53 MB 52 MB /usr 154 MB 154 MB 154 MB /var 1 MB 1 MB 1 MB Supported architectures: SPARC M5 series [1][2] SPARC M6 series [1][2] SPARC T3 series [2] SPARC T4 series [2][3] SPARC T5 series [2][4] SPARC64 X+ series SPARC64-V series SPARC64-VI series 1 of 9 VeritasTM Services and Operations Readiness Tools SPARC64-VII/VII+ series SPARC64-X series UltraSPARC II series UltraSPARC III series UltraSPARC IV series UltraSPARC T1 series [2] UltraSPARC T2/T2+ series [2] 1. A minimum version of Storage Foundation 5.1SP1RP3, and Solaris 10 1/13 are required for support. 2. Oracle VM Server for SPARC supported. See the following TechNote: http://www.veritas.com/docs/DOC4397. 3. Installation of Storage Foundation products may encounter issue on Oracle T4 servers, see TechNote http://www.veritas.com/docs/TECH177307. -
SPARC S7 Servers
Oracle’s SPARC S7 Servers Technical Overview Rainer Schott Oracle Systems Sales Consulting September 2016 Copyright © 2016, Oracle and/or its affiliates. All rights reserved. | Safe Harbor Statement The following is intended to outline our general product direction. It is intended for information purposes only, and may not be incorporated into any contract. It is not a commitment to deliver any material, code, or functionality, and should not be relied upon in making purchasing decisions. The development, release, and timing of any features or functionality described for Oracle’s products remains at the sole discretion of Oracle. Copyright © 2016, Oracle and/or its affiliates. All rights reserved. | 3 • App Data Integrity SPARC @ Oracle Including • DB Query Acceleration Software in Silicon } • Inline Decompression 7 Processors in 6 Years • More…. 2010 2011 2013 2013 2013 2015 2016 SPARC T3 SPARC T4 SPARC T5 SPARC M5 SPARC M6 SPARC M7 SPARC S7 16 x 2nd Gen cores 8 x 3rd Gen Cores 16 x 3rd Gen Cores 16x 3 rd Gen Cores 12 x 3rd Gen Cores 32 x 4th Gen Cores 8 x 4th Gen Cores 4MB L3 Cache 4MB L3 Cache 8MB L3 Cache 48MB L3 Cache 48MB L3 Cache 64MB L3 Cache 16MB L3 cache 1.65 GHz 3.0 GHz 3.6 GHz 3.6 GHz 3.6 GHz 4.1 GHz 4.5 GHz Copyright © 2016, Oracle and/or its affiliates. All rights reserved. | Oracle Confidential Advancing the State-of-the-Art M7 Microprocessor – World’s First Implementation of Software Features in Silicon • SQL in Silicon – High-Speed Memory Decompression… – Accelerates In-Memory Database • Always-On Security in Silicon – Memory intrusion detection • High-Speed Encryption – Near zero performance impact Copyright © 2016, Oracle and/or its affiliates. -
Datasheet Fujitsu Sparc Enterprise T5440 Server
DATASHEET FUJITSU SPARC ENTERPRISE T5440 SERVER DATASHEET FUJITSU SPARC ENTERPRISE T5440 SERVER THE SYSTEM THAT MOVES WEB APPLICATION CONSOLIDATION INTO MID-RANGE COMPUTING. UP TO 4 HIGH PERFORMANCE PROCESSORS, HIGH MEMORY AND EXTENSIVE CONNECTIVITY PROVIDE THE INFRASTRUCTURE FOR BACK OFFICE AND DATA CENTER CONSOLIDATION TASKS. FUJITSU SPARC ENTERPRISE FOR WEB SECURITY, SPARC ENVIRONMENTS MEAN MANAGEABILITY AND EFFICIENCY AND PERFORMANCE RELIABILITY Fujitsu SPARC Enterprise throughput computing Based on a four socket design, Fujitsu SPARC servers are the ultimate in Web and front-end Enterprise T5440 provides up to 256 threads and business processes. Designed for space efficiency, 512GB of memory for outstanding workload low power consumption, and maximum compute consolidation. These servers can deliver outstanding performance they provide high throughput, data throughput performance in web and network energy-saving, and space-saving solutions, in Web environments while also delivering excellent server server deployment. Built on UltraSPARC T2 or consolidation capability for back office and UltraSPARC T2 Plus processors, everything is departmental database solutions. Fully supported by integrated together on each processor chip to reduce solid management and the top scalability and the overall component count. This speeds openness of the Solaris Operating system, you have performance lowers power use and reduces the ability to maximise thread utilization, deliver component failure. Add in the no-cost virtualization application capability, and scale as large as you technology from Logical Domains and Solaris need. Containers and you have a fully scalable environment for server consolidation. Finish it off with on-chip The intrinsic service management in Fujitsu SPARC encryption and 10 Giga-bit Ethernet freeways and Enterprise T5440 combined with the SPARC they provide the compete environment for secure hardware architecture and Solaris operating system data processing and lightening fast throughput. -
Oracle® Developer Studio 12.6
® Oracle Developer Studio 12.6: C++ User's Guide Part No: E77789 July 2017 Oracle Developer Studio 12.6: C++ User's Guide Part No: E77789 Copyright © 2017, Oracle and/or its affiliates. All rights reserved. This software and related documentation are provided under a license agreement containing restrictions on use and disclosure and are protected by intellectual property laws. Except as expressly permitted in your license agreement or allowed by law, you may not use, copy, reproduce, translate, broadcast, modify, license, transmit, distribute, exhibit, perform, publish, or display any part, in any form, or by any means. Reverse engineering, disassembly, or decompilation of this software, unless required by law for interoperability, is prohibited. The information contained herein is subject to change without notice and is not warranted to be error-free. If you find any errors, please report them to us in writing. If this is software or related documentation that is delivered to the U.S. Government or anyone licensing it on behalf of the U.S. Government, then the following notice is applicable: U.S. GOVERNMENT END USERS: Oracle programs, including any operating system, integrated software, any programs installed on the hardware, and/or documentation, delivered to U.S. Government end users are "commercial computer software" pursuant to the applicable Federal Acquisition Regulation and agency-specific supplemental regulations. As such, use, duplication, disclosure, modification, and adaptation of the programs, including any operating system, integrated software, any programs installed on the hardware, and/or documentation, shall be subject to license terms and license restrictions applicable to the programs. -
How the SPARC T4 Processor Optimizes Throughput Capacity: a Case Study
An Oracle Technical White Paper April 2012 How the SPARC T4 Processor Optimizes Throughput Capacity: A Case Study How the SPARCT4 Processor Optimizes Throughput Capacity: A Case Study Introduction ....................................................................................... 1 Summary of the Performance Results ............................................... 4 Performance Characteristics of the CSP1 and CSP2 Programs ........ 5 The UltraSPARC T2+ Pipeline Architecture ................................... 5 Instruction Scheduling Analysis for the CSP1 Program on the UltraSPARC T2+ Processor .......................................................... 6 Instruction Scheduling Analysis for the CSP2 Program on the UltraSPARC T2+ Processor .......................................................... 9 UltraSPARC T2+ Performance Results ........................................... 10 Test Framework........................................................................... 10 UltraSPARC T2+ Performance Results for the CSP1 Program .... 11 UltraSPARC T2+ Performance Results for the CSP2 Program .... 12 SPARC T4 Performance Results ..................................................... 13 Summary of the SPARC T4 Core Architecture ............................ 13 Test Framework........................................................................... 15 Cycle Count Estimates and Performance Results for the CSP1 Program on the SPARC T4 Processor ......................................... 15 Cycle Count Estimates and Performance Results for the -
RISC-V Bitmanip Extension Document Version 0.90
RISC-V Bitmanip Extension Document Version 0.90 Editor: Clifford Wolf Symbiotic GmbH [email protected] June 10, 2019 Contributors to all versions of the spec in alphabetical order (please contact editors to suggest corrections): Jacob Bachmeyer, Allen Baum, Alex Bradbury, Steven Braeger, Rogier Brussee, Michael Clark, Ken Dockser, Paul Donahue, Dennis Ferguson, Fabian Giesen, John Hauser, Robert Henry, Bruce Hoult, Po-wei Huang, Rex McCrary, Lee Moore, Jiˇr´ıMoravec, Samuel Neves, Markus Oberhumer, Nils Pipenbrinck, Xue Saw, Tommy Thorn, Andrew Waterman, Thomas Wicki, and Clifford Wolf. This document is released under a Creative Commons Attribution 4.0 International License. Contents 1 Introduction 1 1.1 ISA Extension Proposal Design Criteria . .1 1.2 B Extension Adoption Strategy . .2 1.3 Next steps . .2 2 RISC-V Bitmanip Extension 3 2.1 Basic bit manipulation instructions . .4 2.1.1 Count Leading/Trailing Zeros (clz, ctz)....................4 2.1.2 Count Bits Set (pcnt)...............................5 2.1.3 Logic-with-negate (andn, orn, xnor).......................5 2.1.4 Pack two XLEN/2 words in one register (pack).................6 2.1.5 Min/max instructions (min, max, minu, maxu)................7 2.1.6 Single-bit instructions (sbset, sbclr, sbinv, sbext)............8 2.1.7 Shift Ones (Left/Right) (slo, sloi, sro, sroi)...............9 2.2 Bit permutation instructions . 10 2.2.1 Rotate (Left/Right) (rol, ror, rori)..................... 10 2.2.2 Generalized Reverse (grev, grevi)....................... 11 2.2.3 Generalized Shuffleshfl ( , unshfl, shfli, unshfli).............. 14 2.3 Bit Extract/Deposit (bext, bdep)............................ 22 2.4 Carry-less multiply (clmul, clmulh, clmulr).................... -
Sun SPARC Enterprise T5440 Servers
Sun SPARC Enterprise® T5440 Server Just the Facts SunWIN token 526118 December 16, 2009 Version 2.3 Distribution restricted to Sun Internal and Authorized Partners Only. Not for distribution otherwise, in whole or in part T5440 Server Just the Facts Dec. 16, 2009 Sun Internal and Authorized Partner Use Only Page 1 of 133 Copyrights ©2008, 2009 Sun Microsystems, Inc. All Rights Reserved. Sun, Sun Microsystems, the Sun logo, Sun Fire, Sun SPARC Enterprise, Solaris, Java, J2EE, Sun Java, SunSpectrum, iForce, VIS, SunVTS, Sun N1, CoolThreads, Sun StorEdge, Sun Enterprise, Netra, SunSpectrum Platinum, SunSpectrum Gold, SunSpectrum Silver, and SunSpectrum Bronze are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. T5440 Server Just the Facts Dec. 16, 2009 Sun Internal and Authorized Partner Use Only Page 2 of 133 Revision History Version Date Comments 1.0 Oct. 13, 2008 - Initial version 1.1 Oct. 16, 2008 - Enhanced I/O Expansion Module section - Notes on release tabs of XSR-1242/XSR-1242E rack - Updated IBM 560 and HP DL580 G5 competitive information - Updates to external storage products 1.2 Nov. 18, 2008 - Number -
SPARC Enterprise Oracle VM Server for SPARC Important Information
SPARC Enterprise Oracle VM Server for SPARC Important Information C120-E618-06EN October 2012 Copyright © 2007, 2012, Oracle and/or its affiliates and FUJITSU LIMITED. All rights reserved. Oracle and/or its affiliates and Fujitsu Limited each own or control intellectual property rights relating to products and technology described in this document, and such products, technology and this document are protected by copyright laws, patents, and other intellectual property laws and international treaties. This document and the product and technology to which it pertains are distributed under licenses restricting their use, copying, distribution, and decompilation. No part of such product or technology, or of this document, may be reproduced in any form by any means without prior written authorization of Oracle and/or its affiliates and Fujitsu Limited, and their applicable licensors, if any. The furnishings of this document to you does not give you any rights or licenses, express or implied, with respect to the product or technology to which it pertains, and this document does not contain or represent any commitment of any kind on the part of Oracle or Fujitsu Limited, or any affiliate of either of them. This document and the product and technology described in this document may incorporate third-party intellectual property copyrighted by and/or licensed from the suppliers to Oracle and/or its affiliates and Fujitsu Limited, including software and font technology. Per the terms of the GPL or LGPL, a copy of the source code governed by the GPL or LGPL, as applicable, is available upon request by the End User. -
Sparc Enterprise T5440 Server Architecture
SPARC ENTERPRISE T5440 SERVER ARCHITECTURE Unleashing UltraSPARC T2 Plus Processors with Innovative Multi-core Multi-thread Technology White Paper July 2009 TABLE OF CONTENTS THE ULTRASPARC T2 PLUS PROCESSOR 0 THE WORLD'S FIRST MASSIVELY THREADED SYSTEM ON A CHIP (SOC) 0 TAKING CHIP MULTITHREADED DESIGN TO THE NEXT LEVEL 1 ULTRASPARC T2 PLUS PROCESSOR ARCHITECTURE 3 SERVER ARCHITECTURE 8 SYSTEM-LEVEL ARCHITECTURE 8 CHASSIS DESIGN INNOVATIONS 13 ENTERPRISE-CLASS MANAGEMENT AND SOFTWARE 19 SYSTEM MANAGEMENT TECHNOLOGY 19 SCALABILITY AND SUPPORT FOR INNOVATIVE MULTITHREADING TECHNOLOGY21 CONCLUSION 28 0 The UltraSPARC T2 Plus Processors Chapter 1 The UltraSPARC T2 Plus Processors The UltraSPARC T2 and UltraSPARC T2 Plus processors are the industry’s first system on a chip (SoC), supplying the most cores and threads of any general-purpose processor available, and integrating all key system functions. The World's First Massively Threaded System on a Chip (SoC) The UltraSPARC T2 Plus processor eliminates the need for expensive custom hardware and software development by integrating computing, security, and I/O on to a single chip. Binary compatible with earlier UltraSPARC processors, no other processor delivers so much performance in so little space and with such small power requirements letting organizations rapidly scale the delivery of new network services with maximum efficiency and predictability. The UltraSPARC T2 Plus processor is shown in Figure 1. Figure 1. The UltraSPARC T2 Plus processor with CoolThreads technology 1 The UltraSPARC -
Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server Architecture Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server Architecture
An Oracle White Paper February 2014 Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server Architecture Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server Architecture Introduction ....................................................................................... 1 Comparison of SPARC T5–Based Server Features........................... 2 SPARC T5 Processor ........................................................................ 3 Taking Oracle’s Multicore/Multithreaded Design to the Next Level 5 SPARC T5 Processor Architecture ................................................ 6 SPARC T5 Processor Cache Architecture ..................................... 8 SPARC T5 Core Architecture ........................................................ 9 Oracle Solaris for Multicore Scalability............................................. 16 Oracle Solaris 11 Operating System ................................................ 18 Oracle Solaris Predictive Self Healing, Fault Management Architecture, and Service Management Facility ....................................................... 19 Oracle Solaris Cryptographic Frameworks................................... 19 End-to-End Virtualization Technology .............................................. 19 A Multithreaded Hypervisor ......................................................... 20 Oracle VM Server for SPARC ...................................................... 20 Oracle Solaris Zones ................................................................... 21 Enterprise-Class -
Opensparc – an Open Platform for Hardware Reliability Experimentation
OpenSPARC – An Open Platform for Hardware Reliability Experimentation Ishwar Parulkar and Alan Wood Sun Microsystems, Inc. James C. Hoe and Babak Falsafi Carnegie Mellon University Sarita V. Adve and Josep Torrellas University of Illinois at Urbana- Champaign Subhasish Mitra Stanford University IEEE SELSE 4 - March 26, 2008 www.OpenSPARC.net Outline 1.Chip Multi-threading (CMT) 2.OpenSPARC T2 and T1 processors 3.Reliability in OpenSPARC processors 4.What is available in OpenSPARC 5.Current university research using OpenSPARC 6.Future research directions IEEE SELSE 4 – March 26, 2008 2 www.OpenSPARC.net World's First 64-bit Open Source Microprocessor OpenSPARC.net Governed by GPLv2 Complete processor architecture & implementation Register Transfer Level (RTL) Hypervisor API Verification suite and architectural models Simulation model for operating system bringup on s/w IEEE SELSE 4 – March 26, 2008 3 www.OpenSPARC.net Chip Multithreading (CMT) Instruction- Low Low Low Medium Low High level Parallelism Thread-level Parallelism High High High High High Instruction/Data Large Large Medium Large Large Working Set Data Sharing Low Medium High Medium High Medium IEEE SELSE 4 – March 26, 2008 4 www.OpenSPARC.net Memory Bottleneck Relative Performance 10000 CPU Frequency DRAM Speeds 1000 2 Years 100 Every Gap 2x -- CPU 6 10 -- 2x Every DRAM Years 1 1980 1985 1990 1995 2000 2005 Source: Sun World Wide Analyst Conference Feb. 25, 2003 IEEE SELSE 4 – March 26, 2008 5 www.OpenSPARC.net Single Threading HURRY Up to 85% Cycles Waiting for Memory -
Oracle VM Server for SPARC 2.1 Release Notes
Oracle®VM Server for SPARC 2.1 Release Notes Part No: 821–2856–12 February 2012 Copyright © 2007, 2012, Oracle and/or its affiliates. All rights reserved. This software and related documentation are provided under a license agreement containing restrictions on use and disclosure and are protected by intellectual property laws. Except as expressly permitted in your license agreement or allowed by law, you may not use, copy, reproduce, translate, broadcast, modify, license, transmit, distribute, exhibit, perform, publish or display any part, in any form, or by any means. Reverse engineering, disassembly, or decompilation of this software, unless required by law for interoperability, is prohibited. The information contained herein is subject to change without notice and is not warranted to be error-free. If you find any errors, please report them to us in writing. If this is software or related documentation that is delivered to the U.S. Government or anyone licensing it on behalf of the U.S. Government, the following notice is applicable: U.S. GOVERNMENT RIGHTS. Programs, software, databases, and related documentation and technical data delivered to U.S. Government customers are "commercial computer software" or "commercial technical data" pursuant to the applicable Federal Acquisition Regulation and agency-specific supplemental regulations. As such, the use, duplication, disclosure, modification, and adaptation shall be subject to the restrictions and license terms setforth in the applicable Government contract, and, to the extent applicable by the terms of the Government contract, the additional rights set forth in FAR 52.227-19, Commercial Computer Software License (December 2007). Oracle America, Inc., 500 Oracle Parkway, Redwood City, CA 94065.