Quartus II Software and Device Support Release Notes Arria 10 Edition v13.1
RN-01080-13.1Arria10.1 Release Notes
This document provides late-breaking information about the Altera® Quartus® II software Arria® 10 edition v13.1. This document contains the following sections: ■ “Release Description” on page 2 ■ “Memory Recommendations” on page 3 ■ “Changes in Device Support” on page 4 ■ “Changes in Software Behavior” on page 5 ■ “Device Support and Pin-Out Status” on page 12 ■ “Timing and Power Models” on page 13 ■ “EDA Interface Information” on page 14 ■ “Antivirus Verification” on page 15 ■ “Software Issues Resolved” on page 15 ■ “Software Patches Included in this Release” on page 15 ■ “Latest Known Quartus II Software Issues” on page 15 For information about operating system support, refer to the readme.txt file in your altera/
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Arria 10 Edition v13.1 December 2013 Altera Corporation
Subscribe Release Description Page 2
Release Description The Quartus II Arria 10 edition software version 13.1 provides support for Arria 10 devices only. All other Altera devices are supported by the Quartus II software v13.1 release. A Subscription edition license is required to run the Quartus II Arria 10 edition software version 13.1. The Quartus II Arria 10 edition software version 13.1 provides initial device support for the following Arria 10 devices: 10AS066, 10AX066, 10AT115, 10AX115. No other devices or device families are supported by this release of the Quartus II software. The Altera Complete Design Suite (ACDS) Arria 10 edition v13.1 is intended for the following purposes: ■ To provide you with access to software that supports Arria 10 devices ■ To enable board layout of Arria 10 devices in selected packages ■ To allow estimation of Arria 10 resource utilization ■ To allow basic timing assessment with Arria 10 advance timing models. An advance timing model has the following characteristics: ■ Based on an advance version of silicon building blocks ■ Used for coarse understanding of timing performance ■ Used for understanding the floorplanning and pipelining needs of your design architecture ■ Used for estimating routing locations and clock structures ■ Includes paths with no advance information; Altera IP cores include false path assignments for affected paths. The Arria 10 timing model included in this release is scheduled to be replaced by a preliminary timing model in the next production release. ■ Does not serve as an accurate predictor of absolute timing performance, because clock skew and timing delay information in the Arria 10 timing model is expected to change in future releases of the software
1 To migrate a design to an Arria 10 device, some IP cores must be removed and replaced with a new IP variant specific to the Arria 10 device family.
December 2013 Altera Corporation Quartus II Software and Device Support Release Notes Arria 10 Edition v13.1 Memory Recommendations Page 3
Memory Recommendations A full installation of the Quartus II software requires up to 18 GB of available disk space on the drive or partition where you are installing the Altera software. The Quartus II Stand-Alone Programmer requires a minimum of 1GB of RAM plus additional memory, based on the size and number of SRAM Object Files (.sof) files and the size and number of devices being configured. Altera recommends that your system be configured to provide virtual memory equal to the recommended physical RAM that is required to process your design. The following table lists the memory required to process designs targeted for Altera devices.
Recommended Family Device Physical RAM 64-bit 10AX066 32.0 GB 10AS066 32.0 GB Arria 10 10AX115 48.0 GB 10AT115 48.0 GB
December 2013 Altera Corporation Quartus II Software and Device Support Release Notes Arria 10 Edition v13.1 Changes in Device Support Page 4
Changes in Device Support This section documents device support changes.
Description Workaround
Change Notifications
fPLL doesn't support fractional mode in simulation. Any fPLL in fractional configuration generated from the Arria 10 Do not use the fractional mode to simulate designs. fPLL MegaWizard (altera_xcvr_fpll_a10 IP) will not lock in simulation.
get_pins in TimeQuest does not support PLL clock outputs TimeQuest will show matching "pins" related to IOPLL and fPLL when get_pins is used as collection method; however, when Use get_nets, or get_clocks to create constraints on the PLL pins are used as a filter to generate a custom clock, PLL. TimeQuest displays an ignored filter warning that the given pin could not be matched.
Source synchronous compensation is not supported Use direct or normal compensation mode, which are The Arria 10 FPLL megafunction does not support source supported. synchronous compensation mode in this release.
Pin-Out File might contain incorrect voltages The Pin-Out File (.pin) generated by the Quartus II software might contain incorrect voltages for some Arria 10 ES voltage rails. The voltage rails affected are: ■ VCC Contact Altera support to obtain the correct voltages. ■ VCCL ■ VCCERAM ■ VCCL_HPS ■ VCCIOREF_HPS ■ VCCPLL_HPS To set the correct VCCIO voltage, add the following line Default VCCIO voltage for 10AX115 devices is incorrect to your project’s Quartus II Settings File (.qsf): On the Voltage page of the Quartus II software, the default set_global_assignment -name voltage listed for VCCIO (2.5 V) is incorrect. STRATIX_DEVICE_IO_STANDARD "1.8 V"
December 2013 Altera Corporation Quartus II Software and Device Support Release Notes Arria 10 Edition v13.1 Changes in Software Behavior Page 5
Changes in Software Behavior This section documents instances in which the behavior and default settings of the Quartus II software have been changed from earlier releases of the software, and known issues with the software. Refer to the Quartus II Default Settings File (.qdf),
Description Workaround
Incremental Compilation limitations The Quartus II software Incremental Compilation feature reduces compilation time by up to 50% and helps you to preserve performance and to ease timing closure. The routing preservation and partial reconfiguration flows for incremental compilation are not supported in this release.
RTL Simulation fails with NativeLink If you use NativeLink to run EDA RTL simulation after running a full To avoid the error, run Analysis & Elaboration only compilation, the simulation fails and displays the following error (instead of a full compilation) and then run your message: RTL simulation with NativeLink. ** Error: (vlog-7) Failed to open design unit file "
Large Periphery clock networks are not supported Use a different clock network type, such as a Large Periphery clock networks are not supported in this release of the Regional Clock, or rely on the Quartus II automatic Quartus II software. The option to target a global signal to a Large global signal promotion feature to choose an Peripheral clock region is not available in the Arria 10 ALTCLKCTRL appropriate clock network type. megafunction nor in Quartus II global signal assignments.
Early timing analysis flow The early timing analysis flow (--post_map) in the TimeQuest Timing Analyzer has changed in this release. In previous versions of the Quartus II software, the flow for early timing analysis was: quartus_map
Create Timing Netlist does not support speed grade selection In the Create Timing Netlist dialog box, do not Specify Speed Grade in the Create Timing Netlist dialog box of the turn on Specify Speed Grade and do not select a TimeQuest Timing Analyzer is not supported in this release. Selecting a Speed grade. speed grade generates an error.
December 2013 Altera Corporation Quartus II Software and Device Support Release Notes Arria 10 Edition v13.1 Changes in Software Behavior Page 6
Description Workaround
Report Timing Closure Recommendations is not available The Report Timing Closure Recommendations feature of the TimeQuest Timing Analyzer is not available in this release.
Report Metastability is not available The Report Metastability feature of the TimeQuest Timing Analyzer is not available in this release.
Registers feeding an empty top partition cannot be timing analyzed If the register is located in a LAB, DSB, or memory Registers in a child partition than feed only paths in its parent partition block, you may add another register as a fanout of might not be timing analyzed if the Netlist Type of the parent partition is the first register so that the first register feeds Empty. This means that timing paths that are fully contained within the some path in the child partition. The path will then child partition might not have their slacks reported if the paths be analyzed by TimeQuest. terminate at such a register.
Internal Error: Sub-system: ACVQM, File: /quartus/ace/acvq/acvqm/acvqm_mapper.cpp, Line: 4042 If you attempt to locate a timing path from the Report Timing report in the TimeQuest Timing Analyzer to the Chip Planner with Show Routing If you want to locate a timing path in the Chip turned on, and then select the located path in the Chip Planner, the Chip Planner, do not turn on Show Routing. Planner generated the following error: Internal Error: Sub-system: ACVQM, File: /quartus/ace/acvq/acvqm/acvqm_mapper.cpp, Line: 4042 Altera recommends that you minimize hard-coded file paths, directory structure assumptions, or Arria 10 IP infrastructure is preliminary node and entity names in SDC constraints, The directory structure, file names, module and entity naming scripts, and other infrastructure. Altera conventions, and saved parameterization format for all IP variants in recommends that you rely on the contents of Arria 10 IP are preliminary and subject to change in a future release of generated report files. the Quartus II software. Altera also recommends that you avoid editing generated IP files. Quartus II Settings File error when migrating or upgrading IP To avoid the error, unarchive the project, and then Unarchiving a Quartus II project in the Quartus II Arria 10 edition close and reopen the Quartus II Arria 10 edition software version 13.1, and then migrating to an Arria 10 device or software version 13.1 to reload the unarchived upgrading the version of some IP (for example, FIFO) might lead to project. errors about the Quartus II Settings file becoming corrupted.
Arria 10 -1 speed grade is not available Some IP GUIs might display -1 speed grade as an option. However, the -1 speed grade is not available in the Quartus II Arria 10 edition Do not use a -1 speed grade. software version 13.1. Generating IP or compiling a design can result in unexpected behavior or errors.
ALTERA_MULT_ADD megafunction: missing variation file Before you run RTL simulation with Nativelink, When it generates an ALTERA_MULT_ADD megafunction, the manually add the variation file (.v or .vhd) to the MegaWizard Plug-In Manager does not include the variation file. Nativelink-generated DO file.
December 2013 Altera Corporation Quartus II Software and Device Support Release Notes Arria 10 Edition v13.1 Changes in Software Behavior Page 7
Description Workaround
RAM Initializer megafunction not supported The RAM Initializer megafunction (ALTMEM_INIT) is not supported in the current release of the Quartus II software. You are not able to create a new RAM Initializer megafunction. If you attempt to regenerate a RAM Initializer megafunction created in a previous version of the Quartus II Do not use the RAM Initializer megafunction. software, regeneration fails with the error: Error: This IP core variant was created for a different device family and is not compatible with the Arria 10 device family.
Setup timing violations with the Interlaken IP core The Interlaken 12 lane X 12.5 Gbps variant might generate setup violations between the following paths: You may safely ignore these setup timing violations. ■ From the M20K ECC status signals to status capture registers ■ From pld_10g_tx to the loose_ready_r. register
IP Upgrade of 40G/100G Ethernet IP Core fails If your design contains a 40G/100G Ethernet IP core and you attempt to Remove the 40G/100G Ethernet IP core from your open the design in the Quartus II Arria 10 edition software version 13.1, design to continue with the IP upgrade process, the IP Upgrade process fails, and then replace the core with the Low Latency The upgrade process fails because the 40G/100G Ethernet IP core does 40G/100G Ethernet IP core. not support the Arria 10 device family.
Low Latency 10G MAC MegaCore IP: TX path CRC insertion must be turned on In Low Latency 10G MAC designs, if you turn on PTP 1-step clock If you turn on PTP 1-step clock support, turn on support, you must also turn on CRC insertion. If you do not turn on CRC insertion. CRC insertion, some data frames might be incorrect with the pause frames and data frames interleave.
Low Latency 10G MAC MegaCore IP: Do not turn on both Enable pass-through mode Preamble pass-through mode does not work with PFC frames and Enable priority-based flow control (PFC). Designs with Enable preamble pass-through mode and Enable You can turn on one or the other, but not both priority-based flow control (PFC) options turned on produce incorrect options. data when the pause frames and data frames interleave.
Transceiver IP cores must be regenerated in future releases of the Quartus II software Transceiver-related IP cores, including Arria 10 Transceiver Native PHY, Arria 10 Transceiver ATX PLL, Arria 10 Transceiver CMU PLL, and Refer to the Arria 10 Transceiver PHY User Guide Arria 10 FPLL will require IP regeneration in future releases of the and the Arria 10 Device Handbook for additional Quartus II software. information and guidance. Transceiver IP cores in this release have only a limited amount of checking for data rate limits, and will allow you to create configurations that might be invalid in future releases of the Quartus II software. Altera recommends waiving these timing Transceiver timing violations violations in the Quartus II Arria 10 edition Timing analysis of transceiver designs might report timing violations software version 13.1. between transceivers and the core, because Arria 10 timing models are These timing violations are expected to resolve advance. The probability of observing timing violations is with updates to the Arria 10 timing models in a approximately 10% to 15%. future release of the Quartus II software.
December 2013 Altera Corporation Quartus II Software and Device Support Release Notes Arria 10 Edition v13.1 Changes in Software Behavior Page 8
Description Workaround
Source and Destination names in paths to and from hard blocks You can obtain accurate names for the source and The TimeQuest Timing Analyzer does not report the names of sources destination of paths to and from hard blocks by or destinations correctly. For paths to and from hard blocks, such as using Report Timing with detailed path the HSSI, TimeQuest reports the source or destination as a clock information: register (for example, wys~pma_rx_pma_clk.reg). report_timing -detail full_path
Transceiver Native PHY IP has an extra SDC file Native PHY IP cores include an extra.sdc file named The extra file has no impact on your design if you altera_xcvr_native_a10_b2.sdc (along with source the fileset generated by Native PHY in your altera_xcvr_native_a10_false_paths.sdc). This version 13.1 IP or core logic. Arria 10-specific .sdc file is included to cut unintentional timing arcs inside the HSSI timing models.
Migration of PCIe® HIP from Stratix V devices to Arria 10 devices A project that targets a Stratix® V device and that includes a PCI To migrate a PCIe HIP block from a Stratix V Express® hard IP (PCIe HIP) block will not compile if you change the device to an Arria 10 device, you must recreate the target device to the Arria 10 family. IP block by using the Arria 10 PCIe User Interface. The Arria 10 HIP _hw.tcl file generates a similar set of files as the You must re-enter all the Stratix V HIP Stratix V HIP _hw.tcl file. The Arria 10 HIP _hw.tcl file generates: parameters. ■ Verilog and VHDL variants that include the HIP, PHY IP, and PLL instances ■ .qip and .sdc files ■ a Qsys design example that includes simulation support with PCIe BFM and PCIe simulation drive.
32 bit PIPE simulation is not supported; for PCIe Gen3, only serial 32 bit PIPE simulation support is planned for a simulation is supported. future release. coreclkout pin out of the PCIe HIP in Arria 10 devices differs from If you have only a small amount of logic running Stratix V devices, such that in Arria 10 devices it is on a global clock off of coreclkout, be aware that you will network. This clock network change facilitates timing closure of your consume a global clock buffer resource on the core application. device; if you leave the pin unconnected, the Quartus II software optimizes it away. Timing violations with 1G/10GbE and Backplane Ethernet 10GBASE-KR PHY IP core Because the Arria 10 timing model is advance, you During compilation, the TimeQuest Timing Analyzer might report timing may ignore these timing violations. violations to and from the 1G/10GbE and Backplane Ethernet 10GBASE-KR PHY IP core. To support data widths of 256 bits, instantiate two Altera GPIO megafunction limitations Altera GPIO megafunctions and manually connect The Altera GPIO megafunction supports data widths up to 128 bits. their input and output ports. Altera OCT megafunction limitations The Altera OCT megafunction: ■ does not support user mode OCT, and ■ does not support VHDL generation
December 2013 Altera Corporation Quartus II Software and Device Support Release Notes Arria 10 Edition v13.1 Changes in Software Behavior Page 9
Description Workaround
Altera SERDES megafunction limitations The Altera SERDES megafunction: ■ does not support external PLL mode in this release ■ does not support using pll_areset as a master reset for the block, and ■ the a TX outclock divide factor of 1 is no longer supported.
December 2013 Altera Corporation Quartus II Software and Device Support Release Notes Arria 10 Edition v13.1 Changes in Software Behavior Page 10
Description Workaround
Altera PHYLite for Memory megafunction limitations The Altera PHYLite for Memory megafunction: ■ cannot be simulated with Aldec Riviera-PRO software ■ must use the -novopt flag for VHDL simulation with Mentor Graphics ModelSim SE ■ does not support post-map-and post-fit simulations with VHDL designs.
External Memory Interface (EMIF) limitations ■ Because the PHY, memory controller and calibration processor are all hardened, UniPHY IP cores are not used for Arria 10 devices. ■ In X8 interfaces, the DM pin must be paired with a DQ pin for proper functionality. The Quartus II software does not perform a legality check for this pairing. In any 12 I/O lane, the pairs are: 0/1, 2/3, 4/5, 6/7, 8/9, 10/11 . 0/1, 2/3, 4/5, 6/7, 8/9, 10/11. ■ X4 DQS groups are not supported. ■ Core and periphery clock phase alignment is not supported. ■ Core-to-periphery and periphery-to-core paths are not analyzed. ■ Soft controllers are not supported. ■ DDR3 and DDR4 limitations. ■ RDIMM and LRDIMM is not supported. ■ Pin planning of on-die termination (ODT) is supported, but not generation or simulation. ■ Low frequency external memory interfaces (<400 MHz) are not supported. ■ Ultra wide external memory interfaces (x144) are not supported. ■ Additive latency is not supported. ■ Interleaved bursts are not supported. ■ DDR4 BL 10/CRC is not supported. ■ DDR4 CS-to-ADDR latency mode is not supported. ■ Pin planning of DDR4 Address/Command parity is supported, but not generation or simulation. ■ Simulation limitations ■ Full calibration is not supported. ■ Post-fit simulation is not supported. ■ Mult-rank can be generated, but not simulated. ■ You can generate and simulate external memory interfaces with Mentor Graphics ModelSim SE and ModelSim Altera Edition; ModelSim SE performance is significantly better than ModelSim Altera Edition. ■ You can generate and simulate external memory interfaces with Synopsys VCS and VCS MX. ■ You can generate, but not simulate external memory interfaces with Cadence INCISIVE Enterprise Simulator and Aldec Riviera-PRO.
December 2013 Altera Corporation Quartus II Software and Device Support Release Notes Arria 10 Edition v13.1 Changes in Software Behavior Page 11
December 2013 Altera Corporation Quartus II Software and Device Support Release Notes Arria 10 Edition v13.1 Device Support and Pin-Out Status Page 12
Device Support and Pin-Out Status This section contains information about the device support status in the Quartus II Arria 10 edition software version 13.1.
Full Device Support Full compilation, simulation, timing analysis, and programming support is now available for the new devices listed in the following table.
Device Family Devices None N/A N/A
Advance Device Support Compilation, simulation, and timing analysis support is provided for the devices listed in the following table that will be released in the near future. The Compiler generates pin-out information for these devices in this release, but does not generate programming files.
Device Family Devices Arria 10 10AX115 —
Initial Information Device Support Compilation, simulation, and timing analysis support is provided for the devices listed in the following table that will be released in upcoming versions of the Quartus II software. Programming files and pin-out information are not generated for these devices in this release.
Device Family Devices 10AX066 10AS066 Arria 10 10AT115 —
December 2013 Altera Corporation Quartus II Software and Device Support Release Notes Arria 10 Edition v13.1 Timing and Power Models Page 13
Timing and Power Models The following table lists a summary of timing and power model status in the current version of the Quartus II software.
Timing Model Device Family Device Power Model Status Status (1) 10AX066 Advance N/A 10AS066 Advance N/A Arria 10 10AX115 Advance N/A 10AT115 Advance N/A Note: (1) This release contains advance timing models for the Arria 10 devices. These models will change and should not be relied on for production timing. For more information about working with advance timing models, please contact Altera.
IBIS Models The following table lists a summary of IBIS model status in the current version of the Quartus II software.
Device Family IBIS Model Status None N/A
December 2013 Altera Corporation Quartus II Software and Device Support Release Notes Arria 10 Edition v13.1 EDA Interface Information Page 14
EDA Interface Information The Quartus II Arria 10 edition software version 13.1 supports the following EDA tools.
NativeLink Synthesis Tools Version Support Mentor Graphics® Precision 2013ba Synopsys® Synplify, Synplify Pro, and Synplify Premier 2013.09-SP1 (a) NativeLink Simulation Tools Version Support 9.2 SP1 Aldec Active-HDL (Windows only) Aldec Riviera-PRO 2013.06 12.20.14 Cadence INCISIV Enterprise Simulator (Linux only) Mentor Graphics ModelSim® PE 10.1d Mentor Graphics ModelSim SE 10.2b Mentor Graphics ModelSim-Altera 10.1d Mentor Graphics Questa® 10.2b Synopsys VCS and VCS MX 2013.06-1 a. EDA Synthesis tools that support Arria 10 devices will be released by vendors shortly after the release of the Quartus II Arria 10 edition software v13.1. Contact your vendor account manager for details.
December 2013 Altera Corporation Quartus II Software and Device Support Release Notes Arria 10 Edition v13.1 Antivirus Verification Page 15
Antivirus Verification The Quartus II Arria 10 edition software v13.1 has been verified virus free using the following software: McAfee VirusScan Enterprise + AntiSpyware Enterprise Version: 8.8.0 (8.8.0.975) Scan Engine Version (32 bit): 5600.1067 Scan Engine Version (64 bit): 5600.1067 DAT Version: 7234.0000
Software Issues Resolved No Customer Service Requests were fixed or otherwise resolved in the Quartus II Arria 10 edition software v13.1.
Software Patches Included in this Release No software patches released for previous versions of the Quartus II software version are included in the Quartus II Arria 10 edition software version 13.1.
Latest Known Quartus II Software Issues For more information about known software issues, look for information on the Quartus II Software Support page at the following URL: http://www.altera.com/support/software/sof-quartus.html You can find known issue information for previous versions of the Quartus II software on the Knowledge Database page at the following URL: http://www.altera.com/support/kdb/kdb-index.jsp
Document Revision History The following table shows the revision history for this document.. Document Revision History Date Version Changes December 2013 Arria 10 Edition v13.1.1 Updated the “Timing and Power Models” section. December 2013 Arria 10 Edition v13.1.0 Initial release
December 2013 Altera Corporation Quartus II Software and Device Support Release Notes Arria 10 Edition v13.1