Safety Analysis Integration in a Systems Engineering Approach for Mechatronic Systems Design Faïda Mhenni
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Systemverilog
SystemVerilog ● Industry's first unified HDVL (Hw Description and Verification language (IEEE 1800) ● Major extension of Verilog language (IEEE 1364) ● Targeted primarily at the chip implementation and verification flow ● Improve productivity in the design of large gate-count, IP- based, bus-intensive chips Sources and references 1. Accellera IEEE SystemVerilog page http://www.systemverilog.com/home.html 2. “Using SystemVerilog for FPGA design. A tutorial based on a simple bus system”, Doulos http://www.doulos.com/knowhow/sysverilog/FPGA/ 3. “SystemVerilog for Design groups”, Slides from Doulos training course 4. Various tutorials on SystemVerilog on Doulos website 5. “SystemVerilog for VHDL Users”, Tom Fitzpatrick, Synopsys Principal Technical Specialist, Date04 http://www.systemverilog.com/techpapers/date04_systemverilog.pdf 6. “SystemVerilog, a design and synthesis perspective”, K. Pieper, Synopsys R&D Manager, HDL Compilers 7. Wikipedia Extensions to Verilog ● Improvements for advanced design requirements – Data types – Higher abstraction (user defined types, struct, unions) – Interfaces ● Properties and assertions built in the language – Assertion Based Verification, Design for Verification ● New features for verification – Models and testbenches using object-oriented techniques (class) – Constrained random test generation – Transaction level modeling ● Direct Programming Interface with C/C++/SystemC – Link to system level simulations Data types: logic module counter (input logic clk, ● Nets and Variables reset, ● enable, Net type, -
White Paper on Approaches to Safety Engineering∗
White Paper on Approaches to Safety Engineering∗ Nancy Leveson April 23, 2003 A life without adventure is likely to be unsatisfying, but a life in which adventure is allowed to take whatever form it will, is likely to be short. — Bertrand Russell This white paper lays out some foundational information about different approaches to safety: how various industries differ in their approaches to safety engineering, and a comparison of three general approaches to safety (system safety, industrial safety engineering, and reliability engineer- ing).An attempt is made to lay out the properties of industries and systems that make one approach more appropriate than another. How do industries differ in their approaches to safety engineering? While the concern about industrial safety dates back to at least the turn of the century (and before in some countries and industries) and individual efforts to design safe products and systems also goes back in time, rigorous and defined approaches to safety engineering mostly arose after World War II, when the AEC (and later the NRC) were engaged in a public debate about the safety of nuclear power; civil aviation was trying to convince a skeptical public to fly; the chemical indus- try was coping with larger plants, increasingly lethal chemicals, and heightened societal concern about pollution; and the DoD was developing ballistic missile systems and increasingly dangerous weapons.Each of these parallel efforts resulted in very different engineering approaches, mostly because the problems they needed to solve were different. Commercial Aircraft The [FAA] administrator was interviewed for a documentary film on the [Paris DC-10] accident. -
Development of Systemc Modules from HDL for System-On-Chip Applications
University of Tennessee, Knoxville TRACE: Tennessee Research and Creative Exchange Masters Theses Graduate School 8-2004 Development of SystemC Modules from HDL for System-on-Chip Applications Siddhartha Devalapalli University of Tennessee - Knoxville Follow this and additional works at: https://trace.tennessee.edu/utk_gradthes Part of the Electrical and Computer Engineering Commons Recommended Citation Devalapalli, Siddhartha, "Development of SystemC Modules from HDL for System-on-Chip Applications. " Master's Thesis, University of Tennessee, 2004. https://trace.tennessee.edu/utk_gradthes/2119 This Thesis is brought to you for free and open access by the Graduate School at TRACE: Tennessee Research and Creative Exchange. It has been accepted for inclusion in Masters Theses by an authorized administrator of TRACE: Tennessee Research and Creative Exchange. For more information, please contact [email protected]. To the Graduate Council: I am submitting herewith a thesis written by Siddhartha Devalapalli entitled "Development of SystemC Modules from HDL for System-on-Chip Applications." I have examined the final electronic copy of this thesis for form and content and recommend that it be accepted in partial fulfillment of the equirr ements for the degree of Master of Science, with a major in Electrical Engineering. Dr. Donald W. Bouldin, Major Professor We have read this thesis and recommend its acceptance: Dr. Gregory D. Peterson, Dr. Chandra Tan Accepted for the Council: Carolyn R. Hodges Vice Provost and Dean of the Graduate School (Original signatures are on file with official studentecor r ds.) To the Graduate Council: I am submitting herewith a thesis written by Siddhartha Devalapalli entitled "Development of SystemC Modules from HDL for System-on-Chip Applications". -
System Safety Engineering: Back to the Future
System Safety Engineering: Back To The Future Nancy G. Leveson Aeronautics and Astronautics Massachusetts Institute of Technology c Copyright by the author June 2002. All rights reserved. Copying without fee is permitted provided that the copies are not made or distributed for direct commercial advantage and provided that credit to the source is given. Abstracting with credit is permitted. i We pretend that technology, our technology, is something of a life force, a will, and a thrust of its own, on which we can blame all, with which we can explain all, and in the end by means of which we can excuse ourselves. — T. Cuyler Young ManinNature DEDICATION: To all the great engineers who taught me system safety engineering, particularly Grady Lee who believed in me, and to C.O. Miller who started us all down this path. Also to Jens Rasmussen, whose pioneering work in Europe on applying systems thinking to engineering for safety, in parallel with the system safety movement in the United States, started a revolution. ACKNOWLEDGEMENT: The research that resulted in this book was partially supported by research grants from the NSF ITR program, the NASA Ames Design For Safety (Engineering for Complex Systems) program, the NASA Human-Centered Computing, and the NASA Langley System Archi- tecture Program (Dave Eckhart). program. Preface I began my adventure in system safety after completing graduate studies in computer science and joining the faculty of a computer science department. In the first week at my new job, I received a call from Marion Moon, a system safety engineer at what was then Ground Systems Division of Hughes Aircraft Company. -
Manuscript Instructions/Template
INCOSE Working Group Addresses System and Software Interfaces Sarah Sheard, Ph.D. Rita Creel CMU Software Engineering Institute CMU Software Engineering Institute (412) 268-7612 (703) 247-1378 [email protected] [email protected] John Cadigan Joseph Marvin Prime Solutions Group, Inc. Prime Solutions Group, Inc. (623) 853-0829 (623) 853-0829 [email protected] [email protected] Leung Chim Michael E. Pafford Defence Science & Technology Group Johns Hopkins University +61 (0) 8 7389 7908 (301) 935-5280 [email protected] [email protected] Copyright © 2018 by the authors. Published and used by INCOSE with permission. Abstract. In the 21st century, when any sophisticated system has significant software content, it is increasingly critical to articulate and improve the interface between systems engineering and software engineering, i.e., the relationships between systems and software engineering technical and management processes, products, tools, and outcomes. Although systems engineers and software engineers perform similar activities and use similar processes, their primary responsibilities and concerns differ. Systems engineers focus on the global aspects of a system. Their responsibilities span the lifecycle and involve ensuring the various elements of a system—e.g., hardware, software, firmware, engineering environments, and operational environments—work together to deliver capability. Software engineers also have responsibilities that span the lifecycle, but their focus is on activities to ensure the software satisfies software-relevant system requirements and constraints. Software engineers must maintain sufficient knowledge of the non-software elements of the systems that will execute their software, as well as the systems their software must interface with. -
Powerplay Power Analysis 8 2013.11.04
PowerPlay Power Analysis 8 2013.11.04 QII53013 Subscribe Send Feedback The PowerPlay Power Analysis tools allow you to estimate device power consumption accurately. As designs grow larger and process technology continues to shrink, power becomes an increasingly important design consideration. When designing a PCB, you must estimate the power consumption of a device accurately to develop an appropriate power budget, and to design the power supplies, voltage regulators, heat sink, and cooling system. The following figure shows the PowerPlay Power Analysis tools ability to estimate power consumption from early design concept through design implementation. Figure 8-1: PowerPlay Power Analysis From Design Concept Through Design Implementation PowerPlay Early Power Estimator Quartus II PowerPlay Power Analyzer Higher Placement and Simulation Routing Results Results Accuracy Quartus II Design Profile User Input Estimation Design Concept Design Implementation Lower PowerPlay Power Analysis Input For the majority of the designs, the PowerPlay Power Analyzer and the PowerPlay EPE spreadsheet have the following accuracy after the power models are final: • PowerPlay Power Analyzer—±20% from silicon, assuming that the PowerPlay Power Analyzer uses the Value Change Dump File (.vcd) generated toggle rates. • PowerPlay EPE spreadsheet— ±20% from the PowerPlay Power Analyzer results using .vcd generated toggle rates. 90% of EPE designs (using .vcd generated toggle rates exported from PPPA) are within ±30% silicon. The toggle rates are derived using the PowerPlay Power Analyzer with a .vcd file generated from a gate level simulation representative of the system operation. © 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. -
Infrastructure (Resilience-Oriented) Modelling Language: I®ML
Infrastructure (Resilience-oriented) Modelling Language: I®ML A proposal for modelling infrastructures and their interconnections Andrés Silva, Roberto Filippini EUR 24727 EN - 2011 The mission of the JRC-IPSC is to provide research results and to support EU policy-makers in their effort towards global security and towards protection of European citizens from accidents, deliberate attacks, fraud and illegal actions against EU policies. European Commission Joint Research Centre Institute for the Protection and Security of the Citizen Contact information Address: TP 210, EC JRC Ispra, Ispra (Va) Italy E-mail: [email protected] Tel.: +39 0332 789936 Fax: http://ipsc.jrc.ec.europa.eu/ http://www.jrc.ec.europa.eu/ Legal Notice Neither the European Commission nor any person acting on behalf of the Commission is responsible for the use which might be made of this publication. Europe Direct is a service to help you find answers to your questions about the European Union Freephone number (*): 00 800 6 7 8 9 10 11 (*) Certain mobile telephone operators do not allow access to 00 800 numbers or these calls may be billed. A great deal of additional information on the European Union is available on the Internet. It can be accessed through the Europa server http://europa.eu/ JRC 63302 EUR 24727 EN ISBN 978-92-79-19324-8 ISSN 1018-5593 doi:10.2788/54708 Luxembourg: Publications Office of the European Union © European Union, 2011 Reproduction is authorised provided the source is acknowledged Printed in Italy Infrastructure (Resilience-oriented) Modelling Language: I®ML A proposal for modelling infrastructures and their connections Andrés Silva1 Roberto Filippini Universidad Politécnica de Madrid JRC of the European Commission Abstract The modelling of critical infrastructures (CIs) is an important issue that needs to be properly addressed, for several reasons. -
VHDL Modelling Guidelines Simulation and Documentation Aspects
Second draft, 23 February 1997 CENELEC TC217/WG2 report 2.14 English version VHDL Modelling Guidelines Simulation and Documentation Aspects This CENELEC Report is under preparation and review by the Technical Committee CENELEC TC 217 Working Group 2. CENELEC members are the national electrotechnical committees of Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland and United Kingdom. CENELEC European Committee for Electrotechnical Standardisation Comité Européen de Normalisation Electrotechnique Europäisches Komitee für Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B-1050 Brussels CENELEC TC217/WG2 report 2.142 Second draft, 23 February 1997 3DJH LQWHQWLRQDOO\ OHIW EODQN Second draft, 23 February 19973 CENELEC TC217/WG2 report 2.14 )25(:25' 7KLV 7HFKQLFDO 5HSRUW LV WKH ILUVW GUDIW RI WKH &(1(/(& 7&:* UHSRUW 7KH UHSRUW LV GHULYHG IURP WKH (XURSHDQ 6SDFH $JHQF\ V (6$©V 9+'/ 0RGHOOLQJ *XLGHOLQHV UHIHUHQFH $6,& LVVXH GDWHG 6HSWHPEHU 7KLV GUDIW KDV EHHQ SUHSDUHG WDNLQJ LQWR DFFRXQW FRPPHQWV IURP &(1(/(& :* PHPEHUV SUHVHQWHG RQ WKH GHGLFDWHG HPDLO UHIOHFWRU 7KH DXWKRU ZRXOG OLNH WR WKDQN DOO FRQWULEXWRUV IRU WKHLU YDOXDEOH LQSXW 7KH (6$ 9+'/ 0RGHOOLQJ *XLGHOLQHV KDYH EHHQ XVHG LQ (6$ GHYHORSPHQW DQG VWXG\ FRQWUDFWV WR HQVXUH KLJKTXDOLW\ PDLQWDLQDEOH 9+'/ PRGHOV 7KH\ KDYH EHHQ SUHSDUHG E\ 3HWHU 6LQDQGHU ZLWK VXSSRUW IURP 6DQGL +DELQF ERWK DW WKH (6$(67(& 0LFURHOHFWURQLFV DQG 7HFKQRORJ\ 6HFWLRQ :60 32 %R[ $* 1RRUGZLMN -
IS2018 Book of Abstract
th Annual INCOSE 28 international symposium Washington, DC, USA July 7 - 12, 2018 Delivering Systems in the Age of Globalization Status as of May 15 th , 2018 Book of Abstract Table of contents keynotes ............................................................................................................................................................................... p. 7 keynotes#Keynote#2: The Big Shift: Innovation and Systems Engineering ................................................................ p. 7 Papers .................................................................................................................................................................................. p. 8 Papers#107: A Framework for Concept and its Testing on Patents ............................................................................ p. 8 Papers#75: A Framework for Testability Analysis from System Architecture Perspective .......................................... p. 9 Papers#128: A Framework for Understanding Systems Principles and Methods .......................................................p. 10 Papers#31: A fresh look at Systems Engineering - what is it, how should it work? .....................................................p. 11 Papers#35: A Hybrid Liver-Candidate Transportation System to Improve Accessibility and Extend Organ Life in L ..p. 12 Papers#55: A Novel “Resilience Viewpoint” to aid in Engineering Resilience in Systems of Systems (SoS) .............p. 13 Papers#97: A successful use of systems approaches in -
Process Safety for the 21St Century and Beyond This Initiative
Process Safety for the 21st Century and Beyond 1 Introduction Process safety has been practiced as a field of research and 1.1 Who was involved in this project? safety management in the oil and chemical industries since the 1960s. Over this period there have been many tragic incidents, This project was led by a steering committee convened to bring which have resulted in fatalities as well as asset, environmental, in academic, industrial, regulatory, and societal perspectives and reputational damage. While standards have improved from around the world and across stakeholders. Trish Kerin, the since then and much work has been done, particularly in director of the IChemE Safety Centre and Dr M Sam Mannan, inherently safer design and management systems, catastrophic the executive director of Mary Kay O’Connor Process Safety incidents are still happening and will continue to do so until Center were the co-chairs of the steering committee. The team we tackle them head on. It appears as if we are not learning members are listed below, and biographical details can be lessons from the past, because the causes of failures for found in Appendix A. current incidents are the same as past incidents, albeit in Team members different environments. We must learn from these incidents. As an industry, our inability to learn from past incidents and ■■ Dr Paul Amyotte demonstrate that process safety is improving has led to this ■■ Dr Ian Cameron project, Process Safety in the 21st Century and Beyond. The aim of this project is to envision better process safety by ■■ Dr Mike Considine outlining efforts that each stakeholder can take. -
Waveform Editor
1. Quartus II Simulator QII53017-9.1.0 This chapter describes how to perform different types of simulations with the Quartus II simulator. Introduction With today’s FPGAs becoming faster and more complex, designers face challenges in validating their designs. Simulation verifies the correctness of the design, reducing board testing and debugging time. The Altera® Quartus® II simulator is included in the Quartus II software to assist designers with design verification. The Quartus II simulator has a comprehensive set of features that are covered in the following sections: ■ “Simulation Flow” on page 1–2 ■ “Waveform Editor” on page 1–5 ■ “Simulator Settings” on page 1–13 ■ “Simulation Report” on page 1–16 ■ “Debugging with the Quartus II Simulator” on page 1–19 ■ “Scripting Support” on page 1–21 The Quartus II simulator supports the following device families: ■ ACEX® 1K ■ APEX™ 20KC, APEX 20KE, APEX II ■ Arria® GX ■ Cyclone® III, Cyclone II, Cyclone ■ FLEX® 10K, FLEX 10KA, FLEX 10KE, FLEX 6000 ■ HardCopy® II, HardCopy ■ MAX® II, MAX 3000A, MAX 7000AE, MAX 7000B, MAX 7000S ■ Stratix® III, Stratix II, Stratix, Stratix GX, Stratix II GX 1 The Quartus II simulator does not support newer devices introduced after Stratix III and Quartus II software version 8.1 and onwards. Use the ModelSim-Altera Edition to run simulations on designs targeting device introductions after Stratix III. For more information about the ModelSim-Altera Edition simulator, refer to the Mentor Graphics ModelSim Support chapter in volume 3 of the Quartus II Handbook. In the Quartus II software version 10.0 and onwards, the Quartus II simulator and Waveform Editor is removed. -
VHDL Verification of FPGA Based ESF-CCS for Nuclear Power Plant I&C
VHDL Verification of FPGA based ESF-CCS for Nuclear Power Plant I&C System Restu MAERANI1, and Jae Cheon JUNG2 1. Department of NPP Engineering, KINGS, Ulsan, 45014, Indonesia ([email protected]) 2. Department of NPP Engineering, KINGS, Ulsan, 45014, Republic of Korea ([email protected]) Abstract: Verification becomes the focus of activities during the integration phase of design life cycle in the development of the system. Verification methods that will not take much cost and time should be properly selected, accordance with the Measurement of Effectiveness (MOEs) need. Verification is one phase that must be done after completing the implementation process. Since Instrumentation & Control (I&C) system has a role as a very crucial to the control protection system in Nuclear Power Plant (NPP), then software verification is very essential and shall to be achieved for safety critical issue in system level. According to IEEE 1076-2008 standard, VHDL is a language that is easy to read by machines and humans; and make it easier for process development, verification, synthesis and testing for hardware reliability in the design. Because this design uses VHDL code for Field Programmable Gate Array (FPGA) based Engineered Safety features – Component Control System (ESF-CCS) and by referring to the NUREG/CR-7006 during VHDL verification on behavioral simulation process, it should be equivalent with the post layout simulation. Furthermore, Vivado will be used as the VHDL verifier, where the VHDL code itself is created, in order to simplify the process of verification with this design life cycle phase on re-engineering process.