DOCSLIB.ORG

Ibm Approved Memory

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Ibm Approved Memory IBM APPROVED MEMORY 33L3308-E 1GB 184pin PC2100 DDR DIMM, IBM NetVista 6824, 6826, A30 6824-xxx, A30 8324-xxx, A30p 2289, M42 8181-xxx, M42 8182-xxx, M42 8301-xxx, M42 8302-xxx, M42 8303-xxx 33L3309-E 1GB 184pin PC2100 DDR DIMM, IBM NetVista 6824, 6826, A30 6824-xxx, A30 8324-xxx, A30p 2289, M42 8181-xxx, M42 8182-xxx, M42 8301-xxx, M42 8302-xxx, M42 8303-xxx 22P9272-E 1GB Unbuffered Non-ECC DDR400/PC3200 DIMM 184PIN, IBM-Lenovo 3000 H100 8789-xxx, H100 8823-xxx, H100 8824-xxx, 3000 J100 8253, 3000 J100 825325U, J100 825326U, 22P9274-E 1GB Unbuffered Non-ECC DDR400/PC3200 DIMM 184PIN, IBM-Lenovo 3000 H100 8789-xxx, H100 8823-xxx, H100 8824-xxx, 3000 J100 8253, 3000 J100 825325U, J100 825326U, 31P8857-E 1GB Non-ECC Unbuffered DDR333/PC2700 DIMM 10K0034-E 1GB DDR266/PC2100 SODIMM 31P9834-E 1GB 200pin DDR SODIMM non ECC 31P9835-E 1GB 200pin DDR SODIMM non ECC 10K0071-E 1GB 184p PC2100 18c ECC SDRAM DIMM, IBM eServer xSeries 205, xSeries 205 (NX80-xxx), 205 8480, 205VL (8480-xxx), IntelliStation E Pro 6216, 6226, Pentium 4 6216-2xx 10K0072-E 1GB 184p PC2100 18c ECC SDRAM DIMMIBM eServer xSeries 205, xSeries 205 (NX80-xxx), 205 8480, 205VL (8480-xxx), IntelliStation E Pro 6216, 6226, Pentium 4 6216-2xx,3xx,4xx, 33L3285-E 1GB 184pin PC2100 ECC REG. SDRAM DIMM. 33L3286-E 1GB 184pin PC2100 ECC REG. SDRAM DIMM. 33L5039-E 1GB PC266 ECC Registered CL2 DIMM (STACKED) 1GB PC266 ECC Registered CL2 DIMM (STACKED) 73P2267-E 1GB Advanced ECC Registered DDR333/PC2700 DIMM 1GB Advanced ECC Registered DDR333/PC2700 DIMM 73P2276-E 1GB Advanced ECC Registered DDR333/PC2700 DIMM 1GB Advanced ECC Registered DDR333/PC2700 DIMM 73P3223-E 1GB PC2-3200 Unbuffered Non-ECC 400MHz, IBM ThinkCentre A51 8122 (DDR2-400MHz), A51 8123 (DDR2-400MHz), A51 8124 (DDR2-400MHz), A51 8129 (DDR2-400MHz) 73P3224-E 1GB PC2-3200 Unbuffered Non-ECC 400MHz, IBM ThinkCentre A51 8122 (DDR2-400MHz), A51 8123 (DDR2-400MHz), A51 8124 (DDR2-400MHz), A51 8129 (DDR2-400MHz) 30R5122-E 1GB Unbuffered Non-ECC DDR2 PC2-4200 533MHz DIMM 73P3215-E 1GB PC2-4200 Unbuffered Non-ECC 533MHz, IBM Lenovo 3000 H100 5310-xxx, 3000 J100 8255, 3000 J100 8256 (DDR2-533MHz), 3000 J100 8456, 3000 J100 8457, 3000 J110 73P3216-E 1GB PC2-4200 Unbuffered Non-ECC 533MHz, IBM Lenovo 3000 H100 5310-xxx, 3000 J100 8255, 3000 J100 8256 (DDR2-533MHz), 3000 J100 8456, 3000 J100 8457, 3000 J110 73P4972-E 1GB PC2-4200 Unbuffered Non-ECC 533MHz, IBM Lenovo 3000 H100 5310-xxx, 3000 J100 8255, 3000 J100 8256 (DDR2-533MHz), 3000 J100 8456, 3000 J100 8457 FRU 30R5122-E 1GB 240-pin PC2-4200 DDR2-533 non-ECC non-Registered DIMM. IBM Lenovo 3000 H100 5310-xxx, 3000 J100 8255, 3000 J100 8256 (DDR2-533MHz), 3000 J100 8456 FRU 40J8873-E 1GB 240-pin PC2-4200 DDR2-533 non-ECC non-Registered DIMM. IBM Lenovo 3000 H100 5310-xxx, 3000 J100 8255, 3000 J100 8256 (DDR2-533MHz), 3000 J100 8456 73P4984-E 1GB PC2-5300 Unbuffered Non-ECC 667MHz 41U2977-E 1GB PC2-6400 Unbuffered Non-ECC 800MHz 73P3844-E 1GB PC2-4200 SODIMM 533MHz, IBM Lenovo 3000 C100 0761, C100 0761-22U, C100 0761-2BU, C100 0761-23U, C100 0761-25U, C100 0761-26U, 3000 K100 0613-xx 73P3845-E 1GB PC2-4200 SODIMM 533MHz, IBM Lenovo 3000 C100 0761, C100 0761-22U, C100 0761-2BU, C100 0761-23U, C100 0761-25U, C100 0761-26U, 3000 K100 0613-xx 40Y7734-E 1GB 200p DDR2-667 PC2-5300 1.8V SODIMM, IBM-Lenovo 3000 C200 8922, 3000 C200 8922-xxx, 3000 G400 2048-xxx, 3000 G410 2049-xxx, 3000 N100 0689, N100 0689-3GU 40Y8403-E 1GB PC2-5300 SODIMM 667MHz, IBM-Lenovo 3000 C200 8922, 3000 C200 8922-xxx, 3000 G400 2048-xxx, 3000 G410 2049-xxx, 3000 N100 0689, N100 0689-3GU 43R1999-E 1GB DDR2 SDRAM Memory Module DDR2-667/PC2-5300 Non-ECC 200-pin 30R5149-E 2GB (2X1GB) Unbuffered ECC DDR2 PC-4200 533MHz Kit 2GB Unbuffered ECC DDR2 PC-4200 533MHz Kit 39M5809-E 2GB (2X1GB) Advanced ECC Registered DDR2 PC2-3200 400MHz Kit 73P2866-E 2GB (2X1GB) Advanced ECC Registered DDR2 PC2-3200 400MHz Kit 73P5121-E 2GB (2X1GB) Registered ECC DDR400/PC3200 VLP DIMM Kit 2GB Registered ECC DDR400/PC3200 VLP DIMM Kit 73P4985-E 2GB PC2-5300 Unbuffered Non-ECC 667MHz 40Y7735 -E 2GB DDR2-5300 DDR2-667 SODIMM 200PIN, IBM-Lenovo 3000 C200 8922, 3000 N200 0687, 3000 N200 0769-xxx, 3000 V200 0764-xxx, 3000 Y200 6469-xxx, 3000 Y300 7759 40Y8404-E 2GB PC2-667 SODIMM 43R2000-E 2GB PC2-5300 DDR2 SDRAM Sodimm Memory 30R5150-E 4GB (2X2GB) ECC 533MHZ KIT 39M5815-E 4GB KIT (2X2GB) PC2-3200 REGISTERED ECC DIMM 39M5814-E 4GB KIT (2X2GB) PC2-3200 REGISTERED ECC DIMM 73P2867-E 4GB (2X2GB) Advanced ECC Registered DDR2 PC2-3200 400MHz Kit 73P4792-E 4GB KIT (2X2GB) PC2-3200 DDR2-400 SINGLE-RANK REGISTERED ECC DIMM 73P4793-E 4GB KIT (2X2GB) PC2-3200 DDR2-400 SINGLE-RANK REGISTERED ECC DIMM 30R5145-E 8GB Kit (2X4GB) PC2-3200 DDR2-400 Dual-Rank Registered ECC DIMM 30R5146-E 8GB (2X4GB) 2 pcs 4GB PC2-3200 DDR2-400 Dual-Rank Registered ECC DIMM 41Y2768-E 8GB (2X4GB) DDR2 ECC REG 667MHZ DUAL RANK KIT 46C7538-E 8GB (2X4GB) DDR2 ECC REG 667MHZ DUAL RANK KIT 33L5040-E 2GB (1X2GB) 1pcs 2GB 184pin PC2100 Registered 2.5V DDR DIMM, IBM BladeCenter HS20 (Type 8678), eServer xSeries 225 (8649-xxx), 235 (NX71xxx), 225 SMP (8647) 09N4309-E 4GB (2X2GB) 2pcs 2GB 184pin PC2100 Registered 2.5V DDR DIMM, IBM BladeCenter HS20 (Type 8678), eServer xSeries 225 (8649-xxx), 235 (NX71xxx), 225 SMP (8647) 41P0252-E 4GB (2X2GB) 2pcs 2GB 184pin PC2100 Registered 2.5V DDR DIMM, IBM BladeCenter HS20 (Type 8678), eServer xSeries 225 (8649-xxx), 235 (NX71xxx), 225 SMP (8647) 73P4129-E 4GB (2X2GB) 2pcs 2GB 184pin PC2100 Registered 2.5V DDR DIMM. IBM BladeCenter HS20 (Type 8678), eServer xSeries 225 (8649-xxx), 235 (NX71xxx), 225 SMP (8647) 73P2269-E 2GB Advanced ECC Registered DDR333/PC2700 DIMM 2GB Advanced ECC Registered DDR333/PC2700 DIMM 73P5122-E 4GB (2X2GB) PC3200 Registered ECC VLP 400MHz, Registered ECC DDR400/PC3200 VLP DIMM Kit 4GB Registered ECC DDR400/PC3200 VLP DIMM Kit 73P3221-E 512MB 240-pin PC2-3200 non-ECC DDR2-400 DIMM. IBM ThinkCentre A51 8122 (DDR2-400MHz), A51 8123 (DDR2-400MHz), A51 8124 (DDR2-400MHz), A51 8129 (DDR2-400MHz) 73P3222-E 512MB 240-pin PC2-3200 non-ECC DDR2-400 DIMM. IBM ThinkCentre A51 8122 (DDR2-400MHz), A51 8123 (DDR2-400MHz), A51 8124 (DDR2-400MHz), A51 8129 (DDR2-400MHz) 30R5121-E 512MB Unbuffered Non-ECC DDR2 PC2-4200 533MHz 73P3213-E 512MB Unbuffered Non-ECC DDR2 PC2-4200 533MHz 73P3214-E 512MB 240-pin PC2-4200 DDR2-533 non-ECC non-Registered DIMM. IBM Lenovo 3000 H100 5310-xxx, 3000 J100 8255, 3000 J100 8256 (DDR2-533MHz), 3000 J100 8456 73P4971-E 512MB Unbuffered Non-ECC DDR2 PC2-4200 533MHz 73P3842-E 512MB DDR2-533 SODIMM. IBM Lenovo 3000 C100 0761, C100 0761-22U, C100 0761-2BU, C100 0761-23U, C100 0761-25U, C100 0761-26U, 3000 K100 0613-xx 73P3843-E 512MB DDR2-533 SODIMM. IBM Lenovo 3000 C100 0761, C100 0761-22U, C100 0761-2BU, C100 0761-23U, C100 0761-25U, C100 0761-26U, 3000 K100 0613-xx 30R5148-E 512MB Unbuffered ECC DDR2 533MHz PC2-4200 36P3348-E 512MB Unbuffered ECC DDR2 533MHz PC2-4200 DIMM 512MB Unbuffered ECC DDR2 533MHz PC2-4200 DIMM 73P2865-E 1GB (2X512MB) Advanced ECC Registered DDR2 PC2-3200 400MHz Kit 1GB Advanced ECC Registered DDR2 PC2-3200 400MHz Kit 73P3522-E 1GB (2X512MB) Advanced ECC Registered DDR2 PC2-3200 400MHz Kit 1GB Advanced ECC Registered DDR2 PC2-3200 400MHz Kit 43R2037-E 8GB DDR3 ECC REG 1333MHZ QUAD RANK DIMM 44T1579-E 8GB PC3-1066 ECC REG VLP 44T1578-E 8GB DDR3 ECC REG 1066MHZ VLP 46C7499-E 8GB DDR3 ECC REG 1333MHZ DIMM 49Y1436-E 8GB DDR3 ECC REG 1333MHZ DIMM 46C7449-E 8GB DDR3 ECC REG 1333MHZ DIMM 43R1987-E 1GB 204pin PC3-8500 DDR3-1066 SODIMM 57Y4390-E 2GB DDR3 1333MHZ UDIMM 64Y6649-E 2GB DDR3 1333MHZ UDIMM 43R1988-E 2GB DDR3-1066 SODIMM Module 55Y3710-E 2GB DDR3 1333MHZ SODIMM 55Y3716-E 2GB DDR3 1333MHZ SODIMM 64Y6651-E 2GB DDR3 1333MHZ SODIMM 41U5252-E 2GB ECC Module DDR3-1066 unbuffered ECC 13N1524-E 256MB 100pin PC2100 DDR SODIMM 73P2685-E 256MB Unbuffered Non-ECC DDR400/PC3200 DIMM 89Y9224-E 4GB PC3-1333MHZ UNBUFFERED NON-ECC UDIMM 0A36527-E 4GB PC3-1333MHZ UNBUFFERED NON-ECC UDIMM 55Y3711-E 4GB DDR3 1333MHZ SODIMM 55Y3717-E 4GB DDR3 1333MHZ SODIMM 64Y6652-E 4GB DDR3 1333MHZ SODIMM 43R2036-E 4GB DDR3 ECC REG 1066MHZ DIMM 46C7444-E 4GB DDR3 ECC REG 1066MHZ DIMM 46C7448-E 4GB DDR3 ECC REG 1066MHZ DIMM 44T1488-E 4GB DDR3 ECC REG 1333MHZ VLP 44T1478-E 4GB DDR3 ECC REG 1333MHZ VLP 44T1498-E 4GB DDR3 ECC REG 1333MHZ VLP 46C0591-E 4GB DDR3 ECC REG 1333MHZ VLP 33L3306-E 512MB Unbuffered DDR226/PC2100 DIMM, IBM NetVista 2289, 6290, 6824, 6826, 8305, 8317, 8318, 8319, A30 6824-xxx, A30 8313 (5BU, 5CU, 52U, 53U, 55U), A30 8315 (5BU, 5CU 33L3307-E 512MB IBM NetVista 2289, 6290, 6824, 6826, 8305, 8317, 8318, 8319, A30 6824-xxx, A30 8313 (5BU, 5CU, 52U, 53U, 55U), A30 8315 (5BU, 5CU, 5DU, 11U, 12U, 24U, 37U, 39U 31P8856-E 512MB 184p PC2700 CL2.5 DDR DIMM. IBM NetVista 8181, 8182, 8301, 8303, 8304, 8306, 8307, 8308, 8309, 8310, 8311, 8312, A30 6826-xxx, A30 8313-xxx, 8314-xxx, 8315-xxx 31P9122-E 512MB 184p PC2700 CL2.5 DDR DIMM.
Load more

Recommended publications
  • DDR and DDR2 SDRAM Controller Compiler User Guide
    DDR and DDR2 SDRAM Controller Compiler User Guide 101 Innovation Drive Software Version: 9.0 San Jose, CA 95134 Document Date: March 2009 www.altera.com Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending ap- plications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. UG-DDRSDRAM-10.0 Contents Chapter 1. About This Compiler Release Information . 1–1 Device Family Support . 1–1 Features . 1–2 General Description . 1–2 Performance and Resource Utilization . 1–4 Installation and Licensing . 1–5 OpenCore Plus Evaluation . 1–6 Chapter 2. Getting Started Design Flow . 2–1 SOPC Builder Design Flow . 2–1 DDR & DDR2 SDRAM Controller Walkthrough .
    [Show full text]
  • Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines, External
    5. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines June 2012 EMI_DG_005-4.1 EMI_DG_005-4.1 This chapter describes guidelines for implementing dual unbuffered DIMM (UDIMM) DDR2 and DDR3 SDRAM interfaces. This chapter discusses the impact on signal integrity of the data signal with the following conditions in a dual-DIMM configuration: ■ Populating just one slot versus populating both slots ■ Populating slot 1 versus slot 2 when only one DIMM is used ■ On-die termination (ODT) setting of 75 Ω versus an ODT setting of 150 Ω f For detailed information about a single-DIMM DDR2 SDRAM interface, refer to the DDR2 and DDR3 SDRAM Board Design Guidelines chapter. DDR2 SDRAM This section describes guidelines for implementing a dual slot unbuffered DDR2 SDRAM interface, operating at up to 400-MHz and 800-Mbps data rates. Figure 5–1 shows a typical DQS, DQ, and DM signal topology for a dual-DIMM interface configuration using the ODT feature of the DDR2 SDRAM components. Figure 5–1. Dual-DIMM DDR2 SDRAM Interface Configuration (1) VTT Ω RT = 54 DDR2 SDRAM DIMMs (Receiver) Board Trace FPGA Slot 1 Slot 2 (Driver) Board Trace Board Trace Note to Figure 5–1: (1) The parallel termination resistor RT = 54 Ω to VTT at the FPGA end of the line is optional for devices that support dynamic on-chip termination (OCT). © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries.
    [Show full text]
  • 64M X 16 Bit DDRII Synchronous DRAM (SDRAM) Advance (Rev
    AS4C64M16D2A-25BAN Revision History 1Gb Auto-AS4C64M16D2A - 84 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Jan 2018 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 62 - Rev.1.0 Jan. 2018 AS4C64M16D2A-25BAN 64M x 16 bit DDRII Synchronous DRAM (SDRAM) Advance (Rev. 1.0, Jan. /2018) Features Overview JEDEC Standard Compliant The AS4C64M16D2A is a high-speed CMOS Double- AEC-Q100 Compliant Data-Rate-Two (DDR2), synchronous dynamic random- JEDEC standard 1.8V I/O (SSTL_18-compatible) access memory (SDRAM) containing 1024 Mbits in a 16-bit wide data I/Os. It is internally configured as a 8- Power supplies: V & V = +1.8V 0.1V DD DDQ bank DRAM, 8 banks x 8Mb addresses x 16 I/Os. The Operating temperature: TC = -40~105°C (Automotive) device is designed to comply with DDR2 DRAM key Supports JEDEC clock jitter specification features such as posted CAS# with additive latency, Fully synchronous operation Write latency = Read latency -1, Off-Chip Driver (OCD) Fast clock rate: 400 MHz impedance adjustment, and On Die Termination(ODT). Differential Clock, CK & CK# All of the control and address inputs are synchronized Bidirectional single/differential data strobe with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK - DQS & DQS# rising and CK# falling) All I/Os are synchronized with a 8 internal banks for concurrent operation pair of bidirectional strobes (DQS and DQS#) in a source 4-bit prefetch architecture synchronous fashion.
    [Show full text]
  • DDR2 SDRAM SO-DIMM MODULE, 1.8V 512Mbyte - 64MX64 AVK6464U51E5667F0
    DDR2 SDRAM SO-DIMM MODULE, 1.8V 512MByte - 64MX64 AVK6464U51E5667F0 FEATURES JEDEC Standard DDR2 PC2-5300 667MHz - Clock frequency: 333MHz with CAS latency 5 - 256 byte serial EEPROM - Data input and output masking - Programmable burst length: 2, 4, 8 - Programmable burst type: sequential and interleave - Programmable CAS latency: 5 - Auto refresh and self refresh capability - Gold card edge fingers - 8K refresh per 64ms - Low active and standby current consumption - SSTL-2 compatible inputs and outputs - Decoupling capacitors at each memory device - Double-sided module - 1.18 inch height DESCRIPTION The AVK6464U51E5667F0 family consists of Unbuffered DDR2 SDRAM SODIMM memory module. This module is JEDEC-standard 200-pin, small-outline, dual in-line memory module. A 256 byte serial EEPROM on board can be used to store module information such as timing, configuration, density, etc. The AVK6464U51E5667F0 memory module is 512MByte and organized as a 64MX64 array using (8) 32MX16 (4 internal banks) DDR2 SDRAMs in BGA packages. All memory modules are fabricated using the latest technology design, six-layer printed circuit board substrate construction with low ESR decoupling capacitors on-board for high reliability and low noise. PHYSICAL DIMENSIONS 2.661 0.040 256MBit 256MBit 256MBit 256MBit 1.18 32MX8 DDR2 32MX8 DDR2 32MX8 DDR2 32MX8 DDR2 BGA SDRAM BGA SDRAM BGA SDRAM BGA SDRAM 512MBit (8MX16X4) 512MBit (8MX16X4) S 512MBit (8MX16X4) 512MBit (8MX16X4) P 32MX16 DDR2 BGA SDRAM 32MX16 DDR2 BGA SDRAM D 32MX16 DDR2 BGA SDRAM 32MX16 DDR2 BGA SDRAM 0.787 1 199 0.140 All gray ICs are on the top, and all white ICs are on the back side of the modude The SPD EEPROM is populated on the back side of the module BGA Package Avant™ Technology LP.
    [Show full text]
  • Memory Controller SC White Paper
    DEVELOPING HIGH-SPEED MEMORY INTERFACES: THE LatticeSCM FPGA ADVANTAGE A Lattice Semiconductor White Paper February 2006 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com Developing High-Speed Memory Interfaces A Lattice Semiconductor White Paper Introduction A common problem for today’s system designers is to reliably interface to their next generation high- speed memory devices. As system bandwidths continue to increase, memory technologies have been optimized for higher speeds and performance. As a result, these next generation memory interfaces are also increasingly challenging to design to. Implementing high-speed, high-efficiency memory interfaces in programmable logic devices such as FPGAs has always been a major challenge for designers. Lattice Semiconductor offers customers a high performance FPGA platform in the LatticeSC to design high-speed memory interface solutions. The LatticeSC family implements various features on- chip that facilitate designing high-speed memory controllers to interface to the next generation high- speed, high performance DDR SDRAM, QDR SRAM, and emerging RLDRAM memory devices. The PURESPEED I/O structures on the LatticeSC, combined with the clock management resources and a high-speed FPGA fabric help customers reduce design risk and time-to-market for high-speed memory based designs. Additionally, the LatticeSCM family implements full-featured embedded high-speed memory controllers on-chip to interface smoothly to the next generation high-speed, high performance DDR I/II SDRAM, QDR II SRAM, and RLDRAM I/II memory devices. The embedded memory controllers, coupled with the I/O structures and clock management resources, are fully verified controllers for customers to use as off-the-shelf solutions.
    [Show full text]
  • 2048Mb Ddr2 Dimm
    Apacer Memory Product Specification 2048MB DDR2 DIMM 2GB DDR2 DIMM based on 128MX8 ,8Banks, 1.8V DDR2 DIMM with SPD Features ‧Performance range ( Bandwidth: 5.3 GB/sec ) Part Number Max Freq. (Clock) Speed Grade 78.A1G9O.404 333MHz(3ns@CL5) 667Mbps ‧JEDECstandard 1.8V ± 0.1V Power Supply ‧VDDQ = 1.8V± 0.1V ‧Internal Bank: 8 Bank ‧Posted CAS ‧Programmable CAS Latency: 4, 5, 6 ‧Programmable Additive Latency: 0, 1 , 2 , 3 and 4 ‧Write Latency(WL) = Read Latency(RL) -1 ‧Burst Length: 4 , 8(Interleave/nibble sequential) ‧Programmable Sequential / Interleave Burst Mode ‧Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) ‧Off-Chip Driver(OCD) Impedance Adjustment ‧On Die Termination ‧Refresh and Self Refresh Average Refesh Period 7.8us ‧Serial presence detect with EEPROM ‧Compliance with RoHS ‧Compliance with CE ‧Operating Temperature Rang: ‧Commercial 0°C ≦ TC ≦ 85°C ‧Refresh: auto-refresh, self-refresh ‧─Average refresh period 7.8us at 0°C ≦ TC ≦ 85°C 3.9us at 85°C ≦ TC ≦ 95°C Pin Description Pin Name Description Pin Name Description A0-A13 DDR2 SDRAM address bus CK0, CK1, CK2 DDR2 SDRAM clocks (positive line of differential pair) BA0-BA2 DDR2 SDRAM bank select CK0, CK1, CK2 DDR2 SDRAM clocks (negative line of differential pair) RAS DDR2 SDRAM row address strobe SCL I2C serial bus clock for EEPROM CAS DDR2 SDRAM column address strobe SDA I2C serial bus data line for EEPROM WE DDR2 SDRAM wirte enable SA0-SA2 I2C serial address select for EEPROM S0, S1 DIMM Rank Select Lines VDD* DDR2 SDRAM core power supply
    [Show full text]
  • Swissbit SMT Memory Product Guide Rev1.9.Pub
    SWISSMEMORY™ Industrial Product Line DRAM Memory Products Solutions for Industrial and Embedded Applications Surface Mount Technology (SMT) DDR3 DDR2 DDR SDRAM DRAM Visit us at www.swissbit.com Version 1.9 - 01/2009 DDR3 SDRAM TECHNOLOGY SDRAM DDR3 modules are Swissbit’s most recent Double Data Rate products to market. DDR3 is the memory choice for performance driven systems with clock frequencies of 400 to 800MHz and data rates of 800 to 1600 Mb per second. In addition to DDR3’s improved performance in dual- and multi-core systems, it also provides increased efficiency with lower power consumption. DDR3 power consumption is approximately 20% or more lower than its predecessor at 1.35V to 1.5V as compared to the 1.8V of DDR2. Swissbit offers DDR3’s unmatched combination of high bandwidth and density with lower power consumption in the variety of module packages. Density Swissbit PN Data Rate (MT/s) - CL Height # IC’s IC Org Rank DDR3 SDRAM UDIMM (240 pin) 512MB (64Mx64) SGU06464C1CB1xx-ssR 800-CL5 / 1066-CL7 / 1333-CL9 1.18" (29.97mm) 4 64Mx16 1 1GB (128Mx64) SGU12864D1BB1xx-ssR 800-CL5 / 1066-CL7 / 1333-CL9 1.18" (29.97mm) 8 128Mx8 1 2GB (256Mx64) SGU25664E1BB2xx-ssR 800-CL5 / 1066-CL7 / 1333-CL9 1.18" (29.97mm) 16 128Mx8 2 DDR3 SDRAM UDIMM w/ ECC (240 pin) 512MB (64Mx72) SGU06472H1CB1xx-ssR 800-CL5 / 1066-CL7 / 1333-CL9 1.18" (29.97mm) 5 64Mx16 1 1GB (128Mx72) SGU12872F1BB1xx-ssR 800-CL5 / 1066-CL7 / 1333-CL9 1.18" (29.97mm) 9 128Mx8 1 2GB (256Mx72) SGU25672G1BB2xx-ssR 800-CL5 / 1066-CL7 / 1333-CL9 1.18" (29.97mm) 18 128Mx8 2 DDR3 SDRAM
    [Show full text]
  • SDRAM Memory Systems: Architecture Overview and Design Verification SDRAM Memory Systems: Architecture Overview and Design Verification Primer
    Primer SDRAM Memory Systems: Architecture Overview and Design Verification SDRAM Memory Systems: Architecture Overview and Design Verification Primer Table of Contents Introduction . 3 - 4 DRAM Trends . .3 DRAM . 4 - 6 SDRAM . 6 - 9 DDR SDRAM . .6 DDR2 SDRAM . .7 DDR3 SDRAM . .8 DDR4 SDRAM . .9 GDDR and LPDDR . .9 DIMMs . 9 - 13 DIMM Physical Size . 9 DIMM Data Width . 9 DIMM Rank . .10 DIMM Memory Size & Speed . .10 DIMM Architecture . .10 Serial Presence Detect . .12 Memory System Design . .13 - 15 Design Simulation . .13 Design Verification . .13 Verification Strategy . .13 SDRAM Verification . .14 Glossary . .16 - 19 2 www.tektronix.com/memory SDRAM Memory Systems: Architecture Overview and Design Verification Primer Introduction Memory needs to be compatible with a wide variety of memory controller hubs used by the computer DRAM (Dynamic Random Access Memory) is attractive to manufacturers. designers because it provides a broad range of performance Memory needs to work when a mixture of different and is used in a wide variety of memory system designs for manufacturer’s memories is used in the same memory computers and embedded systems. This DRAM memory system of the computer. primer provides an overview of DRAM concepts, presents potential future DRAM developments and offers an overview Open memory standards are useful in helping to ensure for memory design improvement through verification. memory compatibility. DRAM Trends On the other hand, embedded systems typically use a fixed There is a continual demand for computer memories to be memory configuration, meaning the user does not modify larger, faster, lower powered and physically smaller. These the memory system after purchasing the product.
    [Show full text]
  • Main Memory Memory Organisation & Memory Signals Physical Structure
    Main Memory Refers to physical memory that is internal to the computer. The word main is used to distinguish it from external mass storage devices such as disk drives. Another term for main memory is RAM. The computer can manipulate only data that is in main memory. Therefore, every program you execute and every file you access must be copied from a storage device into main memory. The amount of main memory on a computer is crucial because it determines how many programs can be executed at one time and how much data can be readily available to a program. Because computers often have too little main memory to hold all the data they need, computer engineers invented a technique called swapping, in which portions of data are copied into main memory as they are needed. Swapping occurs when there is no room in memory for needed data. When one portion of data is copied into memory, an equal-sized portion is copied (swapped) out to make room. Now, most PCs come with a minimum of 32 megabytes of main memory. You can usually increase the amount of memory by inserting extra memory in the form of chips. Memory Organisation & Memory Signals Physical Structure of IC Memory Package & Memory Modules such as SIMM & DIMM. Also their layout Memory module is a broad term used to refer to a series of dynamic random access memory integrated circuits modules mounted on a printed circuit board and designed for use in personal computers, workstations and servers. SIMM A SIMM, or single in-line memory module, is a type of memory module containing random access memory used in computers from the early 1980s to the late 1990s.
    [Show full text]
  • Development of DDR2 SDRAM Module Interface Software Core
    Prajakta Chandilkar. Int. Journal of Engineering Research and Application www.ijera.com ISSN : 2248-9622, Vol. 7, Issue 9, ( Part -2) September 2017, pp.28-32 RESEARCH ARTICLE OPEN ACCESS Development of DDR2 SDRAM Module Interface Software Core Prajakta Chandilkar*, Dr. Uday Wali** *(M.tech Student Electronics and Communication, KLE Dr. M.S. Sheshgiri College of Engineering and Technology, Belagavi, Karnataka, India ,[email protected] **(Professor, Dept. of Electronics and Communication, KLE Dr. M.S .Sheshgiri College of Engineering and Technology, Belagavi, Karnataka, India, [email protected]) ABSTRACT Memory module simulation is critical to testing of embedded systems. Hardware software co-design strategy requires that clock accurate system modules be available in software. DDR2 SDRAM is one of the popular memory modules used in embedded systems. Memory modules have their own built in controllers to interpret and execute commands from the processor. This paper describes an implementation of the finite state machine (FSM) of a DDR2 SDRAM module. The module can be used as a basis for hardware design of memory modules. It can also be used as a part of hardware-software co-design tool for embedded systems using DDR2 memory modules. The technology independent FSM is implemented in Verilog HDL. Keywords Command sets, DDR, DDR2 SDRAM, Hardware-Software co-design, Verilog ----------------------------------------------------------------------------------------------------------------------------- ---------- Date of Submission: 29-08-2017 Date of acceptance: 09-09-2017 ----------------------------------------------------------------------------------------------------------------------------- ---------- modify an existing interface hardware to match any I. INTRODUCTION other member of the DDR family. Developments in VLSI technology are driven by the never ending demand for faster processors. Faster processors need faster memory.
    [Show full text]
  • Tn4719 Form Function Ddr2.Pdf
    TN-47-19: DDR2 (Point-to-Point) Features and Functionality Introduction Technical Note DDR2 (Point-to-Point) Features and Functionality Introduction Point-to-point design layouts have unique memory requirements and selecting the right memory can be critical to project success. With many point-to-point designs, memory accounts for only a small percentage of the overall chip count. Other point-to-point designs are complex and may incorporate specialized processors, large pin-count custom ASICs, sophisticated analog circuitry, and thick, multilayered printed circuit boards. Still others may even use the memory on a common node—where memory is shared and independently accessed by different devices. DRAM has been used extensively on modules and consumed in the personal computer industry where the user can plug and play. For this to happen, the DRAM must be generic and only the minimum functionality is needed. However, DDR2 SDRAM memory has changed this legendary tradition. Unlike previous DRAM, DDR2 SDRAM is designed to provide the point-to-point system designer with versatile options. These options not only enable robust designs, they may also help reduce the overall design time and system cost. DDR2 SDRAM offers several options: • Maximum bandwidth up to 800 MT/s (mega transfers per second) • Supports operations down to 125 MHz clock for debugging and low-power applica- tions • Adjustable on-die termination (ODT) for I/O that promotes high-quality signal integ- rity without additional on-board termination • Signal reflections controlled through selectable output drive levels. Unlike DDR, DDR2 supports this feature on x4, x8, and x16 devices • Small FBGA package sizes, enabling the placement of high-density devices in extremely compact footprints A side-by-side comparison of DDR2 with SDR and DDR reveals how DDR2 facilitates these capabilities (see Figure 1 on page 2).
    [Show full text]
  • New Features of DDR3 SDRAM
    USER'S MANUAL New Features of DDR3 SDRAM Document No. E1503E10 (Ver.1.0) Date Published March 2009 (K) Japan URL: http://www.elpida.com © Elpida Memory, Inc. 2009 User's Manual E1503E10 (Ver.1.0) 2 Descriptions in this document are provided only for illustrative purpose in semiconductor product operation and application examples. Use these information under the full responsibility of the customer. For details about the functions of individual products, refer to the corresponding data sheet. INTRODUCTION Readers This manual is intended for users who design application systems using double data rate 3 synchronous DRAM (DDR3 SDRAM). Readers of this manual are required to have general knowledge in the fields of electrical engineering, logic circuits, as well as detailed knowledge of the functions and usage of conventional synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), and double data rate 2 synchronous DRAM (DDR2 SDRAM). Explanatory Notes Caution: Information requiring particular attention Note: Footnote for items marked with Note in the text Remarks: Supplementary information Related Documents Related documents indicated in this manual may include preliminary versions, but they may not be explicitly marked as preliminary. Document Name Document No. HOW TO USE SDRAM USER'S MANUAL E0123N HOW TO USE DDR SDRAM USER'S MANUAL E0234E HOW TO USE DDR2 SDRAM USER'S MANUAL E0437E Notice This document is intended to give users understanding of basic functions and usage of DDR3 SDRAM. Descriptions in this document are provided only for illustrative purpose in semiconductor product operation and application examples. And numerical values are not guaranteed values.
    [Show full text]