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Gpio Design, Layout, Simulation and Esd Clamp

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Gpio Design, Layout, Simulation and Esd Clamp GPIO DESIGN, LAYOUT, SIMULATION AND ESD CLAMP PLACEMENT CALCULATOR by Shiju Abraham Presented to the Faculty of the Graduate School of The University of Texas at Arlington in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING THE UNIVERSITY OF TEXAS AT ARLINGTON August 2014 Copyright © by Shiju Abraham 2014 All Rights Reserved ii Acknowledgements I would like to thank the Lord Almighty for giving me the opportunity to do MS by Thesis and a co-op with GLOBALFOUNDRIES. I thank God for giving me the ability, patience, perseverance and good health to get this work done. I would like to acknowledge the support and guidance from my advisor Dr. W. Alan Davis. He has been patient and given continuous feedback on my work. It was a privilege to work under his supervision. I express my immense gratitude to Dr. Davis. I would like to thank Dr. Jonathan Bredow and Dr. Kambiz Alavi for being members of my thesis committee and giving me valuable feedback. I thank office assistants (Ms. Ann, Ms. Janice, and Ms. Pauline) of the EE department at UT Arlington. I thank Dr. Mahadeva Iyer Natarajan (Natarajan), Mr. Anil Kumar, Mr. Manjunatha Prabhu and Mr. Chien-Hsin Lee (Ano) for the constant guidance and support they provided while I did my co-op with GLOBALFOUNDRIES and worked on a similar topic. They have been patient and attentive throughout the co-op and reviewed my work at each phase. Finally and most importantly, the thesis would not have been possible without the love and support of my parents (Mr. P.A. Abraham, Ms. P.M. Mariamma), other immediate family members and friends (Mr. Sujith S. Dermal, Ms. Stella Kurian, Ms. Mitha Ann Philip). I thank them from the bottom of my heart for the encouragement and support they provided. June 30, 2014 iii Abstract GPIO DESIGN, LAYOUT, SIMULATION AND ESD CLAMP PLACEMENT CALCULATOR Shiju Abraham, M.S. The University of Texas at Arlington, 2014 Supervising Professor: Dr. W. Alan Davis Input/Output (IO) circuits enable interface between logic circuitry and the actual or raw information to be processed. They also help to isolate the integrated circuit from the unsafe, unknown and noisy environment. IOs come in many flavors and the General Purpose IO (GPIO) is one among them. GPIOs can operate as an input, output or a bi-directional circuit. The purpose of this work is to design an area optimized industrial quality bi-directional GPIO with separate enable signal for transmitter and receiver which can drive a current of at least 16 mA into the PAD (the circuit point where the capacitive load is connected). The typical IO power level (the power at which a Printed Circuit Board, PCB operates) is 1.8 V and the core (the logic circuitry) power level is 1.0 V. Drive strength control and slew rate control are included in the GPIO implementation. Since many GPIOs could be placed in an IO ring (IOs placed around the periphery of the chip), its placement optimization is important for optimal chip area, as well as, robust IO ring from performance and qualification requirements. IOs need to be protected from ESD events. One of the key ESD protection methodologies involve accurate ESD device sizing versus ESD current path distance optimization. A calculator is developed to predict the optimum distance at which a power clamp should be present for a given IO ESD device size and overall current carrying element iv availability. This tool is supposed to get certain inputs regarding the ESD protection devices from the user and suggest an optimum distance at which a power clamp should be placed in an IO ring. This work is intended to produce one of the most compact GPIOs in the given technology node (the distance between source and drain of the CMOS transistor), 28 nm and a clamp placement calculator which works for different technology nodes. v Table of Contents Acknowledgements ....................................................................................................................... iii Abstract ......................................................................................................................................... iv List of Illustrations .......................................................................................................................... ix List of Tables ................................................................................................................................ xii Chapter 1 Introduction to IOs ........................................................................................................ 1 1.1 Signaling Standards ............................................................................................................ 3 1.2 Types of IOs ........................................................................................................................ 5 1.2.1 Input Buffer ................................................................................................................... 6 1.2.2 Output Buffer ................................................................................................................ 6 1.2.3 Bi-directional Buffer ...................................................................................................... 7 1.2.4 Open-drain ................................................................................................................... 8 1.2.5 LVDS ............................................................................................................................ 9 1.3 Physical Arrangement of IOs .............................................................................................. 9 1.4 Performance Metrics for IOs ............................................................................................. 13 1.5 Schematic, Layout, Simulation Standards ........................................................................ 16 Chapter 2 GPIO Development .................................................................................................... 22 2.1 Specification ...................................................................................................................... 22 2.2 General Block Diagram of a Bi-directional GPIO .............................................................. 24 2.3 Design ............................................................................................................................... 25 2.3.1 Design of P-driver and N-driver: ................................................................................. 27 2.3.2 Design of Pre-driver: .................................................................................................. 30 2.3.3 Design of Tri-state Machine: ...................................................................................... 31 2.3.4 Design of a Level-shifter:............................................................................................ 35 2.3.5 Design of Receiver: .................................................................................................... 36 vi 2.4 Layout ................................................................................................................................ 37 2.5 Simulation .......................................................................................................................... 39 Chapter 3 Introduction to Electro Static Discharge (ESD) in ICs ................................................ 41 3.1 ESD Test Models .............................................................................................................. 42 3.1.1 Human Body Model (HBM) ........................................................................................ 43 3.1.2 Machine Model (MM) .................................................................................................. 44 3.1.3 Charged Device Model (CDM) ................................................................................... 45 3.2 ESD Protection Schemes .................................................................................................. 47 3.2.1 Turn-on Type Device .................................................................................................. 47 3.2.2 Snapback Type Device .............................................................................................. 49 3.2.3 ESD Protection Circuit ................................................................................................ 49 3.3 Power Clamp ..................................................................................................................... 51 Chapter 4 ESD Network Analysis ............................................................................................... 52 Chapter 5 The “IO Planner” Tool ................................................................................................. 55 5.1 Resistance Calculation of the VDDIO Power Route [Macro Name: vddResCalc] ............ 58 5.2 Resistance Calculation of VSS Power Route [Macro Name: vssResCalc] ....................... 61 5.3 Resistance Calculation of Diode to Supply Route [Macro Name: diodeSupplyResCalc] . 61 5.4 Resistance Calculation of PAD to Diode Route [Macro Name: padDiodeResCalc] ......... 61 5.5 Resistance Calculation of HBM Up-diode [Macro Name: hbmUpDiodeResCalc] ............ 62 5.6 Resistance Calculation of HBM Down-diode [Macro Name: hbmDownDiodeResCalc] ... 63 5.7 Resistance Calculation of CDM Up-diode [Macro Name: cdmUpDiodeResCalc] ............ 63 5.8 Resistance Calculation of CDM Down-diode
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