Characterization of Degradation and Failure Phenomena in MOS Devices
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Research Collection Doctoral Thesis Characterization of degradation and failure phenomena in MOS devices Author(s): Pfäffli, Paul Publication Date: 1999 Permanent Link: https://doi.org/10.3929/ethz-a-003825871 Rights / License: In Copyright - Non-Commercial Use Permitted This page was generated automatically upon download from the ETH Zurich Research Collection. For more information please consult the Terms of use. ETH Library Diss. ETHNo. 13274 Characterization of Degradation and Failure Phenomena in MOS Devices A DISSERTATION submitted to the SWISS FEDERAL INSTITUTE OF TECHNOLOGY ZURICH for the degree of Doctor of Technical Sciences presented by PAUL PFÄFFLI dipl. Physiker ETH born 14. April 1970 citizen of Hergiswil LU, Switzerland accepted on the recommendation of Prof. Dr. W. Fichtner, examiner Dr. h.c. José Solo de Zaldivar, co-examiner 1999 Acknowledgements I am particularly indebted to Prof. Dr. W. Fichtner for his support and advice during my stay at the Integrated Systems Laboratory. Without his help during the fourth year of my Ph.D. time, the work would probably not have finished. I am grateful for the generous facilities at the institute, espe¬ cially for its excellent equipment, and for the good organization of the insti¬ tute. Sincere thanks go to Dr. Dölf Aemmer and Dr. Norbert Felber for their help. My thanks go to Dr. h.c. José Solo de Zaldivar for accepting spontane¬ ously to be the co-examiner of this thesis. His interest in my work and the fruitful discussions were encouraging. During the first three years of my work I joined the Reliability Labora¬ tory. I thank Prof. Dr. A. Birolini for his support and help in the reliability part of the work. This thesis is partially the result of the European research projects CARE and SUB SAFE. Without this financial support the work would have been impossible. Finally, I gratefully acknowledge support by all my colleagues at the Reliability Laboratory and at the Integrated Systems Laboratory. Especially, I mention Mauro Ciappa and Paolo Malberti. I thank for their continuous in failure help analysis and reliability. Furthermore, I would like to express my thanks to Dr. Andreas Schenk for theoretical advice and suggestions about interesting measurements. i Contents vu ^us«iîînîciirassuii§ »••*••••••••••••••••»••«•••**•**••***•••• II* JLJ.1LX UU.UL IXU11 ••••••••••••••••••••••••••••••«••••«•«••»»•«•»X 2. Survey of Failure and Degradation Mechanisms 3 Hot Carrier Degradation 4 Dielectric and Junction-Breakdown 6 Electrostatic Discharge (ESD) and Latchup 9 Electro- and Stressmigration 13 Corrosion 15 Interdiffusion of Metals 18 Contamination 19 Radiation 21 Thermo-Mcchanical Problems 22 3. Two Examples of IC Degradation 25 Tddq Measurements of a Ripple Counter 26 Analysis of naturally aged SRAM memories 36 4. Some Measurement Methods and Characteristics of MOS Determination of Transistor Geometry by AFM 42 NMOS Transfer Characteristic, Substrate Currents and GIDL 45 Flat-Band and Threshold Voltage 54 Measurement of Polysilicon Doping and Gate Depletion Effects 56 Fowler-Nordheim Current 59 Determination of the Oxide Thickness 74 The Charge Pumping Technique 77 Definition and Measurement of Mobility .82 5. Generation of Oxide Charges and Interface Traps 91 Injection Mechanisms 92 GIDL-, Gatcd-diodc-, Gate- and Substrate-Currents 93 The structure of the Si-Si02 interface, oxide-trapped charges and interface states .97 Charge Pumping Currents 99 Plot Carrier Stress and Lifetime Estimation 103 Generation of Interface Traps after Fowler-Nordheim Stress 112 iii iv Contents 6. Negative Transconductance of MOS Transistors 115 Decreasing Drain Current at Increasing Gate Voltage 115 Is there a Correlation between the Negative Transconductance and the Fowler-Nordheim Current? 118 Influence of Poly-Gate Depletion 120 Influence of Interface Traps 121 The Role of Surface Roughness Scattering 123 A Simple Mobility Model 124 Classical Calculations 127 Quantization of the Inversion Layer 131 Conclusion 142 List of Symbols and Abbreviations 153 Abstract In this thesis various degradation mechanisms and characterization meth¬ ods were investigated for metal oxide semiconductor (MOS) devices. The work starts with a survey of some important degradation and failure mechanisms. Degradation takes place at the three main levels of each device: First, on transistor level the thin gate oxide (especially its interface to the channel) is the most sensitive part. Generation of interface traps and oxide charges leads to shifts of the electric characteristics (mainly shifts of threshold voltage, transconductance and saturation current). Ionic contami¬ nation of the interface can have similar effects. Then, on the interconnection level between various transistors the thin metallization lines are threatened by corrosion, electro- and Stressmigration and interdiffusion. Finally, on package level thermo-mechanical problems lead to shear stress at interfaces and diffusion through the package results in contamination of the circuit. Degradation on circuit level was studied in two examples: The first was a simple CMOS counter. Here, the power of the Iddq technique for the study of leakage currents due to hot carrier degradation and crystal defects was shown. In the second example old SRAM memories were analyzed. Corro¬ sion and migration problems in the metallization of the circuit were observed. The measurement of input leakage currents and of the standby current is proposed as an efficient reliability test before the reuse of old devices as replacement parts. In chapter 4 some important characterization methods on transistor level were considered. An important point was a deeper understanding of impact ionization: In short channel transistors impact ionization due to hot elec¬ trons occurs at a drain voltage as low as 0.7V. Hence, by a simple reduction of the drain voltage the hot electron problem cannot be resolved. Another important section of this chapter treats Fowler-Nordheim tunneling: The tunneling current was calculated approximately and exactly and current oscillations were measured and compared with the computation. Further¬ more, important measurement techniques such as GIDL, charge pumping or the measurement of the channel effective mobility were reviewed. A focal point of this thesis was the degradation of NMOS transistors. Drain avalanche hot electron and Fowler-Nordheim injection were used to v VI Abstract study the degradation of the interface. The measured positive shift of the threshold voltage was explained by the screening effect of negatively charged acceptor traps. Moreover, it was clearly demonstrated that the deg¬ radation after Fowler-Nordheim stress depends on the direction of the elec¬ tron flow: When electrons tunnel from the gate into the channel, the stress is much more severe than vice versa. This dependence is due to the generation of hot holes at the interface. Additionally, the lifetime of a NMOS transistor with a 0.25pm gate length was estimated with the help of the models of E. Takeda and C. Hu. In the last chapter, the negative transconductance effect in NMOS transis¬ tors was considered: At very high normal fields the drain current decreases with increasing gate voltage. After checking various hypothesis experimen¬ tally, it was concluded that surface roughness scattering is the most probable explanation for the effect. Assuming this type of scattering a simple mobil¬ ity model was constructed, which is able to simulate qualitatively all mea¬ sured effects. The assumptions for the mobility model were justified with classical calculations. Finally, another possible physical argument for the negative transconductance effect was studied: quantization of the inversion channel. Eigenenergies and occupation of the subbands in the inversion channels of NMOS transistors on Si(100) and Si(lll) were calculated by solving Schrödinger's and Poisson's equation selfconsistently. The calcula¬ tion showed the interesting effect that at room temperature and low to medium surface fields the occupation of the first subband is lower than the occupation of the second. At high normal fields and at low temperature the occupation is reversed. Zusammenfassung In der vorliegenden Dissertation wurden verschiedene Degradierungsme- chanismen und Charakterisierungsmethoden von Metall-Oxyd-Halbleiter (MOS) Bauteilen untersucht. Die Arbeit beginnt mit einem Abriss über einige wichtige Degradierungs- und Fehlermechanismen. Die Alterung eines Bauteils setzt auf folgenden drei Hauptebenen ein: Auf Transistorebene ist das dünne Gateoxyd (beson¬ ders die Oxyd-Silizium Grenzfläche) der empfindlichste Teil. Die Erzeu¬ gung von Interfacezuständen und Oxydladungen verändert die elektrischen Eigenschaften des Transistors, insbesondere die Schwellspannung, die Transconductance und den Sättisxmssstrom. Die Kontamination der Grenz- fläche mit Ionen kann zu ähnlichen Effekten führen. Auf der Ebene der Ver¬ bindungen zwischen den Transistoren sind die dünnen Metallbahnen durch Korrosion, Elektro- und Stressmigration sowie durch Interdiffusion bedroht. Auf Gehäuseebene schliesslich können thermo-mechanische Probleme zu Scherspannungen an Grenzflächen führen und Diffusion durch das Gehäu¬ sematerial kann die Schaltung kontaminieren. Auf Schaltungsebene wurde die Degradation an Hand zweier Beispiele studiert. Das erste war ein einfacher CMOS Zähler. An ihm wurde die Lei¬ stungsfähigkeit der Iddq Technik zum Studium von Leckströmen, die durch heisse Ladungsträger oder Kristalldefekte verursacht wurden, aufgezeigt.