Research Collection
Doctoral Thesis
Characterization of degradation and failure phenomena in MOS devices
Author(s): Pfäffli, Paul
Publication Date: 1999
Permanent Link: https://doi.org/10.3929/ethz-a-003825871
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ETH Library Diss. ETHNo. 13274
Characterization of Degradation and Failure Phenomena in MOS Devices
A DISSERTATION
submitted to the
SWISS FEDERAL INSTITUTE OF TECHNOLOGY ZURICH
for the degree of
Doctor of Technical Sciences
presented by
PAUL PFÄFFLI
dipl. Physiker ETH
born 14. April 1970 citizen of Hergiswil LU, Switzerland
accepted on the recommendation of
Prof. Dr. W. Fichtner, examiner Dr. h.c. José Solo de Zaldivar, co-examiner
1999 Acknowledgements
I am particularly indebted to Prof. Dr. W. Fichtner for his support and advice during my stay at the Integrated Systems Laboratory. Without his help during the fourth year of my Ph.D. time, the work would probably not have finished. I am grateful for the generous facilities at the institute, espe¬ cially for its excellent equipment, and for the good organization of the insti¬ tute. Sincere thanks go to Dr. Dölf Aemmer and Dr. Norbert Felber for their help.
My thanks go to Dr. h.c. José Solo de Zaldivar for accepting spontane¬ ously to be the co-examiner of this thesis. His interest in my work and the fruitful discussions were encouraging.
During the first three years of my work I joined the Reliability Labora¬ tory. I thank Prof. Dr. A. Birolini for his support and help in the reliability part of the work.
This thesis is partially the result of the European research projects CARE and SUB SAFE. Without this financial support the work would have been impossible.
Finally, I gratefully acknowledge support by all my colleagues at the Reliability Laboratory and at the Integrated Systems Laboratory. Especially, I mention Mauro Ciappa and Paolo Malberti. I thank for their continuous in failure help analysis and reliability. Furthermore, I would like to express my thanks to Dr. Andreas Schenk for theoretical advice and suggestions about interesting measurements.
i
Contents
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2. Survey of Failure and Degradation Mechanisms 3 Hot Carrier Degradation 4 Dielectric and Junction-Breakdown 6 Electrostatic Discharge (ESD) and Latchup 9 Electro- and Stressmigration 13 Corrosion 15 Interdiffusion of Metals 18 Contamination 19 Radiation 21 Thermo-Mcchanical Problems 22
3. Two Examples of IC Degradation 25 Tddq Measurements of a Ripple Counter 26 Analysis of naturally aged SRAM memories 36
4. Some Measurement Methods and Characteristics of MOS
Determination of Transistor Geometry by AFM 42 NMOS Transfer Characteristic, Substrate Currents and GIDL 45 Flat-Band and Threshold Voltage 54 Measurement of Polysilicon Doping and Gate Depletion Effects 56 Fowler-Nordheim Current 59 Determination of the Oxide Thickness 74 The Charge Pumping Technique 77 Definition and Measurement of Mobility .82
5. Generation of Oxide Charges and Interface Traps 91 Injection Mechanisms 92 GIDL-, Gatcd-diodc-, Gate- and Substrate-Currents 93 The structure of the Si-Si02 interface, oxide-trapped charges and interface states .97 Charge Pumping Currents 99 Plot Carrier Stress and Lifetime Estimation 103 Generation of Interface Traps after Fowler-Nordheim Stress 112
iii iv Contents
6. Negative Transconductance of MOS Transistors 115 Decreasing Drain Current at Increasing Gate Voltage 115 Is there a Correlation between the Negative Transconductance and the Fowler-Nordheim Current? 118 Influence of Poly-Gate Depletion 120 Influence of Interface Traps 121 The Role of Surface Roughness Scattering 123 A Simple Mobility Model 124 Classical Calculations 127 Quantization of the Inversion Layer 131 Conclusion 142
List of Symbols and Abbreviations 153 Abstract
In this thesis various degradation mechanisms and characterization meth¬ ods were investigated for metal oxide semiconductor (MOS) devices.
The work starts with a survey of some important degradation and failure mechanisms. Degradation takes place at the three main levels of each device: First, on transistor level the thin gate oxide (especially its interface to the channel) is the most sensitive part. Generation of interface traps and oxide charges leads to shifts of the electric characteristics (mainly shifts of threshold voltage, transconductance and saturation current). Ionic contami¬ nation of the interface can have similar effects. Then, on the interconnection
level between various transistors the thin metallization lines are threatened
by corrosion, electro- and Stressmigration and interdiffusion. Finally, on package level thermo-mechanical problems lead to shear stress at interfaces and diffusion through the package results in contamination of the circuit.
Degradation on circuit level was studied in two examples: The first was a simple CMOS counter. Here, the power of the Iddq technique for the study of leakage currents due to hot carrier degradation and crystal defects was shown. In the second example old SRAM memories were analyzed. Corro¬ sion and migration problems in the metallization of the circuit were observed. The measurement of input leakage currents and of the standby current is proposed as an efficient reliability test before the reuse of old devices as replacement parts.
In chapter 4 some important characterization methods on transistor level were considered. An important point was a deeper understanding of impact ionization: In short channel transistors impact ionization due to hot elec¬ trons occurs at a drain voltage as low as 0.7V. Hence, by a simple reduction of the drain voltage the hot electron problem cannot be resolved. Another important section of this chapter treats Fowler-Nordheim tunneling: The tunneling current was calculated approximately and exactly and current oscillations were measured and compared with the computation. Further¬ more, important measurement techniques such as GIDL, charge pumping or the measurement of the channel effective mobility were reviewed.
A focal point of this thesis was the degradation of NMOS transistors. Drain avalanche hot electron and Fowler-Nordheim injection were used to
v VI Abstract
study the degradation of the interface. The measured positive shift of the threshold voltage was explained by the screening effect of negatively charged acceptor traps. Moreover, it was clearly demonstrated that the deg¬ radation after Fowler-Nordheim stress depends on the direction of the elec¬ tron flow: When electrons tunnel from the gate into the channel, the stress is much more severe than vice versa. This dependence is due to the generation of hot holes at the interface. Additionally, the lifetime of a NMOS transistor with a 0.25pm gate length was estimated with the help of the models of E. Takeda and C. Hu.
In the last chapter, the negative transconductance effect in NMOS transis¬ tors was considered: At very high normal fields the drain current decreases with increasing gate voltage. After checking various hypothesis experimen¬ tally, it was concluded that surface roughness scattering is the most probable explanation for the effect. Assuming this type of scattering a simple mobil¬ ity model was constructed, which is able to simulate qualitatively all mea¬ sured effects. The assumptions for the mobility model were justified with classical calculations. Finally, another possible physical argument for the negative transconductance effect was studied: quantization of the inversion channel. Eigenenergies and occupation of the subbands in the inversion channels of NMOS transistors on Si(100) and Si(lll) were calculated by solving Schrödinger's and Poisson's equation selfconsistently. The calcula¬ tion showed the interesting effect that at room temperature and low to medium surface fields the occupation of the first subband is lower than the occupation of the second. At high normal fields and at low temperature the occupation is reversed. Zusammenfassung
In der vorliegenden Dissertation wurden verschiedene Degradierungsme- chanismen und Charakterisierungsmethoden von Metall-Oxyd-Halbleiter (MOS) Bauteilen untersucht.
Die Arbeit beginnt mit einem Abriss über einige wichtige Degradierungs- und Fehlermechanismen. Die Alterung eines Bauteils setzt auf folgenden drei Hauptebenen ein: Auf Transistorebene ist das dünne Gateoxyd (beson¬ ders die Oxyd-Silizium Grenzfläche) der empfindlichste Teil. Die Erzeu¬ gung von Interfacezuständen und Oxydladungen verändert die elektrischen Eigenschaften des Transistors, insbesondere die Schwellspannung, die Transconductance und den Sättisxmssstrom. Die Kontamination der Grenz-
fläche mit Ionen kann zu ähnlichen Effekten führen. Auf der Ebene der Ver¬ bindungen zwischen den Transistoren sind die dünnen Metallbahnen durch Korrosion, Elektro- und Stressmigration sowie durch Interdiffusion bedroht.
Auf Gehäuseebene schliesslich können thermo-mechanische Probleme zu
Scherspannungen an Grenzflächen führen und Diffusion durch das Gehäu¬ sematerial kann die Schaltung kontaminieren.
Auf Schaltungsebene wurde die Degradation an Hand zweier Beispiele studiert. Das erste war ein einfacher CMOS Zähler. An ihm wurde die Lei¬ stungsfähigkeit der Iddq Technik zum Studium von Leckströmen, die durch heisse Ladungsträger oder Kristalldefekte verursacht wurden, aufgezeigt. Im zweiten Beispiel wurden natürlich gealterte SRAM Speicherbauteile analysiert. Hier wurden vor allem Korrosions- und Migrationsprobleme festgestellt. Die Messung von Eingangsleckströmen und Standbyströmen erwies sich als ein effizienter Zuverlässigkeitstest zum Beurteilen alter Bau¬ teile vor einer Wiederverwendung als Ersatzteile.
Im vierten Kapitel werden einige wichtige Charakterisierungsmethoden auf Transistorebene betrachtet. Ein wichtiger Punkt wird dort das bessere Verständnis der Stossionisation sein: In Kurzkanaltransistoren tritt Stossio- nisation schon bei einer Drainspannung von 0.7V auf. Durch Verkleinern der Drainspannung kann man also Stossionisation nicht einfach unterdrük- ken. Ein weiterer wichtiger Teil dieses Kapitels behandelt Fowler-Nordheim Tunneln. Exakte und approximative Berechnungen des Tunnelstroms wer¬ den dargestellt, Oszillationen im Tunnelstrom wurden gemessen und mit den Rechnungen verglichen. Schliesslich werden noch einige andere wich-
vu VIII Zusammenfassung tige Messtechniken, z.B. GIDL, charge pumping oder die Messung der effektiven Mobilität beschrieben.
Ein zentraler Punkt in der vorliegenden Dissertation ist die Degradierung von NMOS Transistoren. Zwei Techniken, drain avalanche hot electron stress und Fowler-Nordheim Injektion, wurden eingesetzt, um die Degradie¬ rung der Oxyd-Silizium Grenzfläche zu studieren. Die gemessene Schwell- spannungsverschiebung in positiver Richtung wurde durch die Abschirmung der negativ geladenen Grenzflächenzustände erklärt. Im wei¬ teren konnte klar gezeigt werden, dass die Degradierung durch Fowler- Nordheim Stress von der Richtung des angelegten Feldes abhängt: Wenn die Elektronen vom Gate in den Kanal tunnel n ist die Degradierung viel stärker als wenn sie vom Kanal ins Gate tunneln. Diese Abhängigkeit wurde durch die Erzeugung von heissen Löchern an der Grenzfläche erklärt. Schliesslich wurde in diesem Kapitel noch die Lebensdauer eines NMOS Transistors mit einer Gatelänge von 0.25um mit Hilfe der Modelle von E. Takeda und C. Hu abgeschätzt.
Im letzten Kapitel wird der Effekt negativer Transconductance betrachtet: Bei sehr hohen Feldern (normal zur Oberfläche) nimmt der Drainstrom mit zunehmender Gatespannung ab. Verschiedene Hypothesen zur Erklärung dieses Effekts wurden experimentell überprüft. Eine Oberflächenrauhig¬ keitsstreuung scheint die wahrscheinlichste Erklärung zu sein. Mit dieser Art Streuung wurde ein einfaches Modell für die Mobilität konstruiert, das in der Lage ist qualitativ korrekt die gemessenen Effekte zu simulieren. Klassischen Berechnungen bestätigen die Annahmen für das Modell. Zum Schluss wird noch die Quantisierung der Inversionsschicht als eine andere mögliche Erklärung für den Effekt betrachtet. Die Eigenenergien und die Besetzung der Subbänder von NMOS Transistoren auf Si(lll) und Si(100) wurden durch eine selbstkonsistente Lösung der Schrödinger und Poisson Gleichung berechnet. Die Berechnung zeigte folgenden interessanten Effekt: Bei Raumtemperatur und bei kleinen bis mittleren Feldern ist die Besetzung des ersten Subbandes kleiner als die Besetzung des zweiten. Bei hohen Feldern und bei tiefen Temperaturen ist die Besetzung umgekehrt. 1
Introduction
The research work behind this thesis had three main motivations: First, reliability physics, failure and degradation mechanisms in integrated circuits were investigated. Secondly, various characterization techniques to measure degradation effects in n-channel metal oxide semiconductor transistors (NMOSFETs) were studied and thirdly, the negative transconductance effect in NMOSFETs was measured at various transistor geometries at room and at liquid nitrogen temperature and the physical reason for the effect was investigated.
The reliability part was treated during the European EUREKA research project 'CARE'. The main aspect of the project was the recycling of elec¬ tronic waste with all its environmental consequences. One possible solution is the reuse of the electronic devices, for example as replacement parts for expensive equipment. In this connection, ageing and wearout mechanisms of electronic devices on package, circuit and transistor level were studied and a simple reliability test was found.
In the characterization part of the thesis some main physical effects, such as impact ionization, interface degradation and tunneling through thin oxides, were investigated and various techniques to measure the effects were studied.
In the third part, the physical reason for the negative transconductance effect in NMOS transistors at very high normal fields was measured, a phe- nomenological mobility model which is able to simulate the effect was found and quantum mechanical calculations that allow a deeper physical
1 2 Introduction
understanding of the effect were carried out.
The thesis is organized in the following way: In chapter 2 some important failure and degradation mechanisms are described. In this short survey of the main mechanisms some examples of failures and weak points in various circuits are shown. All pictures were taken by the author during several fail¬ ure analysis studies.
In chapter 3 two examples of circuit degradation are described. In the first example hot carrier degradation in a CMOS counter was characterized by measuring the quiescent power supply current (Iddq). Furthermore, the rea¬ son for some abnormal leakage current behavior was identified: The increased leakage current flowed through a crystal defect in a diffusion area. The second example shows corrosion of the metallization of SRAM memo¬ ries in plastic packages. The memories w;ere used during about 15 years in telephone exchanges. The 448 S RAM's were tested and various failures were found. Weak devices were sorted out and analyzed. The failure cause was identified to be due to the penetration of humidity through the package and a subsequent corrosion of the aluminum metallization. Failed or weak devices always showed increased standby and/or increased input leakage currents. It was found that the measurement of leakage currents (Iddq, standby and input leakage currents) provides a simple and efficient tech¬ nique to check the reliability of a CMOS device without a thorough func¬ tionality test.
The rest of the work was dedicated to the characterization and degrada¬ tion of NMOS transistors. In chapter 4 several techniques are described: It treats the determination of transistor geometry (channel length, oxide thick¬ ness), measurement techniques that are helpful for lifetime estimation (sub¬ strate currents, gate induced drain leakage, charge pumping) and studies quantum effects (Fowler-Nordheim tunneling and current oscillations).
Chapter 5 investigates interface and oxide trap generation after hot elec¬ tron stress and due to tunneling through the gate oxide. Furthermore, the lifetime of a NMOS transistors with a 0.25pm gate length was estimated by state-of-the art techniques.
Finally, in chapter 6 the decrease of the drain current in NMOS transistors at low drain voltages and at very high normal fields was experimentally con¬ firmed. Several hypotheses were experimentally checked and some classical and quantum mechanical calculations were made by means of programs developed during the work. Survey of Failure and Degradation Mechanisms
As everything else in the world, electronic devices feel the time and age during their life. The degradation of the performance is due to two main causes: On the one hand environmental influences (for example tempera¬ ture, humidity, radiation,...) lead to thermomechanical stresses, enable cor¬ rosion of the metallization on the chip or degrade the oxides, on the other hand the normal operation of the device degrades its performance. For example, current flow in the metal wires on chip can lead to electromigra- tion and the formation of shorts and opens may be the consequences. Envi¬ ronmental influences, current flow and strong electric fields lead to degradation on the three main levels of a device: They can weaken its pack¬ age and subsequently endanger the sensitive circuit, they can jeopardize the metallization and they can degrade the quality of the isolating oxides, which shifts the electrical performance or even leads to wearout failures.
A failure occurs when an item stops performing its required function. This can suddenly happen (for example after an electrostatic discharge) or after some degradation time (e.g. a time dependent dielectric breakdown) or can be due to a degradation of some electrical characteristics and lead to a malfunction of the circuit (a shift of the threshold voltage of a transistor, for example).
The failure-free operating time is generally a random variable. Let us assume that n statistically identical, independent items are put into opera¬ tion. It is then classically assumed that the failure rate follows a bathtub curve, that means it follows three main phases: In the first period early fail¬ ures occur due to weaknesses in materials, components or in the production
3 4 Survey of Failure and Degradation Mechanisms
process. During this period the failure rate decreases. Then, a period with nearly constant failure rate follows. The items are then often assumed to be memoryless, that means the probability of a failure of a device in some time interval is thought to be constant and independent of its age. The constant failure rate property is very useful in the mathematical formulation of reli¬ ability, because the reliability function is then exponentially falling in time and therefore, simple expressions for the estimated failure free time of a system can be given.
The aim of the rest of this chapter is to give a short survey of the main degradation and failure mechanisms and to present several examples of weak spots and failures of ICs found by the author during the work.
Hot Carrier Degradation
Hot carrier degradation is one of the main mechanisms in integrated cir¬ cuits that shift the performance of a device and lead to wearout failures. In today's rush to even higher integration densities and smaller dimensions, lower voltages, shallower junctions, thinner oxides, and heavier doping help to maintain long-channel behavior [1]. As the reduction of the supply volt¬ age is typically relaxed in order to preserve the high current gain capability and to guarantee interface and system requirements [2f, however, the elec¬ tric fields in the channel increase, carriers gain higher energies and subse¬ quently, hot carrier effects become increasingly important.
The carriers in the inversion channel of a MOS transistor are distributed in their energies. Electrons or holes in the high-energy tail of the energy dis¬ tribution are called "hot carriers". They were accelerated by the electric field near the reverse biased drain-substrate junction, gained energy and were thereby "heated". Then they can generate electron-hole pairs by impact ion¬ break ization, can bonds at the silicon-oxide interface or find their way into the oxide and produce oxide traps. When the density of traps is high enough, this finally leads to a gate leakage current.
As an example, a NMOS transistor will be considered: In its n-channel electrons are accelerated in the high field region near the reverse biased drain junction. Some electrons gain enough energy to generate an electron- hole pair when they collide with an atom. Some holes break bonds at the Si- Si02 interface generating interface traps. The other holes flow to the sub¬ strate contact causing the substrate current. In transistors with thin gate Hot Carrier Degradation 5
oxides it is also possible that hot electrons have enough energy to overcome the energy barrier at the semiconductor-oxide interface. These electrons cause the gate current. Some of them are trapped in the oxide leading to additional oxide charges. The generation of interface and oxide traps shifts the threshold voltage and degrades the transconductance of the transistor.
As an example of hot electron degradation the increase of the gate induced drain leakage current (at V2S<0V) and the decrease of the saturation current of a NMOS transistor is shown in Fig. 1. This degradation of the device was achieved by stressing the transistor at maximum substrate cur¬ rent at a drain voltage of 4V.
Vgs [V]
Fig. 1 : Degradation of saturation current and drain leakage current after 10 hours of stress at Vds=4V and maximum substrate current (I^=-73f.iA, Vns=1.6V).
Hot carrier degradation remains to be a main research field in reliability physics. Hundreds of papers are published each year on this topic. But mod¬ eling hot-carrier effects in MOSFETs is difficult, because the two main
- physical effects impact ionization and carrier injection into the oxide - require the computation of the entire probability distribution, including the high-energy tail [3f.
Further experiments and results to hot carrier degradation of NMOS tran¬ sistor are described in the chapter "Generation of Oxide Charges and Inter¬ face Traps" on page 91. 6 Surve\ of Failure and Degradation Mechanisms
Dielectric and Junction-Breakdown
Dielectric breakdown is another main research topic in reliability physics. Despite the improvements in oxide quality, dielectric breakdown remains a major concern in modern high integrated circuits: The continuous reduction in channel length and oxide thickness leads to higher electric fields and heavier stress of the dielectrics. Especially in electrically erasable program¬ mable memories (EEPROMs) the tunnel oxides are continuously stressed during each read/write operation. The correct understanding of the trap gen¬ eration mechanisms is therefore crucial for the lifetime of the device. But despite intensive studies and hundreds of publications in the past, the under¬ lying physical and microscopical mechanisms remain controversial.
"Breakdown" of a reverse biased junction or a dielectric isolation can occur when a sufficiently high field is applied. A very high current can then flow. If the current is not limited the heat dissipation normally becomes so high that the melting temperature of silicon or silicondioxide is achieved and the structure is destroyed. Besides this immediate breakdown, a slow continuous weakening of an oxide at relatively low stress conditions can be followed by a sudden increase of the leakage current and finally by break¬ down of the dielectric. This type of breakdown is called "time dependent dielectric breakdown" (TDDB).
Now let us briefly consider the different types of breakdowns: There are two different ways a p-n junction can break through. The high current flow can be due to either the tunneling effect or an avalanche multiplication of the carriers. In tunneling, the thickness of the energy barrier becomes small enough that a significant number of electrons tunnel from the silicon valence band into the conduction band (band-to-band tunneling). In silicon this effect occurs for an electric field of about 10 V/cm. In the avalanche case, on the other hand, a multiplication mechanism generates electron-hole pairs by impact ionization. The current increases until a thermal runaway occurs.
In Fig. 2 two pictures of junction breakdowns are shown. In the left pic¬ ture the high electron current in the channel of a NMOS-transistor heated the silicon to the melting point. The direction of the electron flow (from source to drain) can clearly be seen. It is also interesting that the failure occurred at a corner of the gate where the electric field reached its maxi¬ mum. In the right picture of Fig. 2, the p+ doped diffusion of a diode melted during an avalanche breakdown can be seen. Dielectric and Junction-Breakdown 7
drain SpÄ^^A poly-gate
Fig. 2 : Drain-source breakdown of a NMOS transistor after dram current stress (left) subse¬ and melted p+-region of a diode (right) due to breakdown of the junction and a quent excessive current flow.
After this short discussion of the junction breakdown, dielectric break¬ down will now be briefly reviewed. Time dependent dielectric breakdown (TDDB) is a two stage process: First the oxide is slowly damaged under electrical stress and then a rapid runaway process occurs, which leads to the formation of a permanent conductive path through the oxide. Although the mechanism of the intrinsic breakdown has been extensively studied in the past, it is still not completely understood.
One explanation for TDDB is the anode hole injection model [4]. According to this model, a fraction of electrons that tunnel through the oxide barrier can transfer their energy to deep valence electrons. Such an electron is promoted to the conduction band edge, thereby creating a hot
hole. The hole can tunnel back into the oxide and
subsequently breaks a Si-0 bond and creates an oxygen vacancy [5]. Intrinsic breakdown occurs when a critical hole fluence, QPiCnt, is reached. It been that C» decreases for thin has observed cnt oxides [61.
In the picture on the left an example is shown:
Electrons tunnel from the n+-polygate of a NMOS transistor through the oxide into the p- substrate.
Fig. 3 : Generation of hot holes on the anode side. 8 Survey of Failure and Degradation Mechanisms
According to Schuegraf and Hu [6] the breakdown lifetime can be approximated as:
^3.9-108-Q (i) "BD 5-lCTIJ-exp [s.V,cm]
Eq. ( 1 ) was found to work well for oxides thinner than 120A. In Fig. 4 the times-to-breakdown of the gate-oxide of NMOS transistors with dox=3nm and dox=6nm were calculated with Eq. (1) and plotted versus gate voltage.
1E+10-
Ten Year Lifetime
dox=6nm
Fig. 4 : Times-to-breakdown ofNMOS transistors for two different oxide thicknesses.
A second model for TDDB claims that a critical density of electron traps is required to trigger oxide breakdown [7]. Degraeve et al. [81 have linked these two models to a new model based on a percolation concept: After the creation of a critical electron trap density some 'breakdown path' is built up and conduction starts via these generated traps. They supposed that both cri¬ teria, critical hole fluence and critical electron trap density, are equivalent.
Satake et al. [91, on the other hand, show with their experiments that the coexistence of hot electrons and holes is essential for dielectric breakdown in Si02. They suppose that in a first step hot electrons break the weak bonds (such as Si-H and strained Si-O) creating silicon dangling bonds that behave Electrostatic Discharge (ESD) and Latch up 9
like hole traps. In a second step holes are captured by these dangling bonds and as a result, the Si^O can no longer keep its three-dimensional tetrahe- dral structure and collapses to a more plane structure. Dielectric breakdown occurs when a conductive path, connecting the locally collapsed Si=0 struc¬ tures, is produced throughout the oxide.
Electrostatic Discharge (ESD) and Latchup
Electronic components are sensitive to high voltages. Through triboelec- tric static charge build-up voltages ranging from 100V to 20kV are quite possible. During an electrostatic discharge event currents of more than one ampere flow for durations between a few nanoseconds and 100ns. This can cause severe damage in the sensitive areas that are directly connected to the bond pads of the chip. Especially gate oxides of MOS transistors can easily be damaged during an ESD event: The oxide locally melts and a permanent conductive path results. Specific circuits are designed at the input pins of ICs to protect them. Unfortunately, because of the limited available die area, these circuits are normally only capable of dealing with a maximum static voltage of several kilovolts. Therefore, it must always be made sure that the handling of sensitive circuits by persons or robots cannot lead to a charge build-up.
Fig. 5 : Electric discharge failure of an "Ethernet Coaxial Transceiver Interface": The failure occurred in the fehl after the impact of a lightning strike. Silicon melted between the emitter of a bipolar transistor (arrow) and some other device near an input pad. 10 Survey of Faillite and Degradation Mechanisms
In Fig. 5 an example of an electric discharge event near an input pad is shown. The device failed in the field after the impact of a lightning strike. For a better visualization of the failure the sample was prepared by a wet- chemical removal of metallization and oxides by means of diluted hydro¬ fluoric acid (HF-stnp).
Fig. 6 shows a source-drain short in a MOS transistor of a protection cir¬ cuit. The failure was induced during an ESD characterization of the device. Failed devices were analyzed by a pm-to-pm electrical test of the device. During this simple test the IV-curve of each pin of the device is measured against Vdd and Vss. Normally some diode characteristics is found. In the case shown below, however, a resistor was measured between the input and Vdd (respectively Vss). The sample was prepared by a HF-strip, i.e. metalli¬ zation and oxides were removed. Only after preparing the sample in this way, the failure could be exactly located and identified in the microscope.
6 : Fig. Melted silicon path between sowce and chain of a MOS transistor protection cir¬ cuit a in microcontroller This failure occur red diu ing ESD testing.
Different protection circuits were proposed in the past to protect a device from ESD events. The simplest structures are the "clamped diodes" (see Fig. 7). Clamped diodes work as follows: A voltage that is more positive than Vdd at the input pad forward biases the upper diode and a voltage that is more negative than the ground potential forward biases the lower diode [10]. Voltages above the power supply voltage or below the ground potential are therefore conducted away into Vdcl or Vss.
Another widespread ESD protection device is the grounded-gate NMOS transistor (ggNMOS). During an ESD event, the device operates mostly in the snapback mode. The avalanche generation of carriers m the high-field region near the drain results m hole current injection into the substrate. The Electrostatic Discharge (ESD) and Latchup 11
voltage drop across the substrate resistance raises the local substrate poten¬ tial and eventually causes the source-substrate junction to become forward- biased. Electrons injected from the source into the substrate are collected at the drain forming a lateral NPN bipolar parasitic transistor. The drain acts as the collector, the substrate as the base, and the grounded source as the emit¬ ter [11]. At higher stress levels, the device can go into the second breakdown region where filament formation and device failure occurs. To maximize the protection level, ladder structures are used where the MOSFET gates are laid as parallel fingers. However, a uniform conduction of all parasitic bipo¬ lar devices is difficult to achieve. Instead a dynamic gate coupling effect can be used to achieve uniform conduction and to improve ESD performance [12].
V V 1 dd 1 dd i
S H PMOS H PMOS Pad Pad
s NMOS H NMOS j T eaNMOS
7 : ESD Fig. protection of an input CMOS-inverter: clamped diodes (left) and grounded- gate NMOS (ggNMOS) transistor.
Another important failure mechanism is latchup. It occurs when parasitic NPN and PNP bipolar transistors form a PNPN structure. This constitutes a thyristor (SCR), which has the ability to switch between a high impedance blocking state and a very low impedance state. Under normal operating con¬ ditions, the SCR remains in the nonconducting state and does not interfere with circuit operation. However, under certain conditions (e.g. voltage spikes, ionizing radiation, etc.), the SCR may become triggered into the conducting state and the power supply effectively sees a low impedance path to ground. Irreversible damage can then occur to the circuit.
A thyristor can be characterized by the switching voltage Vs and the hold¬ ing voltage Vh, where Vs marks the transition point from the high impedance region to the negative differential resistance region and V^ is referred to the transition from the negative resistance region to the low impedance region. 12 Survey of Failure and Degradation Mechanisms
In a robust CMOS technology Vh is greater than Vdd: Whatever transient triggering occurs, the maximum power supply on chip is below the voltage required to sustain latchup [13].
Fig. 8 shows a simplified cross-section of a CMOS inverter. The various parasitic bipolar components that comprise the inherent PNPN structure are also indicated. Under normal operation the circuit works as an inverter, and the parasitic elements can be ignored. Under certain conditions, however, latchup can be induced. For example when the voltage on Vout exceeds the power supply voltage Vdd (e.g., this condition can be induced by signal reflections at a mismatched interface) the p+/n-well junction becomes for¬ ward biased and holes are injected into the n-well. Some holes recombine with electrons in the n-well. others diffuse to the reverse biased n-well/sub- strate junction and are collected by the substrate. The hole current in the substrate produces an ohmic drop and a grounded n+/substrate junction can become forward biased. When the loop gain of this parasitic PNPN structure exceeds unity and this bias condition exists long enough, the critical switch¬ ing value that turns on the thyristor can be reached. Then the circuit does not correctly function any more and excessive current flow can destroy the device.
p-substrate
Fig. 8 : Latchup structure: n-well CMOS inverter including parasitic bipolar transistors.
Latchup can also be induced when a n+-diffusion lies near an n-well. Dur¬ ing power supply voltage raising the depletion region of the n-well/sub strate reversed bias junction may reach the nearby n+-diffusion and punchthrough will occur. Electrons flowing into the n-well can turn on the parasitic verti¬ cal pup transistor. A third possibility for latchup is given when the power supply voltage is raised sufficiently so that avalanche breakdown in the n- well/substrate junction will occur. For more details, please consider [13]. Electro- and Stressmigration 13
Electro- and Stressmigration
The most important failure mechanism on the metallization level of an IC Is electromigration [14]. The mechanism works as follows: If a sufficiently high current density (above 10 A/cm~) is available in a metallization track, the continuous scattering of electrons at defects transfers a momentum to the aluminum atoms in the lattice surrounding the defect and a net atomic diffusion in the direction of the electron flow can start. At weak spots, such as at steps, voids can be formed and an open failure can occur.
The electromigration phenomenon is only possible in the thin film con¬ ductors of ICs. Only here the efficient heat sink allows the thin film wires to sustain the necessary current density. In conventional metal wires, Joule J. O heating limits the current density to about 10 A/cm". At higher currents the 7 ""> wire fuses. Thin film conductors in ICs can sustain more than 10 A/cm" without immediate damage.
In aluminum the mass transport due to electromigration dominates at the grain boundary. The microstructure of the metallization plays therefore a vital role in the lifetime of a device. It has long been known that the smaller the grain size, the less reliable is the conductor. In fine wires, where the line width is smaller than the grain size (bamboo structure), a continuous grain boundary path is absent and mass transport is therefore strongly reduced. Another important point is the actual composition of the metallization: A small addition of certain alloying elements, particularly copper, significantly increases electromigration lifetime, because these elements diffuse at the grain boundary and are able to fill voids.
Possible migration and void formation also depends on the current direc¬ tion. If a bidirectional current stress is applied, possible voids are cured again. The ac lifetime is usually much longer than the dc lifetime and the design rules can be more aggressive than in the dc case. Width and height of interconnects can be reduced to minimize parasitic capacitances and to achieve better circuit speed and power performance. Tao et al. [15] modeled the influence of the frequency by modifying Black's equation [16] in the fol¬ lowing way:
f Mean Time to Failure = MTTFnr <>= ~-exp (2) ^kf 14 Sui \ ey of Failure and Degradation Mechanisms
where m is a constant with a value around 3.3 and Ea is the activation energy.
But electromigration is not the only cause for aluminum migration. Alu¬ minum and silicon can interdiffuse: At a Si-Al interface, for example at a contact, aluminum atoms can diffuse into the silicon forming a 'spike'. A shorted junction can be the result. To prevent the formation of spikes, barrier layers were introduced. These barriers (e.g. TiN) also improve the elec¬ tromigration reliability: When a void in the Al-track is formed the underlay¬ ing barrier layer shortens the void.
A further mechanism of aluminum transport is due to stress migration. Stresses are introduced during the production process of ICs: Aluminum is deposited at 150-300°C. The Al-grain size is a function of the temperature. Stresses and faults introduced during the deposition are annealed in a next process step: The wafers are heated to about 400°C. But then, during cool¬ ing to room temperature, additional stresses are introduced due to the differ¬ ent expansion coefficients of aluminum, silicon and silicondioxide. At places with high tensile stresses, in particular at steps, atoms can be trans¬ ferred in order to equalize the stresses. This mechanism is called stressmi- gration.
In Fig. 9 an example of a weak point in a circuit is shown: A metallization track is thinned out due to an oxide step. Stress- and/or electromigration led
to the formation of a crack and a void.
Fig. 9 Stress at steps can cause /eliabilirx problems. Corrosion 15
Corrosion
Despite the improvement of package and passivation of ICs, corrosion remains an important failure mechanism. The introduction of plastic pack¬ ages in almost all applications aggravates the problem: Plastic packages are not hermetic and moisture can diffuse to the circuit.
In the following section some basic characteristics of aluminum corrosion will be described. Aluminum has a very high affinity to oxygen. Neverthe¬ less, pure aluminum remains stable in air, because a thin layer of Y-AI2O3 protects it. Aluminumoxide can be converted in aluminumhydroxide (Al(OH)3) after the contact with water. Al(OH)^ is barely soluble in water and aluminum remains protected.
Despite the natural protection of aluminum, corrosion of the metallization in an integrated circuit is a problem. The reason is that in ICs not pure Al, but an Al-Cu-Si alloy is used. This mixture is necessary to prevent the met¬ allization from other failure mechanism, such as electromigration or inter- diffusion with silicon. But, unfortunately, on an Al-Cu-Si alloy the protecting aluminum oxide layer cannot be completely formed and in the gaps in the protecting layer corrosion can initiate.
Next, some main chemical properties of aluminum and some important reaction steps of its corrosion will be briefly discussed: Aluminum is soluble in a non-oxidizing acid, for example in HCl. Hydrogen is thereby formed. Oxidizing acids on the other hand build with Al a protecting layer and do not further attack it. (This is, by the way, the reason why a plastic package can be opened with fumic red nitric acid without destroying the Al-metalli- zation. This fact is very useful for failure analysis.)
Al(OH)3 is amphoter, i.e. it is soluble in strong acids and in bases. The chemical reactions, as described in reference [17], are then:
Al(OH)3 + 3/T <-> Af"" + 3H,0
' '
or (3)
Al(OH)^ + OH" Corrosion in an IC can be due to two different mechanisms: Corrosion in a galvanic cell or corrosion in an electrolytic cell. Such a cell contains two 16 Survey of Failure and Degradation Mechanisms electrodes, called anode and cathode, and an electrolyte, for example water. In the electrolyte the ions that participate in the reaction migrate from one electrode to the other. The electrode with the more positive potential is called 'anode' and the electrode with the more negative potential 'cathode'. Corrosion always occurs at the anode. In a galvanic cell the anode and the cathode consist of two different mate¬ rials (with different standard potentials). In integrated circuits noble metals such as gold or silver form the cathode and aluminum or titanium the anode. When the anode is electrically connected to the cathode a current starts to flow and the ions from the anode go into solution and migrate to the cath- ode. In an electrolytic cell, on the other hand, a dc voltage that drives the chemical reaction is necessary. In this case, the two electrodes may be of the same material. Chlorine or bromine are necessary for the corrosion of an IC metalliza¬ tion, because the Al(OH)3 protection layer must be attacked before the cor¬ rosion of the aluminum can take place. Due to the electric field in an electrolytic cell chloride ions move to the anode and are there absorbed by the hydrated aluminum-surface. Then the following reaction takes place (see reference [18]): Al(OH), o AKOFDt + OFF (4) AKOHt + Cr -> Al(OH),a Al(OFI)2CT is soluble in water, dissociates there and the chloride ions become available for a new reaction with aluminumhydroxide. Therefore, only a very small chlorine contamination is necessary to attack the alumi¬ num with an aqueous solution and to cause serious corrosion of the metalli¬ zation. Chloride ions can also react with aluminum forming aluminum chloride, which reacts with water producing HCl, through the following reaction [ 19]: Al + 3C7" Similar reactions are possible with bromine. Possible chlorine or bromine contaminations in ICs have various roots: Bromine is used in the flame- retardant epoxy of plastic packages. Chlorine contamination can be intro¬ duce during the processing of the wafer (i.e. through the CVD-process of oxides where dichlorsilane is used or during deposition of titaniumnitride by means of titantetrachloride). In Fig. 10 an example of corrosion is shown where the attack of a Vdd- metallization has just started. Fig. 10 : Corrosion of a Vjj -metallization Another latent danger lies in the widely used phosphorsilicate glass (PSG). PSG is used as an intermetal dielectric, as a spacer material and as a passivation layer. PSG is silicondioxide doped with phosphorpentoxide P205. This improves the mechanical qualities of the oxide and also acts as an ion trap (such as Na+) to prevent the active region from contamination. (Ions reaching the active region can shift the threshold voltage of MOS tran¬ sistors.) When the P2O5 doping concentration of the oxide is higher than 6% or when the PSG is not properly annealed, the phosphorpentoxide is not sta¬ ble and can react with water building phosphoric acid: P20, + 3H20->2Hf04 (6) The phosphoric acid can attack the metallization and an open can be the result. 18 Sun e\ of Failure and Degradation Mechanisms Interdiffusion of Metals In devices with a plastic package the chip is bonded to the lead frame with gold wires. (In hermetic packages aluminum wires are normally used.) At the bond place intermetallic compounds between gold and aluminum are formed. Dominant are AuAlo and AuAl5. This is necessary for a good and reliable contact. However, if the Au-Al compound formation is not well controlled (e.g. at too high temperature), the feared purple plague (AuAl2) results. The contact resistance increases and the bond becomes brittle and mechanically weak. Interdiffusion of gold-aluminum can also lead to voids under the bond balls (Kirkendall voiding). Additionally, it should be mentioned that in pres¬ ence of halogens the formation of purple plague is enhanced and failures can already occur at quite low temperatures (at about 180°C, as was reported in reference [21]). An example of an uncontrolled Au-Al interdiffusion is shown in Fig. 11: A gold wire was bonded on an aluminum bond pad. The device was then put into an oven and after a burn-in of about 3000h at 120°C various opens at the inputs and outputs of the circuit were found during a pin-to-pin test. Then the plastic package of a failed device was opened with fumic nitric acid and depassivated with Nitrox. (Nitrox is a solution that etches nitride and slightly oxide selectively against aluminum (see reference [22])). In the SEM a strong Au-Al interdiffusion at the bond place could be identified. Fig. 11 Interruption of metallization due to inteidiffusion of gold and aluminum. Left- secondary electron image, right• backscattered electron image. Contamination 19 Contamination Despite improvements in packaging technology contamination remains an important failure mechanism. The continuous reduction in package size shortens the distance moisture and ions have to diffuse to endanger the sen¬ sitive parts of a device. For the correct functionality of an integrated circuit it is very important to reduce the contamination risk. During wafer processing a cleanroom envi¬ ronment is crucial. At the end of the chip fabrication process the wafers have to be passivated to protect them and finally a reliable package is necessary. Contamination has different sources: It can already be introduced during the crystal growth, it can originate from the wafer processing, from the package or it can later diffuse through the package (especially along an interface, for example along the frame-epoxy) and through the passivation layer to the active region. Silicondioxide, siliconnitride and polyimides are used as passivation lay¬ ers. Silicondioxide is the natural passivation of silicon. Siliconnitride is used because it is chemically very stable and acts as an excellent barrier against moisture and ion diffusion. Polyimides have low dielectric constants, are also stable and easy to deposit (spin-coating). Their disadvantage is, how¬ ever, that they absorb a relatively high quantity of water. For protection the devices are enclosed in a package of metal, plastic or ceramic. The diffusion rate of water in epoxies is about three orders of mag¬ nitudes higher that in glass. Therefore, to prevent an integrated circuit from contamination a preferably hermetic package should be used. A hermetic package consists of two ceramic pieces with a cavity which are sealed together. The disadvantage of hermetic packages is that they are big, heavy, expensive and not very resistant against mechanical shocks. In addition, they have only one heat sink on the back. Therefore, plastic packages are preferred in almost all applications nowadays. In these packages the chip is molded with a mixture of silicon or epoxy resin, silica as a filler material and some additives (e.g. flame retardants). Novolac epoxies are normally used as molding materials. They are very pure, have good mechanical prop¬ erties, a high heat conductivity and a low thermal expansion coefficient. Fur¬ thermore, the contraction during polymerization is low. Silicon resins are used frequently for discrete power devices, because they have very good dielectric properties. The disadvantage of silicon resins is their bad adhesion to the lead frame, which is a result of the water formation at the interface during polymerization. 20 Sun ex of Failure and Degradation Mechanisms In the following the main effects of contamination will be briefly reviewed: Metallic impurities in silicon are efficient minority carrier lifetime killers. They have energy levels close to the middle of the bandgap and serve there¬ fore as traps in Shockley-Read-Hall recombination. Depending on the appli¬ cation, long or short minority lifetimes can be desirable. In some power applications for example, wafers are intentionally doped with gold to reduce minority lifetime and improve switching. On the other hand, a long minority lifetime is important for example in solar cells, where the electron hole pairs generated by photons must have enough time to diffuse out of the depletion region. Recombination centers, given for example by metallic impurities, lower dramatically the efficiency of the cells. Na+, K+ and CF ions in the active region can shift the threshold voltage of a MOS transistor. When Na+ ions drift into the channel of a NMOS, the band is bent down due to the positive charge. The threshold voltage is subse¬ quently lowered and the subthreshold leakage currents increase. Further¬ more, ions over a field oxide can introduce parasitic transistors. Na+ ions can also lower the potential barrier at the Si/Si02 interface and as a result charge injection into the oxide increases. Besides the corrosion problem mentioned above, other failure mecha¬ nisms can be introduced by moisture. An example is the growth of silver dendrites, which can lead to short circuits (e.g. between two bond pads). Silver is sometimes mixed with epoxy to produce a conductive die attach material. When this silver epoxy comes into contact with moisture an elec¬ trolytic plating process starts in the presence of an electric potential. Silver is then solved in the electrolyte and migration starts. Ditz has reported (see reference [23]) that, unlike in other electrolytic plating processes, silver migration does not even require condensed moisture: The migration starts already at a relative humidity of 40%. Another example of a moisture induced failure mechanism is popcorn cracking in surface mount devices (SMDs). Plastic-encapsulated packages absorb ambient moisture until an equilibrium with the surrounding environ¬ ment is reached. The amount of absorbed moisture is dependent on the stor¬ age conditions (on the temperature and relative humidity). When the SMD device is soldered to a printed circuit board, the package temperature sud¬ denly rises and the absorbed moisture will quickly turn to steam. This phase change may result in significant internal pressure rise, which, depending on the absorbed moisture, can result in a swelling or ultimately cracking of the Radiation 21 package [24]. As a result, device manufacturers routinely "dry-pack" devices before shipment. Once the devices are removed from the dry pack, they must be mounted within a specific time. Several possibilities to improve popcorn resistance have been discussed in the literature. Possible improvements can be obtained by a window 125] or by dimples in the lead- frame, by changes in the composition of the molding compound or by the amplification of the adhesion by means of the use of a Zn-Cr coating on the Cu leadframe [26]. Radiation Ultraviolet (UV), X-ray and particle radiation (oc,ß) can influence the function of a device. Various failure modes are possible: A "soft error" occurs when stored information in a memory device was changed by the influence of radiation while the circuit itself is not permanently damaged. A charged particle (an a-particle, a proton, an electron or a muon) can gener¬ ate thousands of electron-hole pairs in the device. When the particle passes near the capacitor of a DRAM memory cell, the tiny charge of the capacitor can be changed. Similarly a floating gate of an EPROM cell can be charged or discharged by ionizing radiation. In high power devices such as thyristors, GTO's, diodes and IGBTs cos¬ mic ray induced catastrophic failures occurred: Heavy particles (e.g. silicon recoil nuclei induced by cosmic neutrons) lead to localized bursts of charge. Then the electron-hole plasma separates in the external applied electric field. If the field is high enough, impact ionization sets in and a self-support¬ ing filamentary discharge can occur [27]. Radiation is also able to generate interface traps and oxide charge. This degradation mechanism leads to shifts in the threshold voltage of MOS tran¬ sistors and weakens the breakdown strength of thin oxides. The main sources of ionizing radiation are radioactive trace impurities and cosmic rays. Important radioactive trace elements in the materials used for device fabrication are uranium and thorium and their fission products. These radioactive impurities could be found in the gold of bond wires, in the alumina of ceramic packages, in the lead-frame alloys and in other materials commonly used in electronic devices. Cosmic rays consist of a number of different particles impinging on the earth's upper atmosphere. The interac¬ tion of these high-energy particles with air leads to cascades of lower-energy 22 Sun en of Failure and Degradation Mechanisms particles. At sea-level the cosmic ray flux is primarily composed of neu¬ trons, protons, electrons, and muons. Thermal neutrons from cosmic rays are among the most abundant particles, but their energy is too low to pro¬ duce charge by nuclear recoil. However, if thermal neutrons are captured by the nuclei of materials in a electronic device, they induce nuclear reactions which produce energetic radiations. Baumann et al. [28] reported that boron is a significant source of secondary radiation induced from thermal neu¬ trons. Boron, as it occurs in nature, is composed of two isotopes, B (80% abundance) and 10B (20% abundance). The thermal neutron capture cross- section of 10B is extremely high. After absorbing a thermal neutron, B fis- sions in an excited Li recoil nucleus, a y -photon, and an alpha particle. Therefore, to reduce the soft error danger, isotopically-separated boron should be used as acceptor doping. Thermo-Mechanical Problems a[10h/Kl i 4 epoxiesv 60 5_oJ_ Polyimides 40 SO Tin-Lead t- — Aluminum -A Coppei —— -- FR4 !£ - Mumma Ulm-42 *' Silicon q 1-4 Fig. 12 : Various thermal expansion coefficients of commonly used materials in elec¬ tronic devices (values are given in reference [29]). The thermal expansion coefficients (a) of the various materials used in a semiconductor device are quite different (see Fig. 12). For example, silicon Thermo-Mechamcal Problems 23 has an a=2.8-10~6/K, aluminum an a=23-10"6/K and epoxy an a=60-10~6/K. These differences in the thermal expansion lead to stresses between die, frame and package. The stress is proportional to (7) (a{-a2)-AT . The different thermal expansion coefficient can induce serious reliability problems when the device is stressed under thermal cycling. Possible conse¬ quences of a thermo-mechanical stress can be: Delamination of the plastic from the chip surface or delamination of the plastic-frame interface, sheer stress of bond wires, aluminum reconstruction and other mechanisms. Delamination at the epoxy-leadframe interface occurs more often than delamination at the epoxy-chip interface. This is due to the relatively bad adhesion of epoxy to metals. The mechanism of aluminum reconstruction works as follows: As a result of the different thermal expansion coefficients of aluminum and silicon, compressive or tensile stresses are introduced in the thin aluminum metalli¬ zation during thermal cycling. When the thermal strain exceeds the elastic limit, the stresses are relaxed by plastic deformation and the aluminum-sur¬ face becomes rough. In IGBTs this mechanism leads to catastrophic failures caused by the lifting of the emitter bonding wires [30]. Devices that produce a lot of heat need a good heat sink. Therefore, mate¬ rials with a high thermal conductivity (X) should be used. For example, it is preferable to use a copper leadframe with k=4 W/cm K instead of an alloy 42 leadframe with only A=0.1 W/cm K. The big differences in the thermal conductivities of different die attach materials are another important aspect to take into account: A gold eutectic has a much higher thermal conductivity than silvcrepoxies. For example, whereas Au-20%Sn has a thermal conduc¬ tivity X of 2.5 W/cmK, silver-epoxy has a X of only 0.001 W/cm K. On the other hand, gold eutectics have the disadvantage that they are so-called "hard solders": Heating or cooling lead to high tensile stresses in the die. "Soft solders" like Pb-5%Sn are able to damp tensile stresses better. Unfor¬ tunately, their thermal conductivity is only 0.35W/cm K. Therefore it depends on the application which die attach is preferable. *** * $ I «^ L. | $ ,«- $• i is** V« M'V ÈOCiï 3 Two Examples of IC Degradation In this chapter, degradation on the circuit level will be investigated and methods that allow a quick reliability test of the device will be shown. Two examples of CMOS circuits were inspected: The first one was a lot of sim¬ ple 7-bit ripple counters and the second a batch of naturally aged SRAM memories. The counters were characterized measuring the quiescent power supply current (Iddq)- In some devices anomalous Iddq currents were detected. The reason for this behavior could be identified to lie in crystal defects. Then, some counters were stressed and characteristic changes in the Iddq current could be found. These changes were interpreted as hot carrier effects. It was shown that the Icldq method allows a quick sort-out-technique of possibly weak devices. Furthermore Ijclq can be used as an indicator of the age of a circuit. The second example was analyzed in connection with the European research project 'CARE' whose main goal was to find solutions for the heap of electronic waste increasing year by year. Besides recycling, an already realized way is the reuse of some specific electronic parts. Although these devices might seem obsolete compared with the performance of new ones, they sometimes can have an amazing high value as replacement parts for long-lived, expensive equipment. The aim of this analysis was to identify main wearout mechanisms and to find a simple electrical test to sort out failed or weak devices before a reuse. To check these questions, 448 old SRAM memories that worked in telephone exchanges during about 15 years were functionally tested. 35 devices could be found that were failed or had problems. All weak or failed memories had increased standby and/or 25 26 Two Examples of IC Degradation increased input leakage currents. The measurement of these currents pro¬ vides therefore a reliable and efficient electrical test to identify problematic devices before reuse. ïddq Measurements of a Ripple Counter Whereas the power supply current of a CMOS circuit lies in the range of amperes during logic state transitions, only nanoamperes flow during the steady state, or quiescent, portion of the clock cycle. This quiescent power supply current, known as Iddq, can be used as a sensitive test to identify defects [31]. The principle of the technique is shown in Fig. 13: A single inverter, consisting of a PMOS and a NMOS transistor, models a CMOS cir¬ cuit. When a logic one is applied at Vm, the PMOS is turned off, the NMOS on and Vout becomes a logic zero. The Iddq is now given by the leakage cur¬ rent in the PMOS transistor. Vice versa, when at the input a logic zero is applied, the PMOS is turned on, the NMOS is off and the output becomes one. The Tddq current is now given by the leakage in the NMOS transistor. Defect Vm Vout Vss Fig. 13 : Principle of an Icicjq measurement. In the quiescent state of a CMOS circuit, about one half of the transistors are turned off, and each off-state device contributes a small leakage current Iddq Measurements of a Ripple Counter 27 to the Iddq (mainly due to junction leakage). A defect in a gate oxide or dif¬ fusion or some short or open in the metallization usually increases the quies¬ cent current in some logic state. This anomalous behavior allows to recognize failed or problematic devices in a lot without a thorough func¬ tional test. The measurement of the Iddq is a very effective technique in modern CMOS IC testing. It is sensitive to junction leakage, gate oxide defects, shifts in the threshold voltage due to ionic contamination or hot carrier effects, opens due to electromigration or missing vias. bridging defects between metal lines and so on. The technique has even eliminated the need for burn-in for some mature product lines. Moreover, Iddq gives hints in fail¬ ure analysis. Unfortunately, it is only effective in ICs fabricated for low background current. For optimum detection of manufacturing defects, the defect-free Iddq of an IC should be less than lu A. To investigate the power of Iddq a simple 7-stage binary counter (MC 14024) was characterized. The device was chosen because it is very easy to understand: It contains only seven flip-flops in series. The states of the counter are: 0:0000000 10:0001010 1:0000001 11:0001011 2:0000010 12:0001100 3:0000011 13:0001101 4:0000100 14:0001110 5:0000101 15:0001111 6:0000110 16:0010000 7:0000111 17:0010001 8:0001000 18:0010010 9:0001001 19:0010011 127:1111111 Fig. 14 : States of the 7-bit binary ripple counter. In each state of the 128 bit counter the lddq was measured with a picoam- peremeter (after a holding time of one second). Depending on how many and which transistors are turned off, more or less leakage current flows. Fig. 15 shows the typical "sawtooth" Iddq-pattern of a new and good counter. A total of 120 counters was characterized in this way and six devices were found with some atypical behavior: Their Iddq current was in certain states increased by several orders of magnitude. Examples are shown in Fig. 16 to Fis. 18. 28 Two Examples of IC Degradation Ob-^-r-COLnOjmcDCOON-^l-T-COLOCMCntO T-c\j(Mco^f^tLncDr-~-N-cocXi050T-->-oJ state Fig. 15 Typical Inpatient of a new counter (#88) foi V^=18V 2 OOE-06 (I I I I I I I 11111,11 oh-^-^-caincMcncûcooN^T-coiocMcncû T-CMCMC0'^f-^-LncDl^.r--C0CT)CT)OT--T-CM state is Fig. 16 . An atypical pattern of a new counter (#108) The defect probably the 4. flip- flop In device #108 (Fig. 16) the states 0 until 7 have an Iddq current of around 4pA whereas in the states 8 until 15, an Iddq of about 1.5uA flows. Consid¬ ering the states of the binary counter (Fig. 14), it can be seen that the increased Iddq flows only when output 4 is high. It can be concluded that the defect is located in the forth flip-flop. A similar behavior shows device #73 (Fig. 17): In the states 0 to 3 about 20pA flow whereas in the states 4 until 7 the leakage is around lOpA. Com¬ paring this with the table in Fig. 14 it can be seen that a high current flows when output 3 is low. Therefore some defect can probably be found in the third flip-flop. Iddq Measiuements of a Ripple Countei 29 2 50E-11 2 OOE-11 1 50E-11 Nmnmmm 2 1 OOE-11 5 00E-12 0 OOE+00 oK,*T-coLncMcnco«ON.^-T-coLOc\ja>CD r-c\j state 17 An Fig. atypical pattern of a new countei (#73) Ihe defect is probably in the 3. flip- flop. Finally, in device #121 (Fig. 18) the states 1 and 2 have leakage currents of about 5nA whereas in the states 0. 3 and 4 only about 4pA flow. From this periodicity it can be concluded that the defect must be in the second flip- flop. 6 OOE-09 5 OOE-09 < 4 OOE-09 er 3 OOE-09 -a 2 2 OOE-09 1 OOE-09 0 OOE+00 or--'* coiocMcncocooh-^ co Lo c\j en co W N CO iocoh-h-ooCT>a>o state 18 ' An Fiq atspical pattern of a neu counter (#121) The defect is probably in the 2 flip-flop The nature of the defect of device #121 (Fig. 18) will now be further ana¬ lyzed. First, the schematic of the circuit of the second flip-flop is considered (see Fig. 19). The part of the circuit drawn in bold lies on the high potential when the increased Iddq flows (i.e. in the states 1, 2, 5, 6, etc.), otherwise only small leakage currents flow. 30 Two Examples of IC Degradation I_ ITT - ! JH~. j _j_ I _[ [ __E. Fig. 19 : Schematic of the 2. flip-flop of the counter The part in bold is high in the states 1 and 2 and low in the states 0, 3 and 4. The device was wet-chemically opened by means of red fumic nitric acid. Then the circuit was put in the second state and observed under an emission microscope. (The emission microscope is a combination of a common light microscope and a very sensitive photomultiplier. which is able to detect tiny light sources in the visible range.) During a first inspection the entire chip was observed, but only noise was detected. Thereafter the emission micro¬ scope was zoomed into the region of the second flip-flop where the defect was suspected. After a very long integration time of about half an hour, a weak emission point was found in the diffusion which is shown in bold in Fig. 19. A photo of this emission point is shown in the left picture of Fig. 20. Considering the circuit further, it was grasped that the metallization track near the emission point as well as the underlying diffusion have both the same (high) potential when the counter is in the second state. The small leakage current of about 5nA can therefore not flow between the metalliza¬ tion and the diffusion. The only possible explanation is that the current flows through the n-diffusion/p-substrate junction. In a next step, passivation, metallization and oxide layers were removed Iddq Measui ements of a Ripple Counter 31 by a diluted hydrofluoric acid solution. After cleaning the remaining bare silicon substrate, the sample was inspected in the secondary electron micro¬ scope (SEM) but nothing unusual could be found. Then the sample was dipped in Wright-etch for a few seconds. (Wright-etch is a solution of con¬ centrated hydrofluoric acid, chrome oxide, nitric acid, copper nitrate, acetic acid and water. This etch decorates defects on both the <100> and <111> planes in n- and p-type material [32].) Fig. 20 : Left: Light emission in the diffusion which is bold in Fig. 19. Right: A crystal defect was found in the silicon at the point where the light emission was found after dip¬ ping the sample m Wright-etch. Fig. 21 : Scanning electron microscope image of the crystal defect delineated by the Wright-etch solution. 32 Two Examples of IC Degradation After the crystal defect delineation by means of Wright-etch, the sample was again inspected in the SEM: At the point of light emission, a crystal defect could be found (see right picture of Fig. 20 and Fig. 21). The tiny junction leakage current of about 5nA was probably due to this defect in the n-diffusion, which was identified before to be the location of leakage. It is quite astonishing that it was possible (with the help of the emission micro¬ scope) to detect the light generation of such a small current. This example demonstrates in a impressive way the power of an Iddq measurement. In the past, Iddq measurements were preferably used in IC testing and fail¬ ure analysis. But the following experiments show that Iddq can also detect hot carrier effects on circuit level. A couple of new counters with a typical Iddq pattern (as shown e.g. in Fig. 15) were stressed at the maximum allow¬ able supply voltage for this technology (Vdd=15V) with a clock frequency of 500kPIz. After 135 hours or 1.9 billion cycles of the counter the typical sawtooth pattern changed into a more flat pattern. This can be noted com¬ paring Fig. 15 and Fig. 22. In the next step the counters were stressed additional 83 hours at the max¬ imum allowable frequency of 6.6 MHz (about 15.4 billion cycles). Thereaf¬ ter the Iddq pattern definitely changed: The sawtooths reversed their direction (Fig. 23) and furthermore the mean Tddq current increased by about one order of magnitude. ON-^t T-cOLOCMa>C£>COO h-^f-T-cOUOCMCDCD T- CMoaco^r^-uicor-- n-coojcdot-t-cm state Fig. 22 : At 15V with a clock frequency f= 500kHz during 135h stressed counter (#88). 33 Iddq Measurements of a Ripple Counter 3 50E-11 3 OOE-11 — 2 50E-11 w 2.OOE-11 o 1 50E-11 ~ 1 OOE-11 5 00E-12 0 00E+00 OK'*T-COLOC\JCT)CDCOON'^-'f-COlOCMCt>CD T-c\jc\jro-*^rLncDh-r-coa)CDOT-T-cM state Fig. 23 : At 15V with 17.3xl09 stressed counter (#88). The changes in the Iddq can be interpreted as follows: The leakage cur¬ rents in fresh counters are the higher the more outputs lie at a logic zero. When several outputs become low (for example after the transition from the state 31 to 32, i.e. 0011111 to 0100000) the Tddq sharply increases. On the other hand, in a stressed counter leakage currents are the higher the more outputs are 'one' (see Fig. 23). Whenever several outputs become low, the Iddq drops hard. After examining the circuit in more details, the following rule was found: When the output of a flip-flop is low, three NMOS and five PMOS are turned off. On the other hand, when the output is high five NMOS and three PMOS are off. This asymmetry of the number of turned off transistors is the root cause of the asymmetry in the leakage currents in the various states. Therefore it can be concluded that the Iddq currents in a fresh counter are mainly given by the leakage of the PMOS transistors in off-state, whereas in a stressed device the leakages current preferably flow through the NMOS transistors. This fact can be simulated counting the number of turned off transistors per state. To simulate the pattern of a fresh counter the number of PMOS transistors per state are drawn against the state number (see Fig. 24). On the other hand, the pattern of a stressed counter can be simulated by counting the total number of switched off NMOS transistors in the device and draw¬ ing it the state number. Results are shown in 25. xto against Fig. The simulation makes clear that the change of the Iddq pattern after stress¬ ing the counters is due to increased leakage currents in the NMOS transis¬ tors of the circuit. Later in chapter 5 (''Generation of Oxide Charges and 34 Two Examples ofIC Degradation Interface Traps" on page 91), single NMOS transistor degradation will be studied in more detail. Citing results of this chapter, it can be said that dur¬ ing the stress of the counter additional interface traps are generated near the drain junctions of the NMOS transistors. These traps lead to an increase of the junction leakage at the interface and to a subsequent rise of subthreshold currents in the NMOS transistors. Furthermore it is known from the litera¬ ture that hot carrier stresses in PMOS transistors are far less severe than in NMOS transistors. OCOCNJCtl^fOCOCMCO^OCOCJCÖTf-OCDCMCOxtOCD T-T-CMCOCD-st-^LOCÛCO Nh-C00>CT>OO->-C\l C\J state Fig. 24 : Total number of turned off PMOS transistors in the counter per state. O CD CM 00 * O CO CM CO "tf- O CD CM CO ^ O CO CM CO Tf O CD T- r-CMCO CO-* Tf W to CO r- N ID (J) o>OOt-C\J c\j state Fig. 25 : Total number of turned off NMOS transistors in the device. To examine further the nature of degradation in the NMOS transistors during the counting, a stressed device (#88 of Fig. 23) was stored for 91 hours at 150°C. Then the Iddq currents were measured again. The pattern changed once more and was again similar to the pattern of a fresh device Iddq Measurements of a Ripple Counter 35 (compare Fig. 15 with Fig. 26). Obviously the interface traps generated dur¬ ing the hot carrier stress can be annealed during a high temperature storage (at least partially). 3.30E-11 3 20E-11 3.10E-11 < 3.OOE-11 ""2.90E-11 2/ 2.80E-11 2 2.70E-11 2.60E-11 2.50E-11 2 40E-11 CD CO Ol^-^-r-COmcMCDCO UO CO N-h-COCT>CT)OT-T-CM state Fig. 26 : Stressed counter (#88) after annealing at 150°C. In a final experiment the effect of X-rays on the Iddq pattern was exam¬ ined. A new device was irradiated with X-rays during 15 minutes and then leakage currents were measured (see Fig. 27). 1.40E-09 -^ 1.35E-09 jg 1.30E-09 1.25E-09 1.20E-09 Oh--*T-ODLOCM05CDCOOKTtT-COLOCMCncû T-OJCMCOTj-Tj-incDN-N-COOCnOT-T-CvJ state Fig. 27 : Radiation damage (15 min. with 33kVX-ray). Irradiating a device has a similar effect on the Iddq pattern as stressing the device at a high frequency. Annealing the irradiated counter at 150°C repro¬ duces the initial Iddq pattern. 36 Two Examples of IC Degradation In can be concluded that in a fresh device the leakage currents preferably flow through the turned off PMOS transistors. Electrical stress of the device at a high power supply voltage leads to hot electrons in the pinch-off of the NMOS transistors and additional acceptor interface-traps are generated near the drain. As a result, the leakage current at the drain-sub strate junction is increased. Irradiating the device with X-rays breaks bonds in the gate oxides and generates positively charged oxide traps. This positive charge lowers the threshold voltage of the NMOS transistors and subthreshold currents rise. Temperature treatment anneals the interface and oxide traps and the initial Iddq pattern can be rebuilt. Analysis of naturally aged SRAM memories In this section results of an analysis of naturally aged devices are pre¬ sented. The author received 15 printed circuit boards (PCB) from a repair center of the national telecommunication company with totally 448 static lkx4 memories (SRAM). The PCBs were partly used in telephone exchanges during about 15 years (where they were under controlled condi¬ tions), partly they were stored as replacement parts. It was interesting to analyze these devices which spent their whole life in the field, to find changes and to locate reliability risks with regard to a possible reuse. All 448 SRAMs were tested on a HP8180/8182 tester. Four different test pattern were written to the devices: Two checkerboards where two neigh¬ boring cells had different logic states and two patterns where only one cell of a column was changed. (The purpose of this test was to check whether or not any cell changed its state when the bitline was activated.) Furthermore, on all devices standby currents and input leakage currents were measured. During the measurement of the input leakage currents all inputs were connected together. Then they were first set to a logic 0 and the input leakage was measured. Thereafter they were driven to a logic 1 state and again input currents were measured. To minimize other leakage currents all outputs were not connected during this procedure. Totally 35 of the 448 SRAMs had problems: 13 devices failed during the write-read test, 14 had a standby current of more than luA (standby cur¬ rents are normally some nA), 7 had input leakage currents of more than 2iiA Analysis of natu/ally aged SRAM memoi les 37 (instead of a few pA). All failed devices had increased standby current and/ or increased input leakage currents. Six of the thirteen failed SRAMs were analyzed in detail. After package opening corrosion of the metallization was always found to be the reason for the failure. Additionally, four of the seven devices with increased input leakage were opened and there corrosion was found as well. But these SRAMs had passed all the functional test despite the partly corroded metallization. Some pictures of problems shall now be presented: Fig. 28 • Left Vss. metallization of the completeh failed SRAM #238. Right Moisture under the passivation laxei pi oduced Newton iin^s on the failed device #331 In Fig. 28 sections of the corroded metallization of the devices #238 and #331 are shown. Both static memories totally failed the write-read test. The measured standby current in #238 was 13mA, compared to a few nanoam- peres in good devices. Through its inputs, a leakage current of about lOuA flowed. (Usually, the measured input leakage current lies in the picoampere range.) The right part of Fig. 28 shows Newton rings of device #331. In this sample moisture diffused from the bond pad under the passivation layer and delaminated the protecting oxide. Optical interferences at the thin layers lead to the so-called 'Newton rings'. The electrical test of device #234 pointed out that cells 0-31 did not work, cells 32-63 worked. 64-95 not, etc. Obviously, bit 5 could not any more be written. A pin-to-pin test demonstrated that pin 5 was open relative to Vss as well as to Vdd. In the left part of Fig. 29 a photo of the input pin 5 of this device is shown. It can clearly be recognized that the metallization near the contact is corroded (note the interruption at the arrow). The three examples mentioned above had all functional problems: Two 38 Two Examples of IC Degradation had totally failed (shown in Fig. 28) and one only partially (Fig. 29 left). However, during the electrical test some devices were found which func¬ tionally worked correct, but their standby or input leakage currents were increased. An example is shown in the right part of Fig. 29: Device #e35 passed the write-read test, the standby current bed within specifications, but a too high input leakage current of about 2nA was measured at input pin 14. To find out the reason for this increased input current the device was opened. During inspection of the sample under the light microscope a cor¬ roded Vss power supply line was found in the vicinity of input pin 14. The open in the Vss metallization had no consequences for the functionality of the SRAM because Vss is distributed m a circle. Obviously the corrosion products led to the measured high input leakage current. Fig. 29 Left Conoded metallization of one add)ess input of the failed device #234 Right: Conoded ViS metallization of the functionally couect working device #e35 It remains the question why the Vss power supply metallization corroded in this case. In an electrolytic cell only the anode (i.e. the metallization with the more positive voltage) is attacked. Device #e35, however, has got a cor¬ roded ground line. The most probable explanation for this corroded Vss met¬ allization is the following mechanism: In the past phosphorsilicatc glass (PSG) was often used as a passivation layer. PSG is a siliconoxide doped with phosphorpentoxide. When the concentration of the phosphorpentoxide is too high, it is chemically not well bound m the oxide and segregates to the surface. Together with water phosphorpentoxide builds phosphoric acid. This acid reacts intensively with aluminum and dissolves it. Also other hints for this mechanism were found: Teststructures without any electrical con¬ nection were corroded. In this case electrolytic corrosion can be excluded as well. Analysis of natinally aged SRAM memories 39 It is clear that devices like #e35 which work functionally correct but have a partially corroded metallization, run a high reliability risk in a possible reuse application. The analysis of the 448 SRAMs showed that risky devices can be found without a thorough functional test with the help of measure¬ ments of the standby and the input currents. Problematic devices can then be sorted out before a reuse application. Beside the corrosion problems, some other weak points were accidentally found during various inspection analyses in the secondary electron micro¬ scope (SEM). These problems were on the metallization level and were identified as beginnings of electro- and/or stress migration failures. In Fig. 30 two pictures of electromigration in the initial stage are shown. In the left part of the picture an open in the metallization at a contact window is pre¬ sented. In the right part of Fig. 30 it can be observed that electromigration prevails at grain boundaries. The arrow points to a triple point where three grain boundaries meet. At this point more material flowed away than was delivered and a hole resulted. Fig 30 Left beginning of aluminum migration at a contact window, right electromi¬ gration at giam boundai tes The anon points at a ti iple point In Fig. 31 two photos of interconnects are shown where oxide steps induced problems. In the left picture a missing gram m the metallization was found. Mechanical stress at the step probably extruded the grain. The right part of Fig. 31 shows a thinning of the metallization at a step. Mechanical stress and electromigration, enhanced at the reduced cross-sec¬ tion, threaten to interrupt the metallization at this point of the circuit. 40 Two Examples of IC Degradation \ Fig 31 Stresses at steps lead to extrusions of single grains (left) or to a thinning and finally an interruption of the metallization line (right) Some Measurement Methods and Characteristics of MOS Transistors In this chapter some important characterization techniques for MOS tran¬ sistors will be reviewed. The presented methods are especially important with regard to measuring degradation effects. We will start with the determi¬ nation of the gate length by atomic force microscopy. Then some remarks on the generation of substrate current by impact ionization in the high field region near the drain will be presented. In this context also the generation of light in the pinch-off region will briefly be discussed. A focal point will be the study of the tunneling current through the gate oxide. Fowler-Nordheim tunneling is applied in electrically erasable read only memories (EEPROMs) during the erase operation. It is also an impor¬ tant technique to study the quality of thin oxides. For a better understanding of the effect the tunneling current will be calculated by the Wentzel-Kram- ers-Brillouin approximation and also exactly. The exact solution leads to Airy wave functions. They represent the fact that the tunneling current oscil¬ lates. This effect was measured in thin oxides and will be compared with calculations. Furthermore, the various components of the tunneling current will be studied: Not only conduction band electrons can tunnel, but also valence band electrons are able to overcome the potential barrier at high normal fields. Another interesting aspect is the dependence of the tunneling current on the direction of the electric field. In further sections the poly depletion effect will be measured and the electrical determination of the effective oxide thickness will be discussed. 41 42 Some Measurement Methods and Characteristics of MOS Transistors Probably the most important technique for the characterization of the interface state density is charge pumping. The two different methods of G. Groeseneken et al. [66] and of TP. Ma et al. [69] will be reviewed and some representative measurements will be explained. Finally, the measurement of the channel mobility and some notes con¬ cerning its universal dependence on the effective electric field will be pre¬ sented in the last part of this chapter. Determination of Transistor Geometry by AFM The length and width of a MOS transistor are important parameters for device characterization. Unfortunately, their values are normally not exactly known, because of inaccuracies between the design and the actual imple¬ mentation in silicon. A method that allows to experimentally determine these values is therefore very useful. One possibility is the use of an atomic force microscope (AFM). A NMOS test-transistor on wafer level was prepared by a HF-strip: The device was dipped in a diluted hydrofluoric acid (about 10% HF) and etched in ultrasound for about nine minutes. Next, the device was washed under running water and blown dry. Finally, the surface was cleaned in warm water with soap by means of a cotton swab. (This cleaning technique is sometimes called "shampoo"). The HF-strip technique removes all layers above the silicon substrate: passivation, metallization, nitrides and oxides. Silicon is only very slowly etched depending on the concentration of the hydrofluoric acid. Polysilicon can be removed by underetching and a subsequent shampoo. After preparing the sample in the described way it was analyzed by an atomic force microscope (AFM). Two AFM-pictures are shown in Fig. 32 and Fig. 33. The images were acquired in "tapping mode": In this mode the tip is oscillating near its resonance frequency. Scanning the tip in the prox¬ imity (but not in contact) of the sample surface changes the oscillation fre¬ quency. This change can be measured and represented in a three- dimensional view. Considering Fig. 32 it can be observed that after such a preparation the active regions of the sample protrude. The HF solution slightly etches sili- Determination of Transistor Geometry by AFM 43 con too, but the etch rate is higher in regions with higher doping concentia- tion. At the boundary of the picture was field oxide before the HF-strip. In the interior of the image source, drain and channel can be recognized. Inter¬ esting is to see that the HF-etch rate depends on the doping of the silicon- the p-type channel region was neaily not attacked, whereas the n+ -doped source and dram region were moie etched. Fig 32 AFM image of a NMOS transistor with (IJW)-O ^pm/5pm, the sample was prepared by a HF-stiip Oxides and metallization w eie iemen ed Fig 33 AFM image of a NMOS transistor w ith (IJW)=0 5/./W/5///// Depending on dop¬ ing also silicon is sligJith etched b\ HF The n-doped source and drain region were etched more than the p-doped c hannel 44 Some Measurement Methods and Characteristics of MOS Transistors With the help of software tools the data can be averaged and a cross-sec¬ tion can be calculated (see Fig. 34). The problem, however, is that it is not exactly clear what shall be taken as "the channel length". As shown in Fig. 34 the p-region is at the top smaller then at the bottom. The measured shape can have various reasons: It can be due to the preparation of the sample. The shampoo can cause some rounding effects at the top or it is possible that the diluted HF-solution is not really selective and the etch rate is more a func¬ tion of the concentration than dependent on the type of the dopants. On the other hand, an explanation can also be found that the measured shape of the channel is real: It is possible that the rounded top is due to the implantation of the channel and of the lightly doped drain and source (LDDs). riM 1.50 Fig. 34 : With the help of the AFM software tools the channel length can now be deter¬ mined. The distance between the two black triangles is exactly 500nm. Besides this "direct" measurement method of the channel length, tech¬ niques based on electrical characterization of the transistor also exist. How¬ ever, the measured effective channel length is normally not equal to the metallurgical channel length 1331. NMOS Transfer Characteristic, Substrate Currents and GIDL 45 NMOS Transfer Characteristic, Substrate Currents and GIDL In this chapter, impact ionization, substrate current, generation of light near the drain junction and gate induced drain leakage current (GIDL) shall be discussed. Impact ionization is one of the basic root causes of hot carrier degradation in MOS transistors. Substrate current, light emission and GIDL are important indicators of degradation in MOSFETs. In Fig. 35 the drain- and substrate currents of a NMOS transistor are shown in dependence of gate voltage. Obviously, the substrate current and the GIDL increase as the drain voltage rises. The shape of these two curves shall now be discussed. Impact Ionization As the drain voltage increases, it eventually reaches a value at which the channel depth is reduced to zero. This point is called the pinch-off point. The drain voltage at the pinch-off point is called saturation voltage Vdsat, because the drain current essentially remains constant during further increasing of the drain voltage. The electric field peak is located in the pinch-off region and can reach in a submicrometer MOSFET a few hundred kilovolts per centimeter or even more. In these high fields electrons are accelerated and can reach energies of more than leV above the conduction band minimum. These electrons are able to create electron-hole pairs by impact ionization. 1E-2 ^Ä^t^^ ^Htt^*Ö^*#^n ro.oE+o NMOS 25u/5u 1E-3 J (LAV)=0 F-5 0E-6 d=6nm 1E-4 1 OE-5 T=298K 1E-5 r-1 5E-5 1E-6 1E-7 --2 OE-5 < 1E-8 r-2 5E-5 lb@Vds= n 1E-9 [0 5 3 5V, r-3 OE-5 1E-10 Step=0 3V] 1E-11 ld@Vds= "—4 OE-5 1E-12 [0 5 3 5V, 4 5E-5 1E-13 Step=0 3V] 1E-14 5 OE-5 -0 5 05 1 5 Vgs [V] Fig. 35 Dram-, substrate-, and GIDL-cur rents for several dram voltages 46 Some Measurement Methods and Characteristics of MOS Transistors Impact ionization is one of the key issues for understanding effects like avalanche breakdown of p-n junctions or the substrate current in MOSFETs. Impact ionization in MOSFETs was described as the cross-gap excitation caused by collision of a conduction electron and a valence electron in the substrate. In reference [34] it was supposed that for low drain voltages an indirect interband transition (F->X) is dominant, whereas for higher drain voltages the momentum transfer becomes smaller and a transition along the A-axis seems to be significant. (F,X and A refer to the symmetry points in the silicon band structure.) The generated electrons enter the drain and the generated holes are col¬ lected by the substrate causing the substrate current. As shown in Fig. 35 the substrate current first increases with increasing gate voltage and then decreases again. The initial increase is caused by the increase of the drain current with VCTS. More electrons flow in the channel and a higher impact ionization occurs. But increasing the gate voltage also raises the saturation voltage Vdsat. The voltage drop between drain contact and pinch-off point is therefore reduced and less impact ionization occurs. This two conflicting factors cause a maximum in the substrate current [35]. Shockley's lucky electron model [36] assumed that an electron gains energy from the electric field as long as it is not scattered by a phonon. In the process of scattering with a phonon the electron loses all its energy and begins anew at zero. The total loss of energy during the scattering process is justified by Shockley with the random direction of the electron's velocity after the collision. The impact ionization coefficient a gives the number of secondary particles generated by a primary electron per unit length. Chynoweth [37] fitted his measurements with the following simple law for a E L a{x) = aM • exp (8) V E[x) where Ec is called the critical field. It is inversely proportional to the mean free path of the carriers. In a simple model the impact ionization gen¬ eration rate G(x) can then be written as G{x) = a(x)-j(x) (9) NMOS Transfer Characteristic, Substrate Currents and GIDL 47 The substrate current is given by the integral over the generation rate G(x). The problem of this simple model is that in short channel MOSFETs the electric field is both high and inhomogenous. The lucky electron model is often used to model the generation rate G(x): The ansatz was justified by Jungemann et al. [38] who compared the lucky electron model with a full-band Monte Carlo simulation. They found a rea¬ sonable agreement, except in the direct vicinity of the oxide where the lucky electron model failed. It is known that the impact ionization rate in the vicinity of the SI/SIOt interface is reduced. One possible explanation for this reduction is that surface roughness lowers the mean free path of the electrons. This results in a larger critical field and a decrease of the impact ionization coefficient. Another plausible explanation of the reduced surface ionization rate is given by the fact that the rate is proportional to the density of states in the conduction and valence bands. Quantization of the inversion layer diminishes the density of states available, thus effectively raising the energy threshold for impact ionization [39]. It can be shown that the lucky-electron model cannot correctly explain all effects. Once the drain bias is reduced below some critical voltage, the cor¬ responding hot electron current should drop very fast and no longer be any problem. The following measurements disagree with this prediction. In the left picture of Fig. 36 drain- and substrate currents of a very short channel (L=0.1um) NMOS transistor are shown. The currents were mea¬ sured in the subthreshold region, i.e. at a low7 gate voltage (VCTS=:0.2V). The threshold (critical) electron energy for creating an impact ionization should be no less than the silicon band gap (l.leV). Nevertheless, in Fig. 36 the substrate current starts to increase at 0.7V! (Junction leakage was measured to be lower then 40fA at Vds=3V.) The total acceleration voltage for the channel electrons was certainly smaller than 0.9V. Still, some electrons gained an energy above 1.1 eV in the electric field! Despite the prediction of the lucky electron model, no cutoff effect at 1.1V could be observed. Furthermore, as shown in the right part of Fig. 36, a gate current could be measured at a drain voltage of less then 2V! This means that some electrons gained enough energy in the pinch-off region to overcome the 3.2eV high barrier at the silicon-silicondioxide interface. Both experiments suggest that electrons can gain energies larger than qVds. There is no evidence of any critical drain voltage. 48 Some Measurement Methods and Characteristics of MOS Transistors 1 5 2 1 15 2 Vds [V] Vds [V] and Fig. 36 : Dram-, substrate- and gate cur rents for V^-0 2V (left) Vos=L5V (right). Impact-Ioruzation starts at Vjs^O 7V The above experiments show that hot electron effects cannot simply be critical value. turned off by reducing the power supply voltage under some The simple lucky electron model is not adequate to explain the low-volt¬ the age behavior shown in Fig. 36. To address this issue, quasi-thermal- equilibrium approach was suggested [40]. This model assumes that the field. electron gas in the channel is in a quasi-equilibrium with the electric The energy distribution follows Fermi-Dirac statistics and can be character¬ elec¬ ized by an "effective electron temperature" Te. As long as the channel tric field is high enough, a fraction of the total electron population can always gain enough energy to initiate impact ionization or to surpass the oxide barrier. Substrate- and gate currents can be expressed as [41] oc I .exp I , sub J t (10) /?ocC(4x)-//-exp where oxide field, respectively. The effective electron temperature Te is modeled as a function of the peak lateral electric field Em T — Cf/f V (U) where X is the electron mean-free path length. In silicon it is about 7.8nm. C. Hu et al. [40] empirically found the following relation between effective electron temperature T and the electric field E in the channel: Te-9.05 x 10"3-E where Te is in units of K, E in V/cm. In spite of the conceptional differences between the lucky electron model and the quasi-thermal-equilibrium approach the formulations of the hot- electron currents are quite similar. In the lucky electron model the substrate current depends on the maximum electric field Em and can be written as [421: (12) ^jEn^lyEnC^V F \ "•-'/H J 1E-5-1 1E-13 NMOS: (L/W)=0.5m/10u Vgs=3V dox=6nm T=297K 1E-6- •1E-14 *k -a "Nu S 1E-7- *hj •1E-15 > ;j3 = -47.2 "% ; y = -61.4 1E-8- 1E-16 0.25 0.27 0.29 0.31 0.33 0.35 0.37 1/Vds [\T1] Fig. 37 : The dependence of gate- and drain currents on drain voltage. 50 Some Measurement Methods and Characteristics of MOS Transistors The dependence of the substrate current on the electric field shown in Eq. (12) is illustrated in Fig. 37. The substrate current was measured as a func¬ tion of the drain voltage and the values were fitted assuming that Em is approximately proportional to the drain voltage. Furthermore, an expression similar to Eq. (12) is plausible for the dependence of the gate current on the maximum electric field in the channel. This is also shown in Fig. 37. Generation of light in high field regions Another interesting effect is the light emission of silicon. Although sili¬ con is a semiconductor with an indirect bandgap, light emission in diodes and in the pinch-off region of MOSFETs can be detected by means of an emission microscope. In Fig. 38 an example of light emission at the drain side of a NMOS transistor is shown. In the left part of the picture an optical microscope photo of the transistor is shown. The arrow points to the drain side of the big transistor with an area of 20um*200pm. The right half of Fig. 38 shows an emission microscope picture of the same transistor driven in saturation. To the drain a voltage of 2.5V and to the gate a voltage of 1.6V were applied. A relatively intensive light source was detected on the drain side. The emission microscope image was taken with a photocathode which is sensitive to light with wave lengths between 400nm and 850nm (maxi¬ mum at 600nm). This is equivalent to photons with an energy between 1.5eVand3eV. Fig. 38 : NMOS transistor (IJW)=20pm/200pm: Optical microscope image (left) and transistor in saturation (\f=1.6V, Vds=2.5V) under the emission microscope (right). In the pinch-off region (near the drain, i.e. on the right side of the transistor in the picture) bright radiation was observed. NMOS Transfer Characteristic, Substrate Currents and GIDL 51 The emitted broad-band spectrum can be attributed to several possible processes: radiative transition of holes between the light-hole band and the heavy-hole band, radiative recombination between a hot electron and a free hole and Bremsstrahlung radiation due to the scattering of the hot electrons by charged Coulomb centers. C. Hu et al. suggested in reference [43] that the most likely process is Bremsstrahlung: Channel electrons that enter the drain junction scatter at the positively charged donor impurities. Experi¬ ments of Wong [44], however, showed that the intensity of secondary pho¬ ton emission in a NMOS does not change if the high-field region is shifted by an auxiliary gate from the drain end to the channel. Therefore, Bremsstrahlung of hot electrons in the Coulomb field of oppositely charged centers cannot be the dominant mechanism responsible for hot-carrier- induced photon emission. The real physical origin of the emitted radiation still remains a debated issue. Villa et al. [45] believe that a phonon-assisted intraband transition plays a key role in the light emission mechanism. Changing the drain voltage the generated photons were counted with the emission microscope (Fig. 39). The dependences of the photon number and of the substrate current on the drain \oltage are similar: Comparing Fig. 39 with Fig. 37 and Eq. (12) it can be seen that light generation and substrate current depend in the same way on the maximum channel field Em. 100000- NMOS: (L/W)=20/200m d=6nm 10000- T=298K 1000^ tn *-* c 3 O O 100- #Counts(V,)=C-Vf cxp ; C- 13 -10s; ß = -28 10- 0.35 0.4 0 45 0 5 0 55 0.6 1/Vds [V1] Fig. 39 : Dependence ofphoton counts on drain voltage Because of the relation between light generation and substrate current, the emitted light can be used as an indicator for the magnitude of impact 52 Some Measurement Methods and Characteristics of MOS Transistors ionization and degradation in the channel of a MOSFET. Sampietro et al. [46] demonstrated that this correlation allows an estimation of the lifetime of a circuit by measuring its light emission. Gate induced drain leakage current (GIDL) As shown in Fig. 35 the gate induced drain leakage current (GIDL) flows when a positive drain voltage is applied and a negative voltage lies at the gate contact. In Fig. 40 a cross-sectional view of a NMOS is sketched: When a negative voltage is applied to the gate, a strong depletion region is formed under the gate-to-drain overlap region. In the presence of the high electric field, the band of the n-type drain bends upwards and valence elec¬ trons are able to tunnel into the conduction band. The drain collects these electrons causing the so-called gate induced drain leakage current. The holes flow to the substrate [47]. Fig. 40 : Cross-sectional view of the deep depletion region where GIDL is generated (left) and band diagram in the GIDL condition (right). The band-to-band tunneling current density is the highest at the point where the electric field has its maximum and the band bending is larger than the energy bandgap E„. A simple expression for the surface electric field at the tunneling point in the gate-to-drain overlap region was given in refer¬ ence [47] NMOS Transfer Characteristic, Substrate Currents and GIDL 53 where Es is the vertical electric field at the silicon surface and the number 3 gives the ratio of silicon permittivity to oxide permittivity. A minimum band bending of 1.2 eV is necessary for band-to-band tunneling. The tunnel¬ ing current is given by [47] 111 ' K yl L,„ I, = A-Es 'Cxp = A-ES- exp (14) • \ 8 q-fi-E, E V i Figure 41 shows the measured GIDL versus the surface field Es. The sur¬ face field was calculated with Eq. (13). The extracted constant B=18.5MV/ cm lies between 18MV/cm given in reference [47] and the theoretical value of 21.3MV/cm. The gate current was also measured to prove that it has no significant influence on the GIDL: Figure 41 shows that the gate current is at a relatively high surface field more than three orders of magnitude smaller than the drain leakage current. MV > «£ -IE-H¬ ot NMOS: (L/W)=0 3|j/10fj SU 1E-12- 32 dox=50 1E-13- **&*, 1E-14- ig [A] -^ 1E-15-J 1E-16- OE+0 1E-7 2E-7 3E-7 4E-7 5E-7 6E-7 7E-7 3E-7 9E-7 1/Es [cm/V] Fig. 41 : Dependence of GIDL on surface field. As described above, the gate induced drain leakage current is due to band-to-band tunneling in the gate-drain overlap region. The main degrada¬ tion during hot carrier stress takes place in this region. This will be investi¬ gated in chapter 5. The generation of additional interface traps has a strong influence on the band bending and hence on the band-to-band tunneling cur¬ rent. Therefore, GIDL is a good monitor for interface- and oxide charges 54 Some Measurement Methods and Characteristics of MOS Transistors located at the interface or in the oxide above the drain region [80]. (For fur¬ ther notes on this topic see "GIDL-, Gated-diode-, Gate- and Substrate-Cur¬ rents" on page 93.) Flat-Band and Threshold Voltage Flat-band and threshold voltage are two important parameters which depend on the interface trap density. For the threshold voltage several defini¬ tions exist. In connection with the measurements of degradation in chapter 5 they shall briefly be defined. The flat-band voltage VFB is defined as the gate-voltage at which the bands in the MOS-diode are flat. This voltage is different from zero due to the difference in work function /., = VFB ®m--ß-~\p(tx(x)xJx . (15) For a NMOS transistor with a n+-polysilicon gate the gate-sub strate work function difference is given by [48] , (NN kT , where \\-x signifies the silicon intrinsic carrier concentration, Ns the sub¬ strate doping concentration and Np the polysilicon doping concentration. For a NMOS transistor with a n+-poly doping ND=6- I019cm"3, a substrate Flat-Band and Threshold Voltage 55 doping N§=3-10 cm"3, an interface state density Nit~10' ^m"2 and negligi¬ ble oxide charge the work function difference equals about -IV and the flat- band voltage is approximately -1.03 V In textbooks (for example reference [35]) the threshold voltage is defined as the gate voltage at which strong inversion starts, i.e. at which the band bending is so strong that the midgap crosses the Fermi level. Heavier substrate doping requires a greater band bending to reach strong inversion. The threshold voltage increases therefore for higher substrate doping. The threshold voltage is the sum of the flat-band voltage, the voltage drop across the oxide and the surface potential \|/s inducing the band bending in the semiconductor = VT VrBJ^~ + ¥s . (17) Qs stands for the total number of charges per unit area in the semiconduc¬ tor. Oxide charges and interface traps cause a shift in flat-band voltage and therefore shift also the threshold voltage. Experimentalists have introduced different and more practicable defini¬ tions of the threshold voltage. One possibility is to measure the transfer characteristic of the transistor and extrapolate the linear portion of the drain current. Another widely used method is to define the threshold voltage as the gate voltage where a certain drain current flows. Throughout this work the threshold voltage was defined as follows: w V @ v • ~- = v- = !•! 0~7 and V = 100/wV vti, *V // [A] u (18) L Temperature Dependence of the Threshold Voltage Temperature affects device parameters and performance, especially mobility, threshold voltage, and subthreshold characteristics. It is well known that, as the temperature decreases, the (absolute) threshold voltage increases about 2-4mV/degree. (Measurements are shown in reference [491, 56 Some Measurement Methods and Characteristics of MOS Transistors for example). The main reason for this behavior is the fact that the Fermi level lies nearer to the band edge at lower temperatures. Besides, also the work function difference depends on temperature (see equation (16)). The temperature dependence of the threshold voltage of a NMOS transis¬ tor was measured. After increasing the temperature from room temperature to 35°C (AT=10K), the threshold voltage decreased 22mV (see Fig. 42). Consequently, it is important to control the temperature during accurate threshold voltage measurements. 3.00E-6- NMOS: (L/W)=1]j710u dox=6nm Vds=0.1V 3.00E-7- 0.8 0 81 0.82 0.83 0 84 0.85 0 86 0 87 0.88 0.89 0.9 Vgs [V] Fig. 42 : Dependence of threshold voltage of a NMOS transistor on temperature. Measurement of Polysilicon Doping and Gate Depletion Effects Heavily doped polycrystalline silicon (also called polysilicon) is exten¬ sively used as gate material for MOS transistors. Despite its high doping and its polycrystalline structure polysilicon behaves similar to a silicon single crystal and the concept of energy bands makes sense. Depending on the electric field its bands bend and depletion or even inversion is possible. When polysilicon is used as a gate material, poly band bending causes a reduction in the effective voltage across the gate dielectric. For ultrathin oxides this can be significant compared to the applied voltage. The finite polygate capacitance CP decreases the gate-to-source capacitance Cas and Measurement of Polysilicon Doping and Gate Depletion Effects 57 lowers the transconductance of the transistor. When the lifetime of thin oxides in an accelerated time-dependent breakdown test is estimated, the polysilicon depletion effect can cause considerable errors (compare with reference [50]). One reason for a large polydepletion effect is often the insufficient activa¬ tion of dopants in the polysilicon due to processing at a too low temperature. Thus the active doping concentration is different from the total concentra¬ tion. A technique to extract the electrically active doping concentration Np will be presented in the following section and the potential drop over the poly-gate will be estimated in dependence of the gate voltage. A method for measuring the active doping of a polysilicon gate was intro¬ duced by Ricco et al. [51]. It assumes uniformly doped polysilicon and a complete depletion of the gate surface toward the channel. Furthermore, it is assumed that the following relation between the gate-to-source C(TC and the poly-depletion capacitance Cp is valid I_ _L+4>v (19) or The poly-depletion capacitance CD is then given by ' ' ^L ^ p C = A = (20) Together with dQD/dVgs=2Cgs the derivative of the inverse of Cp is obtained from d 2C (21) dVg^ £Si-qNp-A2 Because of Eq. (19) we can also write for the derivative of the inverse of a 58 Some Measurement Methods and Characteristics ofMOS Transistors rC d C -C \ZJ>J S1- (22) dV" ir1 Comparing Eq. (22) with Eq. (21) the following expression is obtained C 1 (23) 4CÇ 8SiqNpA- Measuring the gate-to-source capacitance and calculating the left hand side of Eq. (23) allows to determine the active polysilicon doping Np. In the lefthalf of Fig. 43 the measured gate-to-source capacitance is shown. In the right part the estimation of the active polysilicon doping calculated with Eq. (23) is plotted. In the region where the assumptions are satisfied the extracted dopant density reaches a constant value. The value obtained is Np=6-1019cmv\ which is a reasonable result. 1E+21- Np=6E19cmA-3 c « x»fo amm oocm® ruj,iju o—ctrooo o mm -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 vgs [V] vgs [V] Fig. 43 : Gate-tO'Source capacitance of a NMOS transistor (left) and estimation of the active polysilicon doping calculated with Eq. (23) (right). The voltage drop in the polysilicon can be expressed by (see reference [52]) Fowler-Nordheim Current 59 Fl . F2 p 2-q-£s-N (24) p In Fig. 44 the voltage drop Vp over the polysilicon is shown as a function of the gate voltage for Np~6-10 cm°. Polydepletion can strongly influence the transconductance of a transistor. The maximum possible voltage drop is given by the silicon bandgap (1.12V at 300K) due to pinning of the Fermi level at the band edges. Fig. 44 : Effect ofpolysilicon depletion. Fowler-Nordheim Current This chapter looks at Fowler-Nordheim (FN) tunneling through thin oxide layers. In electrically erasable read only memories (EEPROMs) the tunneling of electrons is exploited to charge and discharge the floating gates by applying a voltage to the control gates. However, the tunneling through an oxide generates traps in the oxide and at the interface. As a result the devices deteriorate. Fowler-Nordheim injection is therefore often used in reliability studies of thin oxides. 60 Some Measurement Methods and Characteristics of MOS Transistors Tunneling is a quantum mechanical process. When the wave nature of the electrons is taken into account, the triangular energy barrier of the oxide between metal and semiconductor leads to Airy functions as solutions of Schrödinger's equation. The interference between wave functions makes the tunneling current oscillate. These oscillations were measured and they will be compared with an exact calculation of the tunneling probability. The last part of this chapter discusses the dependence of the tunneling current on the direction of the applied field and on the dopant type. It will be shown that even tunneling of valence electrons is possible. Introduction Figure 45 shows a sketch of the band diagram of a NMOS transistor with n+-polysilicon gate. When the potential drop over the oxide Vox is smaller than the barrier high p-silicon " n Pohsilicon Fig. 45 : Schematic band diagram of FN-iunneling from a NMOS inversion channel. On the right side of the oxide the p-silicon is inverted and on the left side the n+- poly is depleted. The image-force barrier lowering effect is sketched too. Fowler-Nordheim Current 61 Figure 46 shows a measurement of the onset of the Fowler-Nordheim cur¬ rent for four different oxide thicknesses. Electrons tunneled from the inver¬ sion channel through the gate oxide into the n+-doped polysilicon of large NMOS transistors (100pm x 100pm). The values of the three different oxide thicknesses (105Ä, 150Â, 265Â) were determined by measuring the gate- channel capacitance. The large areas minimize edge effects. Polysilicon depletion and quantization of the inversion layer were not considered, because these effects are relatively small. 5E-3 0 2 4 6 8 10 12 14 16 18 Vgs [V] Fig. 46 Fowler-Nordheim current for different oxide thicknesses. The WKB-Approximation This section presents some approximate expressions for the tunneling current. In general, the tunneling current through a barrier is obtained by multi¬ plying the probability that the initial state is occupied times the probability that the final state is unoccupied times the penetration probability of the par¬ ticles through the barrier and finally by integrating over all particle energies. For a metal-insulator-metal structure this leads for the free-electron model to the following expression (see Eq. 7.17 on p. 59 in reference [53]) 62 Some Measurement Methods and Characteristics of MOS Transistors J = jdExD(Ex)N(Ex) f ( \ \ 1 + exp kT (25) 1 x} ' If Er- V Ex —qV 1 + exp kT 7 J Energy and momentum conservation laws are implicitly assumed. Unfor¬ tunately, both of them are generally not conserved in a tunneling process. For the penetration probability through a trapezoidal barrier several expressions were given in the literature. In 1928, Fowler and Nordheim used the WKB approximation to derive their well-known formula for the tunnel¬ ing current: ß /r,v = C-E0vexp E, (26) q A 2m & C = . ß Sxh® 3q7) Barrier lowering due to the image force is neglected and T=0 is assumed. Eq. (26) fits also very well with measured data of the tunneling current. If the effects of the image force on the barrier is taken into account, two correction factors are introduced into Eq. (26). Good and Müller [55] showed a comprehensive model including image barrier lowering and tem¬ perature effects in a WKB approximation. Their most important results shall now be reviewed. The model assumes a metallic electrode where the conduction electrons form a gas of free particles following Fermi-Dirac statistics. An electric field F is applied to draw the electrons out of the metal. The image force lowers the potential barrier: An electron outside the metal is attracted to the metal as a result of the charge it induces on the surface. In addition, it is assumed that the electrons inside the metal essentially remain in equilib¬ rium, although some are escaping from the metal. As the energy of the elec¬ trons is appreciably smaller than the barrier height, the transmission coefficient can be studied in a WKB approximation. For T=0 the total elec- Fowler-Nordheim Current 63 trie current tunneling through the insulator is given as follows 4\2m-4V cf _ WE • J(0,E) = - - E2 exp v(v) : v = (27) 87T//-d>-r(y) 3tiq E O where t(y) is a slowly varying function with values lying between 1.00, and 1.11. The function v(y) is given by - I + \ 1 V" _ A/ v(y) = E(k)-\\-d{-y- \K(k) :k--2it£ (28) i+Vi-r The range of v(y) is between 0 and 1. K(k) and E(k) signify the complete elliptic integrals of the first and second kinds respectively nil K(k)=j J^d(p i Jl-Âr-sin- o v = E(k) U\-k2 sin2 At finite temperatures the energy of some electrons lies above the Fermi level. These electrons arc more likely to penetrate due to the increase in the transmission coefficient with increasing energy of the carriers hitting the barrier. Therefore, three types of electron emission must be distinguished: temperature emission at high temperatures and low fields as described by the Richardson equation, field emission at low temperatures and high fields (Fowler-Nordheim current), and temperature-and-field emission at interme¬ diate temperatures and fields. A condition for the temperature and field range where the emitted electrons mainly have energies below the Fermi level is given in the following relation (30) E>8.83-lO'A0-77 . 64 Some Measurement Methods and Characteristics ofMOS Transistors For a barrier height =2.93eV measured form the Si conduction band edge to the Si02 conduction band edge, and for T=300K, Eq. (30) postulates for Fowler-Nordheim tunneling an electric field E stronger than 4.5MV/cm. As long as Eq. (30) is fulfilled, the total emitted current can be written as = = J(T,E) J(0,E)-^ ;z ^L.2V2w^O-r(v) . (31) sm: nq h Figure 47 compares the calculated Fowler-Nordheim currents for T=0K and T=500K. Obviously, the influence of the factor z/sin(z) in (31) remains small for moderate temperatures. Moreover, both curves can be well fitted with the simple Eq. (26). 0 = 2.93. V (fSi0i * J at T=0K -10 m = 0.42 • nu- J at T=298K -20- -30- tu cf -40- ^(7 = 0) = 222 10s — ;C(T = 0) = 5 10 m -50- ß(T = 500) = 206 108 — : C(T = 500) = 1 5 m -60 o o o ay O) OÎ CD a> + ' UJ 1 Ï ', , UJ LU UJ UJ UJ LU UJ UJ m o CM ^1- CD CO q O o o o d T— C\J ^f CD CO 1/E m ox I /V] Fig. 47 : Fowler-Nordheim plot of the calculated currents at T=0 and T=500K. The cal¬ culations were done using Eqs. (27) and (31). Measurements of the Fowler-Nordheim tunneling current show that in the conduction band of the oxide the free electron mass must be replaced by an effective electron mass m\ Equation (26) allows an estimation of m\ but it is valid only under certain assumptions. With the measurement shown Fig. 48 the two parameters C and ß were determined. Whereas ß can be esti¬ mated within a relatively small error (it is just the slope in the F-N plot, i.e. Fowler-Nordheim Current 65 logJ/E" vs. 1/E), the estimation of C is quite unsure. (In the literature how¬ ever, C is sometimes given with a high accuracy, e.g. in reference [52].) If the barrier height 05lOi = 2.93.V X o m = 0.42 UJ mQ 3 dOT=250A dlA=IOOAand 150A -60- O O) CT) 0) CT) CT) + '. LU 1 i ï LU UJ LU LU LU LU LU q LU LU O CM "t CD CO O O O O d CM "fr co t-\i T U_> CO 1/E0X [m/V] Fig. 48 : Measurement of the two parameters of the Fowler-Nordheim formula when electrons tunnel from the inversion layer through the oxide into the gate. Three different oxide thicknesses (100A, 150A and 250Ä) were measured. Tunneling Current Oscillation The WKB-approximation of the Fowler-Nordheim current through a tri¬ angular barrier (31) neglects the fact that an incident electron wave can interfere with an electron wave reflected at the interface. The interference needs coherent electron waves. When electrons scatter, they lose their coher¬ ence. Thus tunneling current oscillations can only be observed in thin oxides. (<70A) Figure 49 shows the measured tunneling current through a gate oxide of about 60 thickness: In fact a slight oscillatory component can be observed. Maserjian [58] was the first who published this effect at a CrAu/SiOo/Si structure with an oxide thickness of 40À. 66 Some Measurement Methods and Characteristics of MOS Transistors In this section an 'exact' expression for the penetration probability through a triangular barrier will be derived. Nevertheless, in this calculation the image force effect will be neglected. The expression was published already 1966 by Grundlach [54J. He noticed in his comprehensive article that, whereas in the WKB approximation only the tunneling distance b-a in Fig. 45 is considered, in an exact solution the full distance d-a must be taken into account. Electrons with a long free wavelength can interfere in the d-b region. The width of this region depends on the electric field over the oxide. As the field changes, different interference minima and maxima in the trans¬ mission probability occur. Because of a small error in Grundlach's original article (z should be z in Eq. (18) of reference [54]) the most important steps of the calculation shall be repeated on the following two pages: Neglecting the influence of the image potential the potential energy in the three regions is: 0 in region I U(x) = \ (h + E. - (qV + AÔ)-. in region 2 (32) ' d -qV in region 3 (J)! signifies the potential barrier between region I (a metal) and the insu¬ lator (region 2), Et- the Fermi energy in the region 1, V the applied voltage, q the elementary charge, A^^--^ the difference between the two barrier heights and d the thickness of the insulator. Assuming plane waves in the two metals the incident wave function \\i1 and the transmitted wave function \\f^ are given by ^^ ii/,(.r) = A/,X + ^~'V ; with k, = ti (33) ' . /.m.\ r, -+ nv \ , _^'H^+qV_ = ,'V .^kv y/3(x) A,c'hx ;withk, h where nij are the effective masses and Ex is the kinetic energy of the inci¬ dent particle. These wave functions are solutions of Schrödinger's equation. Fowler-Nordheim Current 67 In region 2 (the insulator) Schrodinger's equation is transformable into the Airy differential equation \|/"-z\|/=0. The form of the wave function in the insulator is therefore y/, (:) = A,A/(r) + B^Bi(z) ; "Vl (34) 2m, x with z : d i% Ef -E, -(qV + A(f) h(qV + Aç) The Airy functions Ai(z) and Bi(z) are defined e.g. in reference [59]. According to the common matching procedure the wave functions \|/ and their derivatives have to be continuous at the interface. This leads to four equations for the five variables A^Ai.A^.Bi and Bi. As a result an expres¬ sion for the relation between two of them can be derived. The penetration probability D is the current density of the transmitted wave divided by the current density of the incident wave k A, D = (35) k A Using the identity for the Wronski determinant (Ai'Bi-Bi'Ai)=l/7t the expression for the penetration probability can be written as L Z) = \- (z0)B, {zf)~Ai (zAB, + -j k, n1 v*. {A, (zf\ {Ai(z{))Bi(z,)-Ai(zJBi(z0)} 06) (k r i Y + | -f[Ai(zf)Bi (:0)~Ai (z0)Bt(z;)\ + Ai(zfBi (zf -Ai (zf)Bi(z0) where z' is the derivative of the function z(x) given in Eq. (34), z0~z(0) and zs=z(s). Ai' and BF are the derivatives of the Airy functions. Grundlach showed that in the Fowler-Nordheim case the exact penetra¬ tion probability given in Eq. (36) can be approximated by the following expression: 68 Some Measurement Methods and Characteristics of MOS Transistors 3/2 \ 4,/2m. (h+Ef-E, &-K- exp 3fi qV + A Z) = (37) f , ^3/2^ CJV- -— 2J- -1—-J- — + I + sin -- d fa + E. 3/) qV + A(p E.M+E,-E,- qV-O-^-E. + Ex\ AA-f1k, f with K : k, 0.+E, 0, + E The transmission probability D has a maximum when the sinus term in Eq. (37) equals -1 and a minimum when the sinus is +1. Therefore, the fol¬ lowing simple condition for the maxima can be derived qV-Ef + Ex -0, 472,,., j,. -r 3^ = 2tt ;n = 0,1,2... (38) 3/-/ C7V + A0 4 To illustrate these formulae the tunneling current through the thin oxide of a NMOS transistor was measured and compared with the calculation. In the measurement a positive voltage (relative to the substrate) lied at the gate of the transistor. Electrons tunneled from the inversion channel through the oxide into the n+-poly gate. A transistor with a large gate area was used to minimize edge effects. Source and drain contacts were grounded in order to deliver enough minority carriers into the channel. The current was calculated for T=300K with Eq. (25). For the penetration probability the exact expression given in Eq. (36) as well as the approxima¬ tion given in Eq. (37) were used. The results are shown in Fig. 49 and Fig. 50. In Fig. 49 the usual Fowler-Nordheim plots of the measured and calcu¬ lated currents are drawn. The parameters ß and C of Eq. (26) were fitted to the measured data and their best values are presented in the graph. In Fig. 50 the exponential dependence of the Fowler-Nordheim current was subtracted from the measured and the calculated currents to zoom into the oscillatory part. Fowler-Nordheim Current 69 -30- NMOS: (L7W)=200Li/200|i measured Vs=Vd=Vb=GND; Vg>0 calculated "exact" -35- -40- LU -45- ( 1} ^„r^^m'exp -50- \ E,nJ C-2-10"-4 ; £ = 238 10' — V- m -55- 8.0E-10 9.0E-10 1.0E-9 1.1E-9 1.2E-9 1.3E-9 1.4E-9 1.5E-9 1.6E-9 1/Eox tm/V] Fig. 49 : Small oscillations in the tunneling current can be observed: Measured values (circles) and with Eqs. (25) and (36) "exact" calculated values (bold line) are plotted. NMOS: (L/W)==200li/200ll measured 1.3- Vs==Vd==Vb==GND; Vg>0 - calculated "exact" 0.8- 0.3- 3 if -0.2- -0.7- '/)(, - 0 I0 m0. m, - 0 42 mn. m, = 0 2 ///„, md -04 m0 If - 1 2 cV. . -1.2-" i'" ' i i i i i i |' 1 i 1 3.5 4.5 5.5 Vgs [V] Fig. 50 : Current oscillations: The measured values (crosses), the with Eqs. (25) and (36) 'exactly' calculated values (bold line) and the with Eq. (25) and (37) approximately cal¬ culated values (thin line) are plotted. The parameters used in the calculation are printed in the inset of Fig. 50. The effective transversal electron masses in the p-type substrate and in the n+-polysilicon were assumed to be 0.19m0 and 0.2m0 respectively. For the 70 Some Measurement Methods and Characteristics of MOS Transistors effective electron mass in the oxide the value given by Lenzlinger and Snow [571, mox=0.42m0, was used. The Fermi level in the inversion layer was sup¬ posed to lie approximately 1.2eV above the valence band edge and for the two barrier heights a value of 3.1eV was taken. A best fit was obtained for an oxide thickness of about 50Ä, which is a reasonable value for the physi¬ cal oxide thickness. A C-V measurement resulted in about 60A for the elec¬ trical thickness of the oxide. The difference between measured and calculated oxide thicknesses can be explained by the polysilicon depletion effect (see "Measurement of Polysilicon Doping and Gate Depletion Effects" on page 56) and by the finite distance of the inversion charge from the interface (compare with "Quantization of the Inversion Layer'" on page 131). The Various Components of the Fowler-Nordheim tunneling current The simple Eq. (26) for Fowler-Nordheim tunneling assumes that the cur¬ rent is a unique function of the oxide field for a given oxide thickness. How¬ ever, this equation was derived for tunneling between two metals. In a metal-oxide-semiconductor structure the density of states on the metal or polysilicon side is different from the density in the silicon substrate. This leads to a dependence of the tunneling current on the direction of the applied electric field. In addition, until now it was always assumed that only conduction band electrons tunnel. Still, \alence band electrons are also able to tunnel through the barrier when the electric field is high enough. These effects will be shown in the following section. To distinguish the conduction-band from the valence-band electron tun¬ neling, the carrier separation technique was applied. Since C. Hu et al. [4] introduced this technique, experimentalists used it often: Compare with ref¬ erence [60], for example. In the carrier separation technique, substrate-, source-, and gate-currents are separately measured and the drain contact is not connected. Depending on the bias conditions each current measures another contribution to the tunneling current. For example, when the gate of a NMOS transistor is positively biased and the source and substrate are grounded, the source current measures the electron current tunneling from the inverted Si substrate into the gate and the substrate current measures the hole current flowing into the substrate, which is equal to the valence elec¬ tron tunneling current. In Fig. 51 the gate-, source- and substrate-currents were measured in NMOS and PMOS transistors for positive and negative gate biases. In Fig. 52 and Fig. 53 band diagrams of the four cases are sketched to explain qualitatively the measured effects. Fowler-Nordheim Current 71 0- PMOS: /L/W)=200u/200|i NMOS: (IVW)=200li/200m ^ dox=60A dox=60 ^<"-'"" ' < -4- < -4- -Jtt-'tf Je,-Jb E E ACCUMUATION o Accumula tion -6- ^ -6- Js < -> en -8- en -8- A. Q o -10- -10- ^fn^yy"^ a) "' ...... , .... I -12- -12- t T" | , 5 55 6 6 5 / -2 -2 5 -3 -3 5 -4 -4 5 -5 -5 5 -6 -6.5 -7 : 0 3 35 4 45 Vgs [V] Vgs [V] PMOS (L/W)= 200m/200|.l 04 NMOS:o(LAV)=200u/20()u ""' dox=60 * c? -2 dox=60A < < ~4 c h Inversion E IWFRSION o Js.-Ts o 3 -6 -6- h-A cn en -8 o -a. o / 10 -10H ,' ^ys^V^v^ c) WI^^^ÄÄ/^ d) -12 -12 -7 2 25 3 35 4 4 5 5 55 6 65 -2 -2 5 -3 -3 5 -4 -4 5 -5 -5 5 -6 -6 5 vgs [V] Vgs [V] and PMOS transistors F/g. 51 : Carrier separation measurement at NMOS for positive and negative gate bias. d) ••••-*§- -?r - n-Si © e) ^ COO V»*»* •••V • OOOl p+-poly i. NMOS: AcciMllAriON PMOS: ACCUMULATION !/ inter¬ Fig. 52 : Band diagrams of a MOS-diode (a and d), along the semiconductor-oxide face (c and f), and cross-section (b and e) of a NMOS (left) and of a PMOS (right) tran¬ sistor in accumulation. 72 Some Measurement Methods and Characteristics of MOS Transistors Inversion NMOS1 Iwersion PMOS: Fig. 53 : Band diagrams of a MOS-diode (a and d). along the semiconductor-oxide inter¬ face (c and f), and cross-section (b and e) of a NMOS (left) and of a PMOS (right) tran¬ sistor in inversion. Now we will briefly discuss the four different cases comparing the mea¬ sured currents with the band diagrams and cross-sections: NMOS in accumulation In the first measurement a NMOS transistor is driven into accumulation, i.e. a negative gate voltage is applied (see Fig. 52, left). Electrons from the n+-doped polysilicon gate tunnel through the triangular SiO^barrier into the accumulated p-substrate. Some electrons are able to transfer their energy to deep valence-band electrons. (Compare with reference [4]). Such an elec¬ tron is transferred to the lowest available electron energy state, that is, the conduction band edge, thereby creating a "hot" hole (diagram (a) in Fig. 52). Some of these hot holes tunnel back into the oxide and can there break a Si-0 bond creating an electron trap. The tunneling electron and the gener- ated electron can now drift into the source causing an electron current into the source contact (diagram (c) in Fig. 52) or they can recombine with an accumulated hole causing a hole current out of the substrate contact (see cross-section (b) in Fig. 52). About ten times more electrons recombine than drift into the source. This explains qualitatively the three measured currents shown in section a) of Fig. 51. Fowler-Nordheim Current 73 PMOS in accumulation In the second measurement a PMOS transistor is driven into accumula¬ tion, i.e. a positive voltage is applied to the gate (see Fig. 52, right). Elec¬ trons from the accumulated n-substrate tunnel through the triangular barrier into the p+-polysilicon. Electron current out of the substrate contact replen¬ ishes the tunneled electrons (diagram (d) of Fig. 52). This explains the nearly equal absolute value of gate- and substrate currents in section b) of Fig. 51. To explain the negative source current it was first assumed that holes tunnel from the p+-polygate through the barrier in the channel and drift into the source. A second measurement at a PMOS transistor with the same channel width and a ten times smaller channel length showed exactly the same source current. Therefore, the source current must be an edge effect: Minority carriers (electrons) from the p+-source tunnel into the gate causing the measured negative source current (see diagram (e) of Fig. 52). NMOS in inversion Next, a NMOS transistor is driven into strong inversion, i.e. a high posi¬ tive voltage is applied to the n+-polysilicon gate. Electrons tunnel out of the inversion layer through the triangular barrier into the gate. These electrons are then replenished by electrons from the source flowing into the channel (see diagrams (b) and (c) of Fig. 53). This explains the nearly equal absolute value of the gate- and source current in the measurement (see section (c) of Fig. 51). Increasing the positive voltage at the gate further enables the tun¬ neling of valence band electrons into the gate as well. Compared with the conduction band electrons the valence band electrons sec a 1.1 eV higher barrier. A tunneling valence electron leaves a hole behind in the valence band. This hole drifts out of the substrate causing a negative substrate cur¬ rent (see measurement (c) in Fig. 51). PMOS in inversion Finally, the tunneling into the inversion layer of a PMOS transistor was considered: A PMOS transistor was driven in strong inversion, i.e. a high negative voltage at the p+-polysilicon gate attracts holes from the n-substrate creating a hole-channel. In this case the tunneling current is limited by the supply of electrons from the p+-poly. First, only a few electrons are in the conduction band of the poly and the valence electrons see a high barrier. A further increase of the negative voltage at the gate causes poly-depletion and, for still higher gate voltages, poly-inversion. At that voltage conduc¬ tion-band electrons are available for the tunneling into the substrate [60]. Some tunneling electrons are able to transfer their energy to a deep valence- 74 Some Measurement Methods and Characteristics of MOS Transistors band electron, creating a hot hole. These holes are accelerated against the oxide and a few of them are trapped in the oxide causing oxide damage. The rest of the hot holes thermalise to the valence band edge and then drift through the hole channel into the source. The tunneling electron, finally, flows into the substrate contact causing the positive substrate current mea¬ sured in section (d) of Fig. 52. Fowler-Nordheim tunneling in MOS transistors and diodes depend there¬ fore not only on the oxide field, but also on the direction of the applied field. Furthermore, in degradation experiments it is necessary to remember that electrons tunneling through an oxide can generate hot holes whose contribu¬ tion to the degradation must be taken into account. Determination of the Oxide Thickness The thickness of a gate oxide is an important parameter in device charac¬ terization. Its measurement, however, is far from easy. Only a few direct methods exist: For example, the real physical oxide thickness can be mea¬ sured by means of transmission electron microscopy or optically by ellip- sometry. In the literature different indirect methods for the determination of the 'effective' oxide thickness were reported. All are based either on capaci¬ tance or on Fowler-Nordheim tunneling measurements. The obtained 'effec- live' values are normally higher than the real physical oxide thicknesses. Possible reasons for the differences are the polydepletion effect and the finite distance of the inversion layer charge from the interface. In the follow¬ ing chapter some electrical methods shall be discussed. The classical method for estimating the oxide thickness of a MOS-tran- sistor is to measure the gate-channel capacitance Cec and extract the thick¬ ness dox with the simple formula dpx=——JL . (39) The gate-channel capacitance is determined as shown below (see "Mea¬ surement of the Mobility" on page 85) by measuring the displacement cur¬ rent when a ramp voltage is applied to the gate (quasi-static CV- Determination of the Oxide Thickness 75 measurement). However, this method is only accurate for thicker oxides (dox o > 60A). The discrepancy between the electrical and the physical/optical characterization techniques is due to the effects of finite thickness of inver¬ sion layer (including quantum effects), charge trapping and polysilicon depletion. Values obtained from CV-measurements consistently overesti¬ mate the thickness. Several other methods to electrically measure the oxide thickness have been suggested. In reference [52] the thickness and the polydepletion effect were extracted by fitting Fowler-Nordheim tunneling current measurements using the oxide thickness dox and the active polysilicon doping Np as param¬ eters. For these fits it was assumed that barrier height, flat-band voltage and the parameters C and ß of the F-N current expression are precisely known. The authors claim that a difference of 0.5 A can be resolved. Quantum effects shift the accumulation and inversion charge centroid away from the Si/Si02 interface, which results in an increase of the equiva¬ lent oxide thickness (compare with "Quantization of the Inversion Layer" on page 131). Therefore, Rios and Arora [61] combined a numerical solu¬ tion of a first order QM-corrected Poisson equation with a measurement of the capacitance of a large area MOS capacitor in strong accumulation. They showed that in strong accumulation the capacitance becomes independent of bulk and polysilicon doping, oxide charges and fast interface states. Irene et al. [62J and [63] tried to determine the oxide thickness by fitting tunneling current oscillations. This method is especially suitable for thinner oxides, because on the one hand capacitance and optical measurements become inaccurate for thin oxides and on the other hand coherent interfer¬ ence of electron waves can only be observed in thin oxides. Irene et al. used the fact reported first by Alferieff and Duke [64J that the transmission coeffi¬ cient exhibits local maxima near the zeros of Ai(-c,0) with £,0 2m£\''{E1-^Ei' ' (40) so Tr F A measurement of the oxide field at which the maxima occur allows an estimation of the oxide thickness. An even simpler way is to use Eq. (38). If we assume in addition that the kinetic energy of the tunneling electrons Ex is equal to the Fermi energy Et-, the oxide thickness can be estimated by 76 Some Measurement Methods and Characteristics of MOS Transistors _,3^ 1 3f = + ^7^% ;n = 0,l,2,...; I(Vn) max. ^4/7 4 2tn2(qVn-4 (41) 3 ( l) h qVp + AÔ / I V =min. P- 5-T ; p= 1.2,... ; v lia <2mi{qVp-^) Vn and Vp signify the gate voltages where a maximum (respectively min¬ imum) in the tunneling current occurs. (J)} is the barrier height of the elec¬ trode where the electrons tunnel into the oxide and m2 is the effective electron mass in the oxide. Figure 54 shows measured oscillations in the tunneling current through the gate oxide of a NMOS transistor. The electrically measured oxide thick¬ ness is approximately 60 À (calculated with eq. (39)). Using eq. (41) and the voltages Vn and Vp indicated in Fig. 54 the estimated physical oxide thick¬ ness is about 5IÄ. The difference in the two \allies is probably due the finite distance of the inversion layer from the interface. On the other hand we should always keep in mind our assumptions for the calculation of the tun¬ neling current, these were: plane waves on both sides, elastic tunneling, the effective mass model in the silicon and oxide, and no image barrier lower¬ ing. U D- V=4 075 NMOS' (L/W)=20u/200M 0.5- Vs=Vd=Vb=GND, Vg>0 0 4- 0.3- >> doV=51A ÉÉT 0.2- ~3 r oi- V=5 1 V=5 55 ~&, 0- *°%} \ V=4 65 -0.1- -0.2- er 1 ' -0 3- I I , I 35 45 5 5 5 Vgs [V] ' Fig. 54 Oxide thickness estimation using the maxima and minima m the tunneling cur¬ rent oscillations. The Charge Pumping Technique 77 The Charge Pumping Technique The density of surface states at the silicon/silicondioxide interface is one of the most important characteristics of a MOS transistor. In fact, the exist¬ ence of these states in the silicon band gap was the main reason why MOS - transistors did not work for a long time after their invention. Surface states can trap charges and change the threshold voltage. If there are too many states, the band bending at the surface of the semiconductor becomes so strong that the transistor cannot be controlled by the gate potential. Several techniques for measuring the interface state density were sug¬ gested in the past (e.g. capacitance-voltage curves combined with a simula¬ tion [65], deep-level transient-spectroscopy (DLTS), 1/f noise, etc.). The most successful of these techniques, however, is the measurement of the charge pumping current. The charge pumping (CP) technique allows the measurement of the distri¬ bution of the interface states around mid-gap. (It is well known that the den¬ sity of interface states at energies close to the band edges is much higher. Unfortunately, these fast traps cannot be measured by charge pumping.) The technique is based on the recombination process at the Si/Si02 interface involving the surface states. The required equipment is very simple indeed. A picoamperemeter and a pulse generator are readily accessible and this is one of the reasons why the charge pumping technique quickly became the standard method for the determination of the interface state density. The Conventional Charge-Pumping Technique Though the charge pumping technique was already introduced in 1969 by Brugler and Jespers, it was first correctly explained in 1984 by G. Groe- seneken et al. [66J. The influence of degradation (generation of additional interface states) on the CP current was described later in 1989 by the same authors [67]. The CP technique works as follows: The source and drain of the transistor are connected together and held to ground or to a reverse voltage (relative to the substrate). To the gate contact a trapezoidal pulse is applied. Keeping the amplitude of the pulse constant the base level is shifted from a negative to a positive voltage and the averaged substrate current is measured. Figure 55 shows the measured CP currents of two NMOS transistors with different gate areas. 78 Some Measurement Methods and Characteristics ofMOS Transistors 4.0E-11 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0 -0.5 0 O.i Vb[V] Vb[V] Fig. 55 : Two charge pumping curves measured at two NMOS transistors with different gate areas. Indicated is also die approximative fiatband voltage and the difference of threshold voltage and pulse amplitude. To understand the shape of the curve in Fig. 55 three different operation regions should be distinguished: 1) The base level of the gate pulses (Vbs) is lower than the flat-band volt¬ age and the top level of the pulse lies higher than the threshold voltage. The channel is then pulsed between accumulation and inversion. When the tran¬ sistor is pulsed into inversion, electrons flow from the source and drain into the channel where some of them are captured by surface states. When the channel is driven back into accumulation, the mobile charge drifts back into the source and drain and the trapped charge recombines with the majority carriers from the substrate giving rise to a net substrate current. This current is the so-called charge-pumping current. It is proportional to the frequency f, the gate area A and the mean surface-state density Djt (see Eq. 2 of [67]): = • Ir D -2-q-f'A-kT-In v.. ,>on • cr if P v em. h (42) The G stand for the capture cross sections for electrons and holes and approximately equal 2E-16 cm", tcm are the emission times for electron and hole emissions from the interface states into the conduction or valance band. The Charge Pumping Technique 79 vth is the thermal velocity (=10 cm/s) and n; the intrinsic carrier concentra¬ tion in silicon. 2) When the base and the top level are both lower than the flat-band volt¬ age or when they are both higher than the threshold voltage no net current flows because no recombination of trapped electrons with holes takes place. 3) When the top or the bottom of the pulse lies between the flat-band and the threshold voltage some electrons can recombine with the backfloating holes and a CP current can be measured. The rising and falling edges of the measured CP characteristic are not symmetrical. This asymmetry can be explained by the lateral variation of the threshold and flat-band voltage near source and drain due to the strong change of the impurity profile near the junctions. The fast interface traps located at a certain position in the channel or in the source or drain region will therefore only contribute to the CP current if the gate pulse is such that the base level of the pulse is below the local flat-band voltage, while the top level is above the local threshold voltage (compare with Fig. 56 and refer¬ ence [68]). Fig. 56 : Illustration of the local distribution of the threshold and the flatband voltages and the region of recombination (R). It is important to note that the threshold and the flat-band voltages are defined here in a slightly different way: The "local threshold voltage" is defined as the gate voltage required to induce a certain density of minority carriers and the "local flat-band voltage" as the gate voltage required to induce a certain density of majority carriers at each position. Real values of these densities should be defined such that the interface states can capture holes and electrons during the inversion and accumulation periods. The time constant for electron capture can be calculated with the following formula (see Eq. 3 of reference [67]) 80 Some Measurement Methods and Characteristics of MOS Transistors *«= • (43) , „ „ vth-v„-nfl If we assume 2-10 cnr for the capture cross-section, 10 cm/s for the thermal velocity and a pulse frequency of 500kHz, a electron density of at least 5T014 cm"3 is required to invert the channel. With the charge pumping technique one can also determine the energy distribution of the interface states over the bandgap. By applying trapezoidal pulses with variable fall times while keeping the rise time constant, the energy range in the upper half of the bandgap is scanned and by varying the rise time while keeping the fall time constant, the energy states in the lower half of the bandgap are measured. The following equation (Eq. 34 of refer¬ ence [66]) is valid for the lower half of the bandgap >(e\- t, cucp (44) lAf-'x) q-A-kT-f dt, A similar equation is valid for the distribution of interface states in the upper part of the bandgap. When charge-pumping currents are measured, it should always be kept in mind that only a part of the interface traps can be 'seen'. Fast traps (with energies near the band edges) can possibly detrap before recombination with substrate holes takes place. Slow traps (with energies near the midgap) may not be filled during channel inversion. So only traps in a certain energy range contribute to the CP-current. This fact is often not considered in the literature (see for example Eq. 4 in [69]). The Ma Charge-Pumping Technique During the degradation process of a MOS transistor, nonuniform distribu¬ tions of interface traps can occur. For example, by injection of channel hot carriers into the gate oxide in the high field region near the drain almost all additional interface traps are generated in the vicinity of the drain. There¬ fore, it is important to get information on the spatial distribution of the inter- The Charge Pumping Technique 81 face traps. A charge pumping method which allows the determination of both the lateral interface state distribution and the gate oxide charge was proposed by T.P. Ma et al. in reference [69]. The technique works as fol¬ lows: A trapezoidal periodic pulse with constant base level and variable pulse height is applied to the gate. The averaged drain current (CP-current) is measured having the source non-connected. Comparing this current with the charge pumping current at the source with a non-connected drain, asymme¬ tries in the interface state distribution can be measured. Due to the lateral doping variation and a possible inhomogenous distribution of interface traps after hot carrier stress, threshold and flat-band voltages vary laterally. (Again, the threshold voltage is defined as the appropriate gate bias to induce a certain surface electron concentration. Compare also with Fig. 56.) At given base voltage and pulse height not necessarily all interface traps beneath the gate are contributing to the CP-current. An interface trap con¬ tributes only to the CP-current if its surface potential undergoes cycles of accumulation-inversion-accumulation. Before the pulse height reaches the maximum local threshold voltage, only interface traps residing between the drain (source) and the point whose local threshold voltage equals the pulse height contribute to the current. Fig. 57 : Charge pumping with the method ofT. P. Ma et al. The charge pumping current was measured at an unstressed transistor. The lateral interface trap distribution is there¬ fore symmetric. As shown (arrows) the local threshold voltage distribution can be derived from the curve of an unstressed device. 82 Some Measurement Methods and Characteristics of MOS Transistors Figure 57 shows an example of a CP-measurement at a NMOS transistor. To the gate a 500kHz trapezoidal periodic pulse with equal rise and fall times (=400ns), constant base level of -2V and variable pulse height was applied. Then, the averaged drain current (with non-connected source) and vice versa, the source current (with non-connected drain) were measured and compared. Because the transistor was new and the doping profile sym¬ metrical, the two curves are identical. (Later in chapter 5, in the section "Charge Pumping Currents" on page 99ff, examples of CP-measurements after hot carrier stress are shown. There we will see that after the stress the two currents become asymmetrical.) As indicated in Fig. 57, the L^-V^ curve of a fresh transistor can also be interpreted as a measurement of the local threshold voltage. The maximum of the current corresponds to the full length of the channel contributing to the recombination current. Definition and Measurement of Mobility The mobility of carriers in the channel of a MOSFET is a fundamental quantity. Unfortunately, the mobility is not a simple constant, but it is a function of the applied field and of the quality of the interface and it depends on the doping profile, on temperature and on other factors. In the literature a lot of various mobility models for electrons and holes in the inversion channel of MOSFETs were proposed. The correct dependences on physical quantities remain a subject of research. In the following section some definitions and a mobility measurement method shall be presented and some notes on the universality of the mobility curves shall be made. Later in chapter 6, where the negative transconductance effect is treated, a phenome- nological model of the mobility of electrons in the inversion channel and some deeper physical reflections on the root causes of its shape will be pre¬ sented. Definition In the literature several definitions of the mobility of carriers exist. Phe- nomenologically, the mobility u is defined as the proportionality 'constant' between the electric field E and the drift velocity vd. However, only at low electric fields E and vcl are proportional = • (45) v , u E . a i Definition and Measurement of Mobility 83 The microscopic definition of mobility is given by the mean time ü=A(x) (46) Scattering reduces the mobility of the channel carriers. Solving Boltz- mann's transport equation Schrieffer [70] showed already in 1955 that the mobility decreases as the surface field increases. At least three different scattering mechanisms influence the carrier mobil¬ ity in the inversion layer: phonon scattering, Coulomb scattering and sur¬ face-roughness scattering [71]. The relative importance of these three mechanisms depend on temperature and on the strength of the effective field that the channel carriers experience: 1 ) Electrons or holes in the channel scatter at the various modes of lattice vibration. Phonon scattering is important at room temperature and can be neglected at very low temperatures. 2) Coulomb scattering is due to charged centers, including fixed oxide charge, interface-state charge, and ionized impurity charge. At strongly inverted surfaces this type of scattering becomes less effective because of carrier screening. 3) Surface-roughness scattering finally is caused by the deviation of the interface from the ideal plane. This type of scattering becomes more impor¬ tant at high vertical fields: The closer the carriers are to the surface, the stronger the scattering due to surface roughness will be. Phonon, surface and ionized impurity scattering limited mobilities are often combined by the famous Matthiessen rule I 1 _1 (47) = J_+ ' Ä"// VPh ~Vc Z'w" Analytical expressions for these three most relevant scattering processes are given in references 172] and [73], for example. 84 Some Measurement Methods and Characteristics of MOS Transistors As shown in reference [74] a simple expression for the dependence of the surface mobility on the electric field can be derived starting at the micro¬ scopical definition given in Eq. (46) = = ß ^^ zATL7 . (48) x ' m m -v The thermal velocity vth is defined by 37T, (49) 1 . ; = v -m v~, -kl . 2 2 Assuming diffuse scattering at the surface. 1 is twice the classical channel layer width z defined by q-E-z=3/2kT. As a result, the following dependence of the surface mobility ps on the electric field can then be derived ^-% (50) Unfortunately, the drift velocity of electrons and the mean time between two scattering events of carriers in the inversion channel of a MOSFET are not well known quantities. Therefore, experimentalists have introduced dif¬ ferent definitions of mobility which allow a more convenient measurement: The "effective mobility" or "conductivity mobility" is defined by means of the conductance gd in the following way (see reference [71]) lL/W)-o i p =^Lp±i (51) q-N where qNmv=QN is the total mobile inversion charge. It can be deter¬ mined by measuring the displacement current. This measurement will be described in the next section of this chapter. The drain conductance gd is defined as the derivative of drain current relative to drain voltage at fixed gate voltage. Definition and Measurement of Mobility 85 The effective mobility has to be distinguished from the field-effect mobil¬ ity pFE which is related to the transconductance gm as follows (see reference [71]) (52) 0 d V,->0 The transconductance gm is defined as the derivative of the drain current relative to the gate voltage at a fixed drain voltage. The term Cq stands for the gate capacitance per unit area. Effective and field-effect mobility are essentially identical near the threshold voltage. Beyond this point the field- effect mobility is always smaller than the effective mobility. Measurement of the Mobility In this section the method of Sodini et al. [75] for measuring the mobility in the inversion channel of a MOSFET shall be reviewed. The mobility is measured as a function of gate voltage for a very low drain voltage (e.g. Vds=10mV), It relies on the drift-diffusion equation for electrons in a n- channel, as is expressed in Eq. (53) -fi-^ . ^NQN-fi-Ex+^A x A (53) W q dx The diffusion constant was replaced by the Einstein relationship. In the literature the mobile channel charge is sometimes calculated with QN=C0X(V2S-Vth). This is a quite unsuitable way, because QN depends in this definition on the threshold voltage (which is not well defined) and it ignores the fact that the mobile channel charge does not vary linearly with gate voltage. (In the vicinity of the threshold voltage the channel capaci¬ tance is comparable with the dielectric capacitance.) To obtain the change in mobile charge with respect to the gate voltage, the displacement current l{ flowing out of the source and drain of a NMOS device is measured when a ramp voltage is applied to the gate. The follow¬ ing relation is then valid (Eq. 13 of reference [75]) 86 Some Measurement Methods and Characteristics of MOS Transistors dV,s dQh (54) dt dV^ In a similar manner the change of bulk charge (^depletion charge) can be determined by measuring the displacement current flowing out of the sub¬ strate when a ramp voltage is applied to the gate. (This method is generally known as "split C-V measurement".) The dependence of the electric field and of the mobile charge gradient on gate voltage can be calculated as follows: lh ^'v p? (V ) = ^K qsJ L-C„ d\L (55) K dx Si L dV„ If the drain current Icl and the derivative of the mobile channel charge Q^/ dV„s is measured with respect to the gate voltage, the mobility as a function of gate voltage can be calculated with Eq. (53). Now an example of this method shall be presented. Figure 58 shows the drain currents as a function of the gate voltage for three transistors with dif- ferent oxide thicknesses. The drain currents were measured at a low lateral field (Vds=10mV). Next, the displacement currents of the three transistors were measured: With a picoamperemeter a continuous ramp voltage of 0.08 V/sec was applied to the gate and the current flowing through source and drain into the inversion channel was measured. Source and drain were thereby kept at ground. Dividing the measured currents by the slope of the ramp gives the derivative of the inversion channel charge with respect to the gate voltage. The results are plotted in Fig. 59. Definition and Measurement of Mobility 87 4.0E-6 3.5E-6 3.0E-6d 2.5E-6 NMOS: (L/W)=100m/100|i 2.0E-6T < Vds=10mV 1.5E-6- T=298K 1.0E-6 * Id [A] with d=250A, Vds=1 OmV 5.0E-7- Id [A] with d=150Â, Vds=10mV O.OE+O- 1 Id with d=1 OO Vds=1 OmV [A] , -5.0E-7 -2 6 8 10 12 14 16 Vgs [V] Fig. 58 : Measurement of the drain currents at three different oxide thicknesses. The drain currents were measured at a small drain voltage of only lOmV. 3.5E-11- NMOS: (L7W)=100m/100|j. 3.0E-11 Vds=10mV T=298K 2.5E-11 E 2.0E-11- 1.5E-11 -d g mm mmm-mmpmmmmmmmmmmfi- z J0&ffi&^ 1.0E-11 § * o A * with d=250A 5.0E-12- dQN/dVg [F] i* „J" dQN/dVg[F]withd=150 O.OE+O- ^ dQN/dVg[F]withd=100À -5.0E-12 -2 6 8 10 12 14 16 vgs [V] Fig. 59 : Change of channel charge with increasing gate voltage for various oxide thick¬ nesses. This was calculated by dividing die measured displacement currents by the slope of the ramp applied to the gate. Then, the inversion charge was determined by integrating the curves in Fig. 59. Finally, the mobility of the electrons in the inversion layer was cal¬ culated u by solving Eq. (53) for and replacing E and dQN/dx by the expres¬ sions shown in Eq. (55) 88 Some Measurement Methods and Characteristics of MOS Transistors IJVg)-L-Cox-q ß(VA- (56) w.v . dQN(V^)-[QJVA-q~-k-T-C0X) D dVr In Fig. 60 the extracted mobilities are plotted as a function of Vos: 450- NMOS (L/W)=100u/100u Vds=10mV 400- T=298K _ 350- * \x with d=250A H with d=150À £ ". 300H (.iwith d=100 250- 200- 10 12 14 16 Vgs [V] Fig. 60 : Calculated channel electron mobilities of three NMOS transistors with different oxide thicknesses as a function of the gate \ oltage However, several sources of errors affect the measurement: Charge trap¬ ping and gate leakage currents are neglected in this technique. A part of the electrons of the displacement current are trapped at the interface and do not contribute to the drain current. Ignoring charge trapping the total mobile charge is overestimated: The trapped charge is not moved along the channel by the electric field and consequently, it does not contribute to the drain cur¬ rent. Furthermore, especially in transistors with thinner gate oxide, a gate leakage and/or tunneling current can falsify the measurement of the dis¬ placement current. This also results in an overestimation of the total mobile channel charge. Both factors lead to a lower extracted mobility. Definition and Measurement of Mobility 89 In the last part of this chapter some aspects of the 'universal' dependence of the mobility on the effective electric field shall be considered. From Gauss's Law, the peak field at the silicon surface is given by: E,=~~\Q +Qr] (57) fcV The inversion charge Qim (=mobile channel charge QN) and the depletion charge (= bulk charge QB) can be measured by means of the "split-CV method" described above. However, this peak field is not what most of the electrons in the inversion layer see. Quantum-mechanical calculations of inversion layer carrier distri¬ butions show that the carriers are dispersed in the semiconductor with a peak density some nanometers away form the interface. This will be reflected later in chapter 6 (see "Quantization of the Inversion Layer" on page 131). Electrons or holes in the channel feel therefore an "effective" field Ecff which is usually defined as (see for example reference [71]) i-ô,m+ôJ • (58) fc In the literature it has been reported that the electron and hole mobilities in the inversion layer of a MOSFET on a (100) wafer follow universal curves independent of the substrate impurity concentration or of the sub¬ strate bias when they are plotted as a function of the effective field [71]. To illustrate the 'universality' of the dependence of the mobility on the electric field, the mobilities shown in Fig. 60 were plotted versus the electric field. For simplicity, however, not the effective field was determined, but the surface field was used. The difference between effective and surface field becomes relatively small for high substrate doping and high transversal fields. The result of this calculations are shown in Fig. 61. Quite a good uni¬ versal dependence of the mobility on the surface field can be observed. A simple model, which describes main effects of the universal mobility dependence, will be treated in chapter 6 in the section "A Simple Mobility Model" on page 124. 90 Some Measurement Methods and Characteristics of MOS Transistors 450- NMOS: (L/W)=100^/1 OOii Vds=10mV 400- T=298K 350- > I 300- * dox=250A 250- dox=150 o dox=100 200- 0.2 0.4 06 08 1 1 2 1.4 1.6 1.8 E [MV/cm] Fig. 61 : A good 'universal' dependence of the electron mobility in inversion channels can be found plotting the mobilitx vei sus the surface field. Shown are the values for- three different oxide thicknesses. 5 Generation of Oxide Charges and Interface Traps After the survey in the previous chapter of main characterization tech¬ niques, we come back to the main subject of this thesis. In chapter 2 and 3 important degradation mechanisms were reviewed and examples of degra¬ dation on circuit level were presented. In this chapter, degradation on tran¬ sistor level shall be treated in some detail. The main degradation of submicron transistors is due to the generation of oxide charges and of interface traps by hot carrier stress. (Nevertheless, also other degradation mechanism exist on transistor level: for example, ionic contamination or radiation effects. But these will not be studied.) From the literature it is known that the hot electron degradation of NMOS transistors is dominant in comparison with the hot hole degradation of PMOS transis¬ tors. Therefore, in this chapter only the NMOS case will be considered. The following aspects will be reflected: First a short review of the differ¬ ent injection mechanisms will be given, though later, only drain avalanche hot electron and Fowler-Nordheim injection will be further investigated. In the second part the effect of hot carrier stress on the gate induced drain leak¬ age and on the substrate current will be analyzed. Then, after some theoreti¬ cal review of the microscopical structure of the Si-Si02 interface and the nature of oxide traps, examples of charge pumping curves measured after hot electron stress will be presented. Next, the different magnitude of degra¬ dation during Fowler-Nordheim stress depending on the direction of the electric field will be explained and finally, a lifetime estimation of a quarter micron NMOS transistor will be made. 01 92 Generation of Oxide Charges and Interface Traps Injection Mechanisms Interface traps and oxide charges are generated during injection of elec¬ trons and holes into the gate dielectric. Takeda et al. [76] distinguish between six different injection mechanisms: channel hot-electron, drain avalanche hot-electron, secondary generated hot-electron, substrate hot-car¬ rier, Fowler-Nordheim tunneling and direct tunneling. The gate current with its peak at VSs~Vds generally results from channel hot-electron (CHE) injection. "Lucky electrons" gain sufficient energy in the channel to surmount the potential barrier at the silicon-oxide interface. This injection mode is used in EPROM and flash EEPROM for the "write" operation. Because of peak-ICT current, early reports on device degradation were focused mainly on CHE injection. But then in 1983, Takeda and Suzuki [771 empirically found that the most severe hot-carrier stress condi¬ tion in MOSFETs corresponds to the peak-Isub condition around VCTS=Vds/2. This condition is called drain avalanche hot-electron (DAHC) injection. At VCTS=Vds/2, the largest impact ionization for a given drain voltage occurs. Electrons and holes are injected into the gate and can be measured as gate current (see reference [78]). To measure hot-carrier lifetime under worst case conditions it is sufficient to stress the device under DAHC injection. The origin of secondary generated hot-electron injection (SGHE) remains unclear. However, gate currents different from those due to DAHC injection can be measured for V2s Injection by Fowler-Nordheim and direct tunneling is achieved by applying a sufficiently high oxide field so that electrons from the inversion channel tunnel through the barrier into the oxide. This was already dis¬ cussed in chapter 3, section "Fowler-Nordheim Current" on page 59. In the substrate hot-hole injection condition, finally, the well/substrate junction of a PMOSFET is forward biased and at the gate a negative voltage is applied. At the forward biased well/substrate junction holes are injected into the n-well, are accelerated to the interface and finally, some of them are injected into the oxide. Satake et al. [79] used substrate hot hole and Fowler- Nordheim injection to individually control the amounts of injected hot elec¬ trons and holes into the gate oxide. They found that the coexistence of hot electrons and holes is essential for dielectric breakdown in SiOo. GIDL-, Gated-diode-, Gate- and Substrate-Currents 93 GIDL-, Gated-diode-, Gate- and Substrate-Currents In this chapter the influence of interface and oxide traps in the vicinity of the drain shall be considered. Additional traps were generated by stressing a NMOS transistor with drain avalanche hot electrons. Then, changes in drain leakage, tunneling and substrate currents were measured. Drain leakage and substrate currents are important monitors of device lifetime. They show a strong degradation after hot electron stress because both currents strongly depend on the local field. Figure 62 shows an exam¬ ple of the degradations of the gate induced drain leakage (GIDL) and the substrate current in a NMOS transistor. First. GIDL and substrate current were measured at a fresh 0.25pm NMOS transistor. Then, the transistor was stressed by drain avalanche hot electrons: To the drain a voltage of 3V was applied and the gate was kept at the potential at which the substrate current was maximum. It is known that in this condition the degradation of the device is the most severe (see reference [77]). 1E+0^ -5.0E-7 1E-1- 1E-2- -0.0E+Û 1E-3 NMOS (L/W)=0.25p/5M * 1E-4- Vds=2.5V 1R-5-Î --5.0E-7 =298K _, 1E-6- < Zi 1E-7-1J --1.0E-6 - 1E-8H 1E-9-I — 1.5E-6 1E-10-* GIDL —2.0E-6 -2.5E-6 vgs[Vi Fig. 62 : Drain- and substrate currents measured at Vcjs=2.5V. Substrate current and GIDL were measured first at the fresh transistor and then after DAHC stress at Vjs=3V and V„s=1.46VLifter Hi, 2h, 4h and Sh of stress. Both GIDL and f-, increase with stress. In Fig. 62, it can be observed that the GIDL and the substrate current increased after stress. The increase of the GIDL current has two main rea¬ sons: First, electrons trapped in the interface or in the oxide in the gate-to- drain overlap region intensify the local electric field and cause a stronger 94 Generation of Oxide Charges and Interface Traps band bending. Therefore, after stress more valence electrons move by band- to-band tunneling into the conduction band increasing drain leakage. Sec¬ ondly, trapped electrons can detrap and contribute to the drain leakage cur¬ rent. GIDL is therefore sensitive to trapped charges in the gate-to-drain overlap region. These traps can hardly be detected by threshold voltage measurements or by charge pumping. Comparing with threshold voltage shifts it is also noteworthy that the GIDL current exhibits an exponential dependence on oxide charge, whereas the threshold voltage is only linearly dependent on trapped charge. Thus the threshold voltage may not be suffi¬ ciently sensitive to oxide charge variation and stress suffered [80]. GIDL is only sensitive to charged traps and not to neutral traps. Wang et. al. [80] therefore developed a method to generate traps, fill the traps and then measure the detrapping GIDL current transient. As a result of electron detrapping, both the oxide field and the silicon surface field decrease and the GIDL current decays with time. They reported that it was possible to differ¬ entiate between oxide charge and interface charge because of the large dif¬ ference in time-constants. The dependence of GIDL current on the silicon surface field Es can be expressed as (see "NMOS Transfer Characteristic, Substrate Currents and GIDL" on page 45ff) \ B (59) I, = A- Es -exp F where B is a constant with a value around 18.5MV/cm. The stress-created oxide charge Qeff can be evaluated from the measured pre-stress and post- stress GIDL currents as follows (see reference [80]) e E; I,( pre —stress (60) c1t — B I,( post stress As can be observed in Fig. 62 also the substrate current increases after stress. Hot electrons generate electron-hole pairs by impact ionization. Holes flow to the substrate contact and recombine there with electrons caus¬ ing the substrate current. The impact ionization rate strongly depends on the amplitude of peak electric field, which increases during the generation of oxide charge and interface traps. GIDL-, Gated-diode-, Gate- and Substrate-Cuiicuts 95 The GIDL technique is similar to the gated-diode measurement configu¬ ration [81] with the difference that in the latter method the forward drain- substrate current as a function of gate voltage is measured. In contrast to the reverse drain-sub strate mode, in the forward mode a defect-assisted tunnel¬ ing current flows at lower band bending. The forward drain-sub strate leak¬ age current consists of two components: the diffusion current and the recombination current. But for small forward biases the recombination cur¬ rent dominates. The active generation/recombination centers are located in the depletion region at the drain-substrate junction. When the junction is forward biased the depletion region is small. Sweeping then the gate voltage from depletion to accumulation, the active area scans like a pointer along the interface toward the drain and the generation/recombination current rises and falls depending on the number of midgap interface states. In the left part of Fig. 63 an example of this technique is shown. A small negative voltage (Vds=-0.2V) was applied at the dram to forward bias the drain-substrate junction. Then, the drain current was measured at the fresh device during a sweep of the gate potential between zero and -3.5V Next, the transistor was stressed with DAHC stress during five minutes at Vds=3.5V and then the leakage current was measured again. 1E-8- 0.0E+0 -Id before stress -2 OE-5 lb before stress -Id after 1E-9- stress -4 OE-5 lb after stress ' gated-diode' leakage -6 0E-5- I substrate 5f-8 0E-5^ current NMOS - -1.0E-4- 1E-11- (L/W)=0 3u/10u" -1 2E-4- NMOS dox=6nm dox=6nm -1 4E-4 1E-12- : Vds=-0.2V Vds=3 5V -1 6E-4- (L/W)=0 3,u/10,u 1E-13- -1 8E-4 -3 5 -3 -2 5 -2 -15 -1 -0 5 0 -0 5 0 05 1 15 2 25 3 Vgs [V] vgs [V] ' Fig. 63 Left: 'Gate-diode' measurement of the dram leakage current compared with the substrate current before and after 5' drain axalanche hot electron stress with Vds=3 5V 96 Generation of Oxide Charges and Interface Traps In the right part of Fig. 63 the substrate currents of the fresh device and elfter the DAHC stress are shown for comparison. It can be seen that the 'gated-diode' method is very sensitive to the generation of interface traps. Combined with a numerical simulation the spacial distribution of the oxide-trapped charge Qox and interface states Nlt can be determined (see reference [82]). Cheng et al. showed in reference [82] that after channel hot electron stress the peak of the electric field, and the peaks of the oxide- trapped charge and the interface state distribution all lie between drain junc¬ tion and gate edge. Finally, the influence of hot electron stress on the Fowler-Nordheim tun¬ neling current shall briefly be reflected: Stressing a NMOS transistor by DAHC generates acceptor interface traps and some negative oxide charges. When the Fowler-Nordheim tunneling current is measured subsequently, a higher gate voltage must be applied to create the same oxide field as in an unstressed oxide: During build-up of the inversion channel negative charge is trapped in acceptor traps. Together with the trapped electrons in the oxide this charge screens the electric field. -0 5 0 05 1 15 2 25 3 Vgs [V] Fig. 64 : Only small changes in GIDL and gate-current can be observed after 5 minutes drain avalanche hot electron stress w ith Vcjs=3.5V An example is shown in Fig. 64: At the same transistor as used in the pre¬ vious experiment (shown in Fig. 63), GIDL and Fowler-Nordheim tunneling current before and after the DAHC stress were measured. It can clearly be seen that the tunneling current is reduced as a result of the trapped charge. Additionally, it is obvious that the changes in GIDL and tunneling current are much smaller than the changes in the forward drain leakage current and the substrate current (compare Fig. 64 with Fig. 63). The structure of the Si-Si02 interface, oxide-trapped charges and interface states 97 The structure of the Si-Si02 interface, oxide-trapped charges and interface states In this section the microscopical structure of the Si-SiOo interface shall be discussed. Despite its importance for the proper working of a MOS tran¬ sistor, the atomic microstructure is not very well known. However, some models are published in the literature. The most important aspects shall now be reviewed. Various experimental techniques were used in the past to investigate the interface. Examples are transmission electron microscopy (TEM), X-ray grazing incidence diffraction (GID), electron spin resonance (ESR) and oth¬ ers. These measurements demonstrate that the thermal oxide is amorphous and stoichiometric down to about one nanometer from the interface. The microscopic structure of the first nanometer oxide near the interface was studied by Ourmazd and Bevk et al. [83]. In their article they published some excellent TEM-pictures of the Si-Si02 interface. Their photos show an atomically flat Si-SiO^ interface with a crystalline transition layer of about 5Â. The structure of the transition layer was that of tridymite, a well-known, crystalline, bulk phase of Si02. Ourmazd and Bevk noted further that when steps at the Si surface are present, tridymite grows in grains with different orientation. The grain size was determined by the spacing between the steps on the Si surface prior to oxidation. • • • • • Fig. 65 : Model of the Si-Si02 interface with Py0 and Ph] interface defects and E' oxy¬ gen vacancies seen in the [110] direction. In the inset, the Si unit cell is shown. 98 Generation of Oxide Charges and Interface Traps In Fig. 65, a model of the Si-Si02 is plotted. It is a synthesis of the infor¬ mation given in reference [83] of the ideal Si-Si02 interface and the possi¬ ble nature of interface and oxide traps published in [51 and [84]. The picture shows a view along the [110] direction. The lower part is bulk silicon. Com¬ paring with the inset of Fig. 65, where the unit cell of silicon is drawn, it can be seen that looking into the [110] direction always two silicon atoms of one unit cell lie one upon another. Therefore, double lines in the lower part of Fig. 65 indicate the bonds to two different Si-atoms. At the interface some Si atoms share their 'unused' electrons by dimerization (dashed line). Other dangling bonds trap hydrogen or a hydroxyl group. On the top of the Si(100) surface a crystalline transition layer in the tridymite structure is sketched. Moreover, Figure 65 shows two different interface defects and two oxide defects: The defects were identified by electron spin resonance and are referred to as Pb and E' centers. Two spectroscopically different types of interface defects, called Ph0 and Pb|. were identified in reference [84]. Both were ascribed to single dangling interfacial Si orbitals. The atomic assign¬ ment, however, still remains unclear: It is supposed that Pb0 is a «Si=Si^ and Pbl a -Si=Si20 dangling bond. Since SiOo films are grown on Si substrate with large lattice mismatches, oxygen vacancies are inevitably introduced and remain in Si02 films to release the strain energy. Calculations showed a relation between the O vacancies and paramagnetic structures called E' centers found during elec¬ tron spin resonance measurements. Oxygen vacancies are widely accepted to be hole trap centers. Therefore, the termination of the dangling bonds of these vacancies is a very important step during processing. Annealing in H2 and/or NH3 is thought to terminate the defects and to improve the reliability of the oxide films. However, it was suspected in reference [5] that H atoms are not effective terminators of O vacancies, i.e. their protection against hole trapping is bad. A good solution would be to terminate the dangling bonds in the oxide with a OH-group. K. Hess et al. [85] discovered that the use of deuterium instead of hydro¬ gen in the low temperature post-metal anneal process improves the hot car¬ rier lifetime of a transistor by a factor of 10-50. During this anneal process the silicon dangling bonds at the Si/Si02 interface are passivated with deu¬ terium, which is apparently more resistant to hot-electron excitation than the silicon-hydrogen bond. Charge Pumping Currents 99 Charge Pumping Currents In this section the localized damage of a NMOS transistor after drain ava¬ lanche hot carrier stress is investigated by measuring charge-pumping cur¬ rents. This technique is probability the best one for the understanding and sense of early damages at the interface (compare with "The Charge Pump¬ ing Technique" on page 77). To investigate hot carrier degradation some 0.25pm NMOS transistors were stressed and characterized at wafer level. Two charge pumping meth¬ ods were used: the method of Groeseneken et al. [66] and the method of Ma et al. [68]. The Ma method has some advantages because it allows to deter¬ mine the lateral distribution of the interface traps. 2.5E-10- NMOS: (L/W)=0 25p/5|j aftet Shouts of DAHC f=500kHzwith tr=400ns 2 0E-10- Vh-Vb=2V 1.5E-10- a o 1.0E-10- 5 0E-11- 0.0E+0 0.5 Fig. 66 : Charge pumping currents with a constant pulse height and variable base volt¬ age (after Groeseneken et al. ): CP currents w ere measured at the fresh device and after Ih, 2h, 4h, 8h of stress with Vj^-SV and at maximum substrate current. Figure 66 shows an example of the Groeseneken method: To the gate trapezoidal pulses with a frequency of 500kHz, with 400ns rise and fall times and an amplitude of 2V were applied. Source and drain were con¬ nected to ground and the averaged substrate current was measured with a HP4156 precision parameter analyzer. The first charge pumping current was measured at a fresh, i.e. unstressed NMOS transistor. With Eq. (42) (see "The Charge Pumping Technique" on page 77) the density of interface traps was calculated to equal about 6-10 eV cm""-. Then, the device was stressed wo Generation of Oxide Charges and Interface Traps during one hour with drain avalanche hot electrons at a drain voltage of 3V During the stress the voltage that resulted in the highest substrate current was applied to the gate. After one hour of DAHC stress the charge pumping current was measured again. It can be observed in Fig. 66 that during this initial stress the most interface traps were generated. Probably, all weak bonds broke during the initial stress minutes. A calculation with Eq. (42) results in Djt=1.7-10 eV cm"". Then, the transistor was further stressed and the charge pumping current was measured after each hour. The values after two, four and eight hours are plotted in Fig. 66. It can be seen that the number of additional interface traps increases further but slower with stress time. Now, the influence of hot electron stress on the Ma charge pumping curves will be discussed (compare with "The Ma Charge-Pumping Tech¬ nique" on page 80). -2.5E-10 NMOS (L/W)=0.25u/5u f=500kHz with -2.0E-10 tr=400ns Vb=-2V constant -1 5E-10- -1.0E-10-1 a o drain and source currents of the fresh NMOS -1.5 -0.5 0 0.5 1.5 Vh[V] Fig. 67 : Charge Pumping current with a constant base voltage and variable pulse height (as proposed by Ma). The charge pumping current was first measured at the drain side, then at the source side. No difference was measured. After a 4h stress the currents were again measured at the drain and the source side. A clear difference between the two cur¬ rents could then be observed. 67 an Figure shows example of the Ma charge pumping method. Again a fresh 0.25pm NMOS transistor was first characterized: To the gate a 500kHz trapezoidal pulse with a fixed base level at -2V and with varying amplitude was applied. The source was not connected, the substrate and the drain were kept at ground and the averaged drain current was measured. Charge Pumping Currents 101 Then vice versa, the averaged source current was measured with the drain not connected. Both currents were equal. In the next step, the transistor was stressed for four hours with drain avalanche hot electrons at Vds=3.3V and at maximum substrate current. After this stress the two currents were mea¬ sured again: In Fig. 67, it can be seen that after stress a clear difference between the CP-current measured at the drain contact (with floating source) and the one measured at the source contact (with floating drain) can be observed. This shows clearly that the degradation region is located near the drain junction, where the field was the highest during the stress. Generally, when a fresh NMOS-transistor is first measured using this method, then stressed and finally measured again, the two curves can be interpreted in the following way (compare with reference [86]): 1) A change in oxide charge without changing the interface state density will only cause a local shift of the second lcp-Vh curve. 2) An increase in the interface state density without changing the oxide charge will only change the slope and the maximum of the fcp-Vh curve. The increase of the charge pumping current measured on the drain side can be explained as follows: In the gate-to-drain overlap region acceptor interface traps are generated during DAHC stress. After increasing the gate pulse amplitude the channel becomes depleted or even slightly inverted while the pulse is near its upper level. As shown in Fig. 68 an electron from the drain contact can be trapped by an interface dangling bond near the drain junction. When the channel is driven back into accumulation, the trapped electron is reemitted and recombines with a hole in the substrate. When additional traps in the vicinity of the drain are generated, the probability for this recombination process increases. Therefore, the charge pumping current on the drain side rises at lower gate voltages compared with the CP current on the source side (compare with Fig. 67). 68 : Fig. Charge Pumping into a Pb/ dangling bond located near die drain junction. 102 Generation of Oxide Charges and Interface Traps Figure 67 can also be compared with the figures shown in reference [86], where a lot of oxide charge was generated. It can then be concluded that in our case mainly interface traps were generated. (Note that the increase of the maximum current is proportional to the generated number of interface traps. Additional oxide charge would have shifted the curve along the x- axis.) This is also in agreement with the known fact that in NMOS transis¬ tors mainly interface traps are generated whereas in PMOS transistors oxide charge injection dominates during hot carrier stress [80]. Hot Carrier Stress and Lifetime Estimation In this section first the effects of drain avalanche hot carrier stress (DAHC) on threshold voltage, GIDL, transconductance, substrate- and charge pumping currents shall be compared. Then, with the gathered data the hot carrier lifetime of a 0.25pm NMOS transistor will be estimated. 1E+0-^ Fig. 69 : Extensive device degradation after drain avalanche hot electron stress with V^—3.5V and at maximum substrate current (lf=-39pA( During MOSFET degradation three important electrical characteristics change: threshold voltage, turn-off in the subthreshold region (also called gate swing) and transconductance. Figure 69 shows the degradation of a Hot Carrier Stress and Lifetime Estimation 103 NMOS transistor after severe drain avalanche hot electron stress at Vds=3.5V and maximum substrate current. A clear increase in the threshold voltage VT and gate-voltage swing S can be observed after the stress. (S is defined as the gate voltage needed to reduce the subthreshold current by one order of magnitude [35].) Furthermore, the transconductance gni in the lin¬ ear and the saturation region considerably deteriorates. In the next example, GIDL, threshold voltage, transconductance, sub¬ strate- and charge pumping currents will be compared. Again a fresh transis¬ tor was characterized and then stressed and measured periodically. This time, however, the DAHC stress was only at Vds=3.3V and Vss= 1.6V. The left picture of Fig. 70 shows the shift in the threshold voltage mea¬ sured at lOOmV drain voltage. The degradation was quite severe: Already after 80 minutes DAHC stress the threshold voltage shifted about 60mV in positive direction. The positive shift of VT is due to the generation of accep¬ tor traps near the drain junction. Negative charged traps screen the gate potential and consequently, a higher gate voltage is necessary to induce the same electric field at the silicon surface. On the right side the transfer char¬ acteristics measured at a drain voltage of 2.5V is plotted. Here, apart from some increases in GIDL, only small changes can be observed. 1E-5- Threshold Voltage: 1E-2-| 1E-3-I NMOS: (L/W)=0.25u/5u 1E-4-| 1E-5-J 1E-6- < 1E-7- 2 1E-8-; GIDL: 1E-9- NMOS: (L/W)=0,25|j/5u 1E-10- dox=6nm 1E-11-3 N*/ Vds=2.5V 1E-12- T=298K 1E-13- C\J 00 •<* LO CD CO 05 CO LO LO m LO LO LO LO LO -0 5 0.5 1 1 5 o o o o o o o o Vgs [V] Vgs[V] Fig. 70 : Positive threshold voltage shifts measured at Vj=0.1V (left) and transfer char¬ acteristics with GIDL measured at Vd=2.5V (right) after DAHC stress at Vd=3.3N: Currents were measured at the fresh device and after lOmin., 20min.. 40min., 80min., 160min. arid 250min. of stress. 104 Generation of Oxide Charges and Interface Traps 1E-5- OE+0 Transconductance: 1E-5- NMOS: (L/W)=Q.25lj/5u -5E-7 dox=6nm 1E-5- Vds^O.IV T=298K 8E-6- I 6E-6-H 4E-6 2E-6H M0lhww>W»w«W' OE+0 LOT-CMCO^tLOCDh-COCTiCO qLOlolololololololo,—; 0 02 04 06 0.8 1 1.2 1.4 1 6 1 8 2 oddoooooo Vgs[V] vgs [V] Fig. 71 : Comparison of transconductance degradation (left) and increase in substrate current (right) after DAHC stress at Vj=33N: Currents were measured at the fresh device and after lOmin., 20min., 40rnin., 80min., 160min. and 250min. of stress. 4E-10 -3.5 -3 -2.5 -2 -1 5 -1 -0.5 0 0 -0.5 0 0.5 1 1.5 Vb[V] Vh[V] Fig. 72 : Conventional charge pumping technique (left): Degradation of charge pumping currents after DAHC stress at Vcis=3.3V: Values were measured at the fresh device and after 10min., 20min., 40min., 80min., 160min. and 250min. of stress. Right: Ma charge pumping technique: A clear change of the shape of the CP-current can be observed after a 250min. drain avalanche hot electron stress at Vds=3.3Vand V0?=1.6V (maximum sub¬ strate current). The CP-current measured at the drain contact with floating source con¬ tact starts at lower gate voltages than the CP-current measured at source with non- connected drain. Hot Carrier Stress and Lifetime Estimation 105 Figure 71 compares the decrease in transconductance with the increase in substrate current after DAHC stress. The increase in substrate current shows that the peak electric field near the drain-substrate junction becomes higher during stress. As a result, more channel electrons gain enough energy to generate electron-hole pairs by impact ionization. Finally, in the left part of Fig. 72 the charge pumping currents measured with the conventional method introduced by Groeseneken et al. are shown. It can be observed that during an initial stress the interface state density quickly rises. Then, during further stresses the trap density continues to increase, but the generation of additional states slows down. The right part of Fig. 72 compares the charge pumping curves measured at the drain with non-connected source and varying gate pulse amplitude with the currents measured at the source and non-connected drain. First the fresh device was characterized and then the charge pumping currents were measured after 250 minutes of DAHC stress at Vds=3.3 V. Whereas the initial averaged cur¬ rents at the drain are identical with the currents measured at the source (that means the fresh transistor was symmetrical), the charge pumping currents of the stressed device show an asymmetrical distribution of the interface traps: Impact ionization in the high field region near the drain generated there a lot of additional traps and the recombination current increases on the drain side at lower gate pulse amplitudes compared with the current measured at the source. Figure 73 shows the dependence of threshold voltage shift on stress time. In spite of the severe stress condition and in disagreement with reference 65 [87] (where a power dependence At^t0 was reported) the measurements show that the shift linearly depends on the stress time. The linear time dependence of the degradation can also be observed at a lower drain voltage (see later in Fig. 74). The shift rate of the threshold voltage is constant over quite a long time. Only at the beginning, the shift rate is slightly larger, but after this initial stress, Vth increases every hour by about the same value. The right picture of Fig. 73 shows that the maximum substrate current and the estimated number of interface traps depend in the same manner on stress time. All these curves suggest that the common cause for the degrada¬ tion is the generation of acceptor-type interface traps by holes created in the pinch-off region. A possible microscopic mechanism is that a hole breaks a silicon-hydrogen bond. If the silicon and the hydrogen atom renew their bonding, no interface trap is generated. If the hydrogen atom diffuses away from the interface, a new interface trap is generated. Replacing hydrogen by deuterium improves lifetime considerably [85]. The additional neutron of 106 Generation of Oxide Charges and Interface Traps deuterium doubles its mass and therefore, deuterium diffuses much slower away from the trap site. It is also well known that nitridation of gate oxides reduces hot carrier damage. This can be explained in this model by the lower diffusivity of hydrogen in silicon nitride. 25- -6E+11 Substrate Current: Threshold Voltage Shift: 2.7E-6-I NMOS. dox=6nm NMOS: ^ (L/W)=0.25|j/5p -5E+11 20- fL/W)=0.25u/5u^T stress with Vds=3.3V 2 5E-6 Vds=2 5V ,#) (*) H4E+11 _ > .15- _2.3E-6- 0) < CM x stress @Vds=3,3V e —3E+11 o 2.1E-6- > g o n 10- Interface state density: -2E+11 1 9E-6-1 measured with CP dox=6nm, Vds=0.1V 5- O lbs Vth=Vgs@ld=1uA 1.7E-6 -1E+11 T=298K Nit 1.5E-6 ' " " " M " " -0E+Ö I | I I 0 20 40 60 80 100 120 140 160 180 200 0 50 100 150 200 250 t [min] t [min] Fig. 73 : (Left): The positive threshold voltage linearly depends on stress time. (DAHC at Vds=3.3V at maximum substrate current (Vos~1.6V)). The stress time between each measurement was 10 minutes. Right: Substrate current and interface state density as a function of stress time. A very similar dependence was found. In the second section of this chapter, a technique for the estimation of the lifetime of a NMOS transistor will be presented. Important parts of this technique were first published in 1983 by E. Takeda et al. [77]. The com¬ plete theory, however, was developed by C. Flu et al. in 1985 (see reference [87]). Impact ionization, light emission, hot electron emission and generation of interface states are the main hot carrier effects. Any of these hot carrier effects could set the scaling limit for a given circuit. For example, substrate current can cause latch-up in CMOS devices. However, the generation of interface traps (or surface states) is the dominant cause of MOSFET degra¬ dation. All hot carrier effects have a common root cause: the maximum channel electric field Em. Therefore, they have all similar dependencies on Em 1871 Hot Carrier Stress and Lifetime Estimation 107 9h f, oc / • exp (61) ; qÀE, m / \ hv I oc I . exp , , ' photo a qXE, m J where Iph0t0 is indicative of the generation of minority carriers in the sub¬ strate by photons generated in the pinch-off region, % is the mean free path of electrons, cpt the minimum energy that a hot electron must have in order to create an impact ionization and cpb the barrier energy at the Si-Si02 inter¬ face. These dependences are a result of the exponential dependence of the impact ionization coefficient on 1/Enr The formulae can be understood by thinking of the 'lucky electron*' concept (compare with "NMOS Transfer Characteristic, Substrate Currents and GIDL" on page 45): (p/qE,^ is the distance that an electron must travel in the electric field to gain the energy (p4 and exp(-(pj/q^Em) is the probability of an electron traveling a sufficient dis¬ tance to gain the energy cp, without suffering a collision. Thus, Id-exp(-cp/ q^Em) is the rate of hot electrons possessing energies higher than (pj. Without knowing the exact physical mechanism responsible for the gen¬ eration of interface traps, a similar expression can be postulated for the gen¬ eration of interface traps. Take cpit to be the critical energy that an electron must have in order to create an interface trap. If the lifetime i of the device is defined as the time at which the number of generated interface traps ANit reaches a chosen value, the expression for the lifetime of the device will be W ^ x oc _. • exp (62) qXE, ft m J From the expression for lsub, Iphoto and T the following dependence of lifetime on drain and substrate current or on drain current and photon flux can be derived 108 Generation of Oxide Charges and Interface Traps T-(plti(Pl -cpjhv sub photonflux LLl (63) w L Therefore, measuring the substrate current or the light emission allows in principle to determine the age of a device, when the critical energy cplt of interface trap creation and the proportional constant are known. Eq. (63) is the famous model of C. Hu et al. (see reference [871). Fortunately, the maximum channel electric field Em, which is the com¬ mon root cause of all hot electron effects, needs not to be known for the life¬ time estimation in (63). Em is not easy to determine. An expression for Em is given in [87] V, -V, g —fill _Vv where Xj is the approximate junction depth. Together with Eq. (61) the substrate current is roughly proportional to I a°'< I oc —y , c''exü 1mb 7 (65) i| y Using the model of Takeda et al. [77] the lifetime of a MOS devices under hot carrier stress can therefore be written as: 1 b" (66) r oc exp v With the help of this last Eq. (66) the maximum allowed drain voltage for a given technology can be estimated: A representative transistor for the design has to be degraded at a number of elevated drain voltages. Then, with the measured lifetimes the maximum drain voltage for a lifetime (for exam¬ ple of 10 years) can be extrapolated. Hot Carrier Stiess and Lifetime Estimation 109 To illustrate these techniques the lifetime of a 0.25pm NMOS transistor will be estimated. First, a criterion for the lifetime of the devices has to be chosen: Here the lifetime of a transistor was defined as the time after which the threshold voltage of the device shifted lOmV from its initial value. Then, six fresh devices were stressed with drain avalanche hot electrons at differ¬ ent drain voltages and at maximum substrate currents. The results are plot¬ ted in Fig. 74. 120- lsub/21.6uA ISüb=-29 7yA lsub=-38 6MA / 100- g ^ub^O.OMA 80- A ^ Threshold Voltage Shift: > ^' ./ CK NMOS. (LAA/)=0.25m/5|J £ '' 60- (J % Of' dox=6nm, Vds=0.1V > n 40- lsub=-1 6.3[jA 20- sub=-11.6[jA 0--F 0 5000 10000 15000 20000 25000 30000 35000 t[s] Fig. 74 : Threshold voltage shifts for different stress i onch turns: The indicated substrate currents are the f,^ at the beginning of the stress. The measured threshold voltage shifts shown in Fig. 74 are linearly dependent on the stress time. The data was therefore fitted with a straight line. Then the time to achieve a I OmV threshold degradation was extrapo¬ lated. The following table summarizes the values for different stress condi¬ tions: Vds [VJ vgjvi Lubmi ImAI Id [mA] x[s] 34 1 56 38 5 1.27 560 3.3 1.60 29.7 1.27 915 3.2 1.52 20.9 1.10 1854 3.1 1.54 16 3 1.17 5957 30 1.50 116 108 11757 Table I Stic s s conditions and time nadcd to shift the tin ahold \ oltaqe 1 OmV pom its initial \ cilue 110 Generation of Oxide Charges and Interface Traps 1E+9-J, 10 years / Dependence of Lifetime 1E+8-f Maximum Drain Voltage: 0 on Isub - NMOS: (LAA/)=0.25/5|j IE+7- 7 (AVth=10mV): 1E+4- Vth=Vg@td=1E-7*W/L=2pA, : i NMOS (LW)=0.25p/5jJ 1E+6^ Vd=0.1V dox=6nm p — 1E+5 T=298K 1E+3- ^ 1E+4 1E+3- 1E+2-^ / 1Ef2- - 1E+1- / slope=-2.9 / 1 Pj.1 —j 1E+0 " ' ' ' I1"" ' I"'1 .. ' | ' ' (m ' ' i 1E+0 1E-1 1E-2 1E-3 1E-4 1E-5 0,2 0.25 0.3 0.35 0.4 0.45 0.5 I.sul/Td 1/Vds [1/V1 -2.9 drain Fig. 75 : Device lifetime rK/n,|,'" (left) und estimation of the maximum voltage for a device lifetime of 10 years (right). Finally, in Fig. 75 the values given in Table 1 were plotted in the ways as described by Eq. (63) and (66). Because of the power law Eq. (63) the data can be fitted in a loglog plot by a straight line whose slope is equal to the exponent in Eq. (63) (compare with the left part of Fig. 75). The lifetime of the NMOS transistors of this technology can then be estimated by the fol¬ lowing formula: T = 4.5 • 10"2 • W • I\Q • Tj;} [A, cm, s] (67) The slope of the Tld/W versus I^i/Id plot is exactly the same as the one given in Fig. 8 of reference [87]. This is a proof of the technology indepen¬ dence of the critical energy for the generation of an interface trap. In the right part of Fig. 75 the estimation of the maximum allowed drain voltage for a 10 year lifetime is shown: At a drain voltage of 2.2V the threshold voltage will shift in a worst-case condition (i.e. at maximum sub¬ strate current) lOmV from its initial value. This estimation is the so-called Takeda model (see reference [771). Generation of Interface Traps after Fowler-Nordheim Stress 111 Generation of Interface Traps after Fowler-Nordheim Stress In the previous sections of this chapter, the transistors were always degraded by drain avalanche hot electron (DAHC) stress. Tn this final sec¬ tion, another injection mechanism shall be discussed: Fowler-Nordheim tun¬ neling. This current is exploited, for example, to erase a cell in electrically erasable read only memories (EEPROMs). Generation of interface and oxide traps during the erase of cells has therefore important implications for the reliability of these devices. Furthermore, Fowler-Nordheim tunneling currents are often used in time dependent dielectric breakdown (TDDB) studies of thin oxides. A good understanding of the involved mechanisms is therefore desired. Degradation due to Fowler-Nordheim injection was studied in NMOS transistors with a large gate area (20pm x 5pm) to minimize edge effects. Two transistors were stressed injecting a gate current of 200pA. One transis¬ tor was stressed with electrons tunneling form the gate through the triangu¬ lar barrier into the accumulated substrate. (A negative voltage relative to the substrate was applied to the n+-polygate.) In a second experiment the other transistor was stressed with electrons tunneling form the channel into the gate. In this case a positive voltage relative to the substrate was applied to the gate. 6.0E-7- 6 0E-7- Vth=1E-7*W/L=0 4MA Vth=1 E-7*W/L=0.4|jA 5 5E-7- Vds=50mV Vds=50mV 5 0E-7 pesh ^ 4 5E-7-3 nine hours 4 0E-7 '3 5E-7- 3.0E-7 3 0E-7- NMOS (L7W)=20m/5|J NMOS (LAA/)=20p/5p 2 5E-7- dox=6nm dox=6nm 2.0E-7 2 0E-7- !gs=200pA lgs=-200pA T=298K 1.5E-7-I 1 5E-7- T=298K 1.0E-7 1 OE-7 'i ) j""i "| ri—111'T'i'n'nj'nTi'i 11 i"i'"j"i"]"i"i|'1111 j 11 CD CM CO ^ LO CD 00 CD Is- cD-i-cum^-Lncoh-cocnK 5 CD CD CO CO CO CO CO CO Ocococococococococo0 O O O O O O o o o ooooooooo Vgs [V] Vgs [V] Fig. 76 : Threshold voltage shifts after Fowler-Nordheim injection. Left picture: electron injection from the gate. One hour of FN-stress with Eb=-200pA between measurements. Right picture: electron injection from the channel. Nine hours of FN-stress with 1^=- 200pA between measurements. 112 Generation of Oxide Charges and Interface Traps — oc-o oc-o j«««Ü? tune hour NMOS NMOS (LyW=20iJ/5|j) 5E-8t » (LAV=20|j/5m) • dox=6nm » 4E-8- 4E-8- . dox=6nm . Ig=200pA 4E-8- lg=-200pA f=1MHz /**"*V* 3E-8- nine hours 3E-8- f=1MHz tau=100ns tau=100ns <ù**mmx Y 3E-8- 2E-8- T=298K «* VI T=298K 2E-8- 1 - ^ * T 1E-8- 2E-8- fresh 1E-8- *^ *^ ^ //cv/; 0E+0- ï 5E-9- A * 1 0E+0- .. ., '" " ' -1 c-o i 11 1 1 ''v-M"'l1-llll)|li ! ! r ,^.1—» 111 11 j 11 | | 1 1 1 1 | 1 1 1 | , 1 M -1 -0 5 0 0.5 -35-3-25-2-15-1-050 05 Vbs [V] Vbs [V] Fig. 77 : Increase of the number of interface traps due to Fowler-Nordheim stress. Left picture: electron injection from the gate. Between to measurements was one hour of FN- stress with 7=-200pA. Right picture: electron injection from the channel. Between the two measurements was a nine hour FN-stress with /?=200pA. Figure 76 compares the shifts in threshold voltages: For electrons tunnel¬ ing from the gate into the substrate, the degradation of the threshold voltage after nine hours of stress was about 74mV. In the case where electrons tun¬ nel from the inversion channel into the gate, the shift was about ten times smaller (AVth~8mV). A similar behavior shows the charge pumping currents in Fig. 77: When electrons tunneled from the gate into the substrate, a huge amount of addi¬ tional acceptor interface traps were generated. On the other hand, in the case where electrons tunneled from the inversion layer into the gate the increase of the interface state density remained small. This effect can be explained by the following model (compare with "The Various Components of the Fowler-Nordheim tunneling current" on page 70): Electrons tunneling from the n+-polygate into the p-substrate can transfer their energy to a deep valence-band electron creating a hot hole. The hot hole is then accelerated to the interface by the negative gate voltage where it breaks a chemical bond thus creating a trap [41. In the other case where channel electrons from the inversion layer tunnel through the triangu¬ lar barrier into the n+-polygate no hot holes are generated near the interface and therefore the damage (bond breaking) is much smaller. This mechanism is sketched in Fig. 78. Generation of Interface Traps after Fowler-Nordheim Stress 113 h+-poly * .' P-Si nApgA P-Si Accumulation Inversion Fig. 78 : Band diagram of a NMOS transistor in accumulation (left), in inversion (cen¬ ter) and a model of the trapping process of an electron in an acceptor type interface state when a positive gate voltage is applied (right). In the left part of Fig. 78, the band diagrams of the MOS diode during Fowler-Nordheim tunneling of electrons from the gate and from the channel are shown. In the first case the impact ionization of tunneling electrons takes place near the channel-oxide interface. The holes are attracted by the nega¬ tive gate bias and can create an acceptor trap. In the second case only a few tunneling electrons damage the interface during tunneling. In the right part of Fig. 78, the trapping of electrons while rising the gate voltage is sketched: When the threshold voltage is measured after the stress, the generated acceptor traps catch an electron during the increase of the gate voltage and screen the electric field in consequence. The build-up of an inversion channel near the drain junction starts at a higher gate voltage and therefore, the drain current increases later, i.e. the threshold voltage shifts to more positive values. 6 Negative Transconductance of MOS Transistors In this chapter the degradation of the field-effect mobility of electrons in the inversion channel of a NMOS transistor shall be discussed. Especially at low temperature, this degradation can lead to a negative transconductance at high normal fields. Although the effect is already known for quite a long time in the literature, the underlying physical reason still remains unclear. However, it seems that at higher field and at lower temperature the channel electrons are closer to the interface where they suffer stronger interface scat¬ tering. The decrease of the mobility is so pronounced that in the linear region the drain current decreases with increasing gate voltage. The goal of this chapter is first to confirm experimentally the effect at state-of-the art NMOS transistors. Then, various possible physical reasons will be checked and a phenoinenological mobility model that is able to qual¬ itatively describe the measurements will be proposed. Finally, some classi¬ cal and quantum mechanical calculations will bring a deeper understanding of the physics involved in this effect. Decreasing Drain Current at Increasing Gate Voltage Already in 1966, Fang and Howard [88] found that the field-effect mobil¬ ity of electrons in a n-type inversion layer has an anomalous effect at high normal fields (>lMV/cm). They discovered that the transconductance (i.e. dId/dVa) becomes zero for an oxide field of about 3MV/cm. They observed 115 116 Negative Transconductance of MOS Transistors also that the field at which the maximum drain current can be measured increases with temperature. For room temperature they measured an oxide field of 6MV/cm. At liquid helium temperature, on the other hand, the nec¬ essary oxide field was only 2.5MV/cm. Furthermore, Fang and Howard noted that samples on Si(l 11) surfaces did not show this anomaly. Later, in 1987 C. Hu [89] and in 1990 T. Hori [90] confirmed the negative transcon¬ ductance effect in their articles. Hori studied nitrided-oxides and found that nitridation avoids negative transconductance. To confirm the effect the transfer characteristic at 77K and at room tem¬ perature was measured. Figure 79 compares both curves: Whereas at 77K a clear reduction of the drain current with increasing gate voltage above about VçS=2.5V can be observed, at room temperature the drain current decreases at a much higher gate voltage of about Vgs=4.5V. In contrast to C. Hu et al. [89] who found a diminution of the drain cur¬ rent only at 77K, in this measurement also at room temperature a decrease could be measured. The required field was exact the value that Fang and Howard published in their original work (see reference [88]). OC-D- NMOS: (L/W)=5|i/5,u T=77K 7E-6- dox=6nm ^ 6E-6- 5E-6-T 4E-6- < T^300K 3E-6- 2E-6- 1E-6- ld@Vds=10mVandT=77K OE+CH o ld@Vds=10mVandT=300K ~1 P~R • I CD i i , i | | j j i i | ii j i i i | i i i 0.5 1.5 2 2.5 3.5 4.5 vgs [V] Fig. 79 : Measured transfer characteristic at 298K and at 77K. With the following simple reflections the problem can be considered from a different point of view: As shown for example in reference [351, the drain Decreasing Drain Current at Increasing Gate Voltage 117 current of a NMOS transistor in the linear region can be approximated by /^^K(^K. With Eq. (68) the transconductance gm can be calculated dl, w rr duJV^ — r p =—tt_ ( .y (69) ^«( »v+ cly~ I 8s th The channel width W, channel length L, gate-oxide capacitance Cox, drain-, gate- and threshold-voltage Vds, V„s and Vth and the effective mobil¬ ity pn are all positive values. However, the mobility pn is at increasing gate voltage a monotonously falling function (compare with Fig. 61 in "Defini¬ tion and Measurement of Mobility" on page 82). Its derivative is therefore negative. Thus, if the absolute value of the derivative of the mobility at some gate voltage times the gate drive (Vgs-Vth) becomes larger then the mobility at that gate voltage, then the drain current starts to decrease gm<0 <=> pn(Vg^+d^^(V^VtiyO . (70) At 77K, the scattering of channel electrons with phonons is reduced com¬ pared to the scattering at room temperature. The mean free path of the chan¬ nel electrons is therefore longer. Looking at the microscopic definition of the mobility (see Eq. (48) in chapter "Definition and Measurement of Mobility" on page 82) it is clear that at low temperature the mobility of the channel electrons is higher. On the other side, it is known that at lower tem¬ perature the electrons travel closer to the interface. The electrons suffer therefore more surface scattering at low temperature than at high tempera¬ ture. Both things together lead to a higher absolute value of the derivative of the mobility at 77K compared with the value at room temperature. The decrease of the drain current starts therefore at lower gate voltage. In the following sections some possible reasons for the effect will be experimentally checked. 118 Negative Transconductance of MOS Transistors Is there a Correlation between the Negative Transconductance and the Fowler-Nordheim Current? It was observed that at room temperature the decrease of the drain current starts at an oxide field of about 6MV/cm. This is also the onset point of the Fowler-Nordheim tunneling. It was therefore supposed that electrons tun¬ neling out of the channel reduce the mobile inversion charge and, as a result, the drain current decreases. To check this hypothesis drain and gate current of the same transistor were measured at 77K and at room temperature. In Fig. 80 the results are plotted. It can be observed that despite the earlier decrease of the drain cur¬ rent at low temperature the tunneling current at that temperature was smaller compared with the current measured at room temperature. Quantitatively, at 77K the decrease of the drain current at VSS=3.5V compared with the maxi¬ mum at about VSS=3V was 3.3pA. This has to be compared with the tunnel¬ ing current of only 15pA at Vffs=3.5V. 4.0E-4- NMOS: (L/W)=0.25,u/5ia 3.5E-4-J d=60Â, Vd=50mV 3.0E-4 ld@298K 2.5E-4- ld@77K 2.0E-4- 2 1.5E-44 1.0E-4- 1.0E-11 // lg@298K 5.0E-5- 4 lg@77K -5.0E-12 0.0E+0 wÊmr WMMH »w»l>)^ny>lwv.it 0 0.5 1.5 2 2.5 3.5 Vgs [V] Fig. 80 : Negative transconductance and Fowler-Nordheim current at 77K and at room temperature. In further experiments the decrease of drain current and the gate currents were compared for eight different oxide thicknesses at room temperature. O O O o Results for the 15A, 30A, 40A and 50A oxides are shown in Fig. 81 and the curves of the 60A, 100A, 150A and 250A oxides are presented in Fig. 82. and the Fowler-Nordheim Is there a Correlation between the Negative Transconductance Current? 119 -1E-5 9E-6- -IE-5 4 0E-6- .»"t = NMOS (L7W)=100m/100(j NMOS (L/W)=1[J/0 5(J 8E-6^ -1E-6 3 5E-6- ,rt>* ,o^f-1E-G *sP" dox=15Ä 7E-6 dox=30À -1E-7 3 0E-6 6E-6 -1E-8 o' -1E-7 Vds=30mV Vds=30mV 2 5E-6- 5E-6 V -1E-9 > 5 * T-298K g > 2 0E-6- T=298K ^ -1E-8 4E-6-: -1E-10 » * I «' 3E6- 1 5E-6- I„ ~ 1E-9 -1E-11 2E-6- 1 OE-6-^ -1E-12 1-1E-10 1E-6- 5 OE-7^ OEt-0 -1E-13 OOE+O-i »»tM»|*tM*t*T 1E-11 -1E-6 -1E-14 -0 5 05 1 5 0 5 0 05 1 15 2 25 3 Vgs [V] Vgs [V] 9E-6- 1 2E-5- NMOS NMOS (L/W)=200li/200 (L/W)=100li/100|J 8E-6- dox=50A 7E-6- dox=40 Vds--30mV 6E-6- Vds=30mV f\\ 5E-6 5f T=298K T=298K 2 4E-6-^ 3E-6 2E-6-3 1E-6 OE+0 i|imni[i|i|iiiii|<,,i| -0 5 0 0 5 1 15 2 2 5 3 3 5 0 05 1 15 2 25 3 3 5 4 Vgs [V] Vgs [V] Fig. 81 : Negative transconductance at lower oxides thicknesses. 1 2E-5- 7 50E-6 7 OOE-i 6 50E-6- 6 00E-6 10 11 12 13 14 15 vgs [V] Fig. 82 : Negative transconductance at higher oxides thicknesses. 120 Negative Transconductance ofMOS Transistors In the transistors with ultrathin oxides (dox<50À) the electrons are able to tunnel directly already for very low oxide fields. In these transistors the tun¬ neling current reached the order of magnitude of the decrease in drain cur¬ rent. However, in the transistors with thicker oxides (Fig. 82) the decrease in drain current is initially higher than the tunneling current. For example, the drain current in the transistor with dox=250 decreased at 18V about 37nA compared with its maximum value at about 17.2V, but only a gate current of 0.1 nA was measured. In this transistor the carriers tunneling out of the channel contribute only to a small amount to the negative transconductance effect. In conclusion, it cannot be excluded that in transistors with oxides thinner than 60 tunneling currents contribute the main part to the decrease in the drain current. In transistors with thicker oxides, however, the influence of the Fowler-Nordheim current on the decrease of the drain current at high normal fields is initially small. In addition, it was observed that at 77K the possible effect of electrons tunneling out of the channel is still smaller. Therefore, tunneling cannot explain the negative transconductance effect! Influence of Poly-Gate Depletion It was supposed that the polygate depletion effect could cause the decrease in drain current with increasing gate voltage. In the chapter "Mea¬ surement of Polysilicon Doping and Gate Depletion Effects" on page 56 the polysilicon depletion effect was estimated for a NMOS transistor with an oxide thickness of 6nm. In Fig. 44, the voltage drop over the polysilicon was plotted. At a gate voltage VSS=4.5V the voltage drop is approximately 0.3V This value can be compared for example with Fig. 82 and it can be seen that the voltage drop should be about 2V to account for the negative transcon¬ ductance effect. Furthermore, T.P. Ma [91] et al. used aluminum gates when they com¬ pared transconductance in FETs with nitride as a gate dielectric with the transconductance in MOSFETs. They found that the transconductance becomes zero at a high normal field independent of the dielectric material. To sum up, polysilicon depletion lowers the transconductance of the tran¬ sistor, but it cannot explain the full effect. Influence ofInterface Traps 121 Influence of Interface Traps It was supposed that charge trapping could cause the decrease in drain current with increasing gate voltage. The trapped charge would then screen the gate voltage, lowering the transconductance, though charge trapping would probably only lead to a saturation and not to a decrease of the drain current. To examine the influence of interface traps on the decrease of the drain current, a lot of additional interface states were generated in the following experiment: The interface of a NMOS transistor was stressed under Fowler- Nordheim current injection. Electrons tunneled from the gate into the sub¬ strate creating electron-hole pairs by impact ionization. The holes were accelerated to the interface and generated many acceptor traps. By measur¬ ing the charge pumping currents the increase of the interface state density could be estimated. The measured curves are plotted in the left part of Fig. 83. When the gate voltage is raised, channel electrons are trapped in the gen¬ erated acceptor traps. This negative charge at the interface screens the gate voltage and shifts therefore the threshold voltage of the NMOS transistor to more positive values. The measured threshold voltages are shown in the right picture of Fig. 83. 1 20E-7- 5£_7. Vth=1 E-7*W/L=0 1 A NMOS: (LVW>10|j/10m |J J'es,f ~*afte> Vds=50mV , _ 5h 1.00E-7 ' ..^*""**' dox=6nm #•**% 1E-7- 8 00E-8 lg=-1nA f=1MHz, * > 6.00E-8 3f tau=100ns a. *P"*^ 5h T=298K 1E-8- aftet 2 4 00E-8 % ^ NMOS (L7W)=10p/10M 2 00E-8H v. dox=6nm * .,_ X1 0.00E+0 Jf lg=-1nA fresh 1E-9- T=298K 5E-10- -2.00E-8 ' ' iii111111 111—i 11 i i 11 11 i 111—i i | 11 i 11 i T 3 5-3-25-2-15-1-050 05 Vbs[V] Vgs [V] Fig. 83 : The increase in charge pumping currents (left picture) and in threshold voltage (right picture) due to the generation of interface traps. Distance between two measure¬ ments is one hour of FN stress with source and drain floating and Igs=-lnA. (The elec¬ trons tunneled therefore from the gate contact through the gate oxide into the semiconductor.) 122 Negative Transconductance ofMOS Transistors Figure 84 shows the effect of the additional traps on the drain current. It can be observed that the maximum drain current decreases with increasing stress time. Furthermore, it can be seen that the gate voltage necessary to cause a decrease in the drain current shifts to more positive values. The measured effects can be explained as follows: The trapping of elec¬ trons into the generated acceptor interface states causes a screening of the gate potential at low normal fields. As a result, compared with the unstressed transistor a reduction of the number of carriers in the conduction channel occurs. This reduction is significant because the carrier concentra¬ tion is of the same order as the interface trap density at low normal fields . Therefore, at low normal fields the transconductance is reduced. At high normal field, however, the trapped carriers only represent a small portion of the total inversion channel charge. The screening effect of the trapped charge seems to cause a smoothening of the electronic interface, which results in a reduction of the interface roughness scattering. Therefore, the transconductance increases at high normal fields after trap generation [91]. On the other hand, the additional Coulomb scattering at the charged inter¬ face states reduces the effective channel mobility of the inversion charge, which causes a net reduction of the drain current. In conclusion, it can be said that the interface traps lower the drain cur¬ rent due to a reduction in mobility, but transconductance at high normal fields increases. Consequently, interface traps do not explain the decrease in drain current at high normal fields. Fig. 84 : Shift of the maximum drain current to more positive values after generation of interface traps. The Role of Surface Roughness Scattering 123 The Role of Surface Roughness Scattering In this section the influence of surface roughness scattering on the nega¬ tive transconductance effect will be discussed. Intuitively, it is clear that increasing the normal electric field at the silicon surface diminuishes the mean distance of the inversion charge to the interface. The probability of a scatter event increases and mobility decreases. On a microscopic scale, the roughness of the Si-Si02 interface is very small. For example, transmission electron microscope (TEM) pictures pre¬ sented in reference [83] show an atomically flat interface. On a larger scale, however, the interface is not ideally flat, but shows irregularities (steps) with a typical amplitude of one or two atomic layers. If surface roughness scattering is the reason for the negative transconduc¬ tance effect, the point of maximum drain current should depend on the effective channel length. To check this effect, the transfer characteristics of NMOS transitors with various gate length were measured. As can be seen in the left part of Fig. 85, the effect depends in fact in the suspected way: In longer channels the probability of some surface steps in the channel increases and therefore, the effect of surface roughness scattering is stronger than in shorter channels. 1.01 - 4.48E-4- NMOS: dox=6nm Vds=50mV 1- 4.46E-4- T=298K. 4.44E-4- 0.99- 4.42E-4- < | 0.98- T3 4.40E-4- 0.97- (L/W)=0.25n/5n 4.38E-4- o (L/Vv>0,5|i/5,u 0.96- 4.36E-4- • (L/W)=2n/5n 0.95- T-TT-p-T-T-p 4.34E-4- 3.2 3.4 3.6 3.8 4 4.2 4.4 4.5 5 Vgs [V] Vgs [V] Fig. 85 : Influence of effective channel length: Normalized drain currents for three dif¬ ferent gate lengths (left) and negative transconductance dependence on drain voltage (right). 124 Negative Transconductance of MOS Transistors A second hint that this hypothesis is true is given by the fact that the nor¬ mal field at which the transconductance becomes zero depends on the drain voltage: For higher drain voltages the effective channel length is reduced and the probability that electrons see some macroscopic roughness in the channel is reduced. This effect is shown in the right part of Fig. 85. On the other hand, it was reported in reference [92] that the influence of surface roughness scattering on the channel electron mobility is weaker than theoretically predicted. The authors of this article measured interface rough¬ ness by atomic force microscopy, calculated the theorectical mobility and compared it with the measured mobility values. They found that the high- field mobility of an intensionally roughened sample with a mean height of 4.3nm (that is more then 20 times the normal asperity) decreased only about 20%, which is much less than the theroretically predicted value. In short, roughness scattering is one of the most probable physical grounds for the negative transconductance at high normal fields. However, some doubts do remain. A Simple Mobility Model In this section a phenomenological mobility model for electrons in the inversion channel of a NMOS transistor will be proposed. This mobility model is based on well-known dependencies of the mobility on the effective electric field. Interestingly, this simple model is able to simulate most of the previously measured effects at least qualitatively. It is known that three different scattering mechanisms lower the effective mobility: Coulomb, surface and phonon scattering. Ferry (see reference [93]) showed theoretically that the surface roughness contribution is propor¬ tional to E~" and the bulk phonon contribution goes with E4/3. Schwarz and Russek [74] were the first who proposed the E~1/3 dependence. Hori [90] and Takagi et al. [94] measured the E"~ dependence at 77K and the E dependence at 298K. It is known that at low temperatures the channel elec¬ trons are nearer to the interface. Probably, at 77K surface roughness scatter¬ ing gives the main contribution, whereas at room temperature bulk phonon scattering predominates. To account for the interface trapped charge a Cou- A Simple Mobility Model 125 lomb scattering term proportional to T/Qtr was introduced. This term is however not really necessary. It only serves to simulate the effect of the increased high field transconductance of a stressed device. Surface roughness, phonon and Coulomb scattering can be combined with the help of the Matthiessen rule. The temperature effect can be taken into account by dividing (multiplying) the phonon (Coulomb) mobility by T. The proposed dependence of the effective channel mobility on the effective electric field Eeff, the temperature T and the trapped charge Qtr looks as fol¬ lows: ^ptix^pfn* )~ efl\ eff> ) £1/3. r E2 ÇJ v {)y eft i eff j_ Mlr a b T -c where a=10 b=4.6 10 and c=4-10 are , fitting parameters. The drain current can approximately be calculated with Eq. (68). At each Vgs, the effective normal electric field in the inversion layer Eeff was defined as follows (see reference [89]) ^J2 E ~ f± eff P cjv„- where O « ox[Vg,-yth)Vth) ifVgs»Vlh" ygs^vth (72) and Qb=^4-q-Nmb-ESi-^h Iff and The simple expressions for the inversion and depletion charges, Qinv and Qb, are approximative^ correct in strong inversion. With the model expressed in Eq. (71) the mobility was calculated at room temperature and at 77K in dependence on the effective electric field. The results were plotted in Fig. 86. The calculated values are reasonable and comparable to measurements. (See for example the measured mobilities in reference [89].) 126 Negative Transconductance ofMOS Transistors 1200- Universal Electron Mobility 1000- 800H 600 400- T=298K 200- 0- I ' I ' ] j 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Eeff [MV/cm] Fig. 86 : Calculated electron mobilities for 77K and 298K obtained through Eq. (71). 1.0E-5- 7 0E-6- T=77K 6 0E-6- 5 0E-6-: r? 4 0E-6- 5.0E-6- dox=30A 2 3.0E-6- 4 0E-6^ 3 0E-64 Vds=30mV 2.0E-6- 2.0E-64 dox=60A T=298K 1 0E-6- 1.0E-6-Ë Vds=10mV 0.0E+0 0 0E+0 ' I'l'Ti i p-rrrpr i|i'n"'|'i'iTi'|'i'iri|'irii|iiTt'|Ttîr|TTTT[iiii|i 0 05 1 1.5 2 2.5 0 0.5 1 1 5 2 2.5 3 3.5 4 4.5 5 Vgs [V] Vgs [V] 1 9E-5- dox=250A Vds=30mV T=298K 3.5 4 10 11 12 13 14 15 16 17 1£ Vgs [V] Vgs [V] Fig. 87 : Calculated drain currents for different oxide thicknesses, temperatures and after interface trap generation obtainedfrom Eqs. (68), (71) and (72). With this simple mobility model the negative transconductance effect can be qualitatively modeled at 77K, at room temperature, for different oxide thicknesses and after interface trap generation. In the upper left picture of Classical Calculations 127 Fig. 87 for example, the drain current in dependence of the gate voltage for a 30 thick oxide was calculated. For a gate voltage above 2.3V the transcon¬ ductance becomes negative. Comparing this with the measured drain current of a NMOS transistor with a 30A thick gate oxide shown in Fig. 81, it can be seen that the gate voltage for the maximum drain current is about 2.5V and the measured current is slightly smaller than in the simulation. In the upper right picture of Fig. 87, the drain currents for a 60A oxide was calcu¬ lated at 77K and at 300K. The same model (Eq. (71)) with the same param¬ eters was used as before. Comparing this with the measured curves shown in Fig. 79, it can again be seen that gate voltages and drain currents do agree quite well. Next, in the lower left picture, the drain current of an unstressed and a stressed transistor were calculated. A correct tendency can be stated by comparing with the measurements shown in Fig. 84. Finally, the drain current was calculated for a thick oxide of 250 and plotted in the lower right picture of Fig. 87. This should be compared with the measurement in Fig. 82. A good agreement can be found. In conclusion, despite the simplicity of the used mobility model the nega¬ tive transconductance effect could be simpulated and the values are in a good agreement with the smeasurements. Furthermore, it must be stressed that the 1/E2 dependence of the inversion layer mobility on the effective electric field is responsable for the decrease in the drain current at high nor¬ mal fields. This was justified by Ferry [93] with surface roughness scatter¬ ing. Classical Calculations In the previous section the quadratic field dependence of the surface- roughness contribution to the mobility was used to model the negative transconductance effect. Ferry [93J noted in his article that the surface- roughness scattering is too weak at room temperature and has too strong a dependence upon Eeff to impact the inversion layer mobility. Only at very high normal fields (Eeff>106V/cm) the surface-roughness contributes to the inversion layer mobility. To get a feeling of the distribution of the electric field in the measured transistors, some classical calculations are presented in this section. First of all, the equations for the charge and field distribution in a MOS diode (p- 128 Negative Transconductance ofMOS Transistors substrate) were solved. Polysilicon depletion, interface traps and oxide charges were neglected. The channels of the transistors that were used throughout this work are implanted to reduce short channel effects. To calculate a realistic example, the following channel implantation profile (typical for a NMOS transistor) was assumed (see Fig. 88): 6E+17- 5E+17- j^4E+17-H £ ^ 3E+17- fc—J < Channel Implantation: Z 2E+17- NMOS: dox=6nm 1E+17-4 J Nsub=4E15/cm3 0 rn | i it | i i i | i i i | i i i p i i j i i i p i 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 z[pm] Fig. 88 : Channel implantation of a typical NMOS transistor. At zero applied gate voltage, the Fermi level is constant through the MOS structure. The band bending caused by the channel implantation, was first calculated solving the charge neutrality condition: p(z) = N:(z) + n(z) (73) From this equation the energy difference between valence band edge and Fermi level Ev(z) was received. Next, Poisson's equation was solved for dif¬ ferent surface potentials \\fs Ev(z)ß] E,+Ev(z)\ß dhff ..1 MM _ lN„-e >(#_! Nc-e (74) dz2 Then the surface electric field Fs was calculated by building the first Classical Calculations 129 derivative of the electric potential \|/ at the silicon surface. Finally, the gate voltage Vg for the different surface potentials \|/s was calculated using the boundary condition for the normal component of the electric field at the interface (£sFs=£oxFox) * ' (75) vg _ s L'o\ Ys The results are shown in Fig. 89. 1 2- 1 2- Surface Field 1- 1- .,,i^^'-^-"^ NMOS: dox=6nm «#*>•" „0 8- 08- £ ü 5 06- '06- E Q. U- 04 0 4- Surface Potential 02 02- / NMOS: dox=6nm 0 pxr-T ,-p-n-rjT-, . i | l l . I | . . 111 i ii 111111111111111111111111 0 05 1 15 2 25 3 0 05 1 15 2 2.5 3 35 Vg[V] vg[V] Fig. 89 : Calculated surface field and surface potential for different gate voltages. When Fig. 89 is compared with Fig. 79 where the negative transconduc¬ tance was measured at 77K and at room temperature, it can be seen that the surface electric field at the point where the drain current starts to decrease is above lMV/cm. Ferrys condition for a strong influence of surface scattering is therefore fulfilled. Next, the potential and the charge distribution in the semiconductor was calculated for the depletion (see Fig. 90) and strong inversion case (see Fig. 91). The electron and hole densities were calculated with: n,(z) = Nc-e-\WV.e*W (76) n t{z) = Nv-eE^ß.e^ß 130 Negative Transconductanc e ofMOS Transistors 0 07- Potential Distribution Field Distribution in depletion in depletion NMOS dox=6nm NMOS dox=6nm 0 002004006008 0 1012014016 0 002004006008 010 12014016 z[|jm] z[um] 3 5E+6- 3 5E+17- d P) 3 0E+6- 3 0E+17- ;= 2 5E+6- | 25Ef17-4 t= 2 0E+6- 0E+17- 01 >2 c •g 1 5E+6- electron distribution c 1 5E+17-I 0) c hole distribution 2 1 0E+6- in depletion » 1 0E+17- o in ^ depletion NMOS dox=6nm 5 0E+16- NMOS dox=6nm 0 0E+0- 0 0E+0- tftfm pn-rnr 'I'"!' 'I' 0 002004006008 010120 14016 0 0 02 0 04 0 06 0 01 012014016 z[um] z [pm] Fig. 90 : Distribution of electric peld (a), potential (b), electrons (c) and holes (d) in sil¬ icon for a low surface potential. Potential Distribution Field Distribution in strong inversion in strong inversion NMOS dox=6nm NMOS. dox=6nm 0 002004006008 0 10 120 140 16 0 0 0200400600801012014016 z[pm] z[um] 1 6E+20- 3 5E+17- 1 4E+20- 57 0E+17- d E m3 .o 1 2E+20- 2 5E+17- T— | >1 0E+20- "20E+17- C 8 0E+19- o a electron distribution c 1 5E+17 6 0E+19- o c •a hole distribution o in inversion o 1 0E+17 S 4 0E+19- strong o o £ in strong inversion NMOS dox=6nm ö 2 0E+19- 5 0E+16- NMOS dox=6nm 0 0E+0- 0 0E+0- TT"!1'1!111!111!111!1 0 0 020040060 01 012014016 0 002004006008 01012014016 zfom] z [um] Fig. 91 : Distribution of electric field (a), potential (b), electrons (c) and holes (d) in sili¬ con for a high surface potential. Quantization of the Inversion Layer 131 It is interesting to see how rapid the electric field drops in the semicon¬ ductor at high gate voltages (see Fig. 91b). Classically, the highest electron density in the inversion channel is at the interface (see Fig. 91c). Quantum mechanical calculations in the next section will show, however, that the average distance of the inversion charge from the interface amounts to some nanometers. Quantization of the Inversion Layer The electric field in an inversion layer is strong enough to produce a potential well whose width in the direction perpendicular to the surface (z- axis) is small compared to the wavelengths of the carriers. As a result, quan¬ tum effects occur. The energy levels of the electrons are grouped in sub- bands, each of which corresponds to a quantized level for motion in the z- direction. The motion in the plane parallel to the surface remains continuous (see the original article of Stern and Howard, reference [95]). When Fang and Howard [88] published the first paper on the negative transconductance effect in 1966, they noted that samples on Si(l 11) surfaces did not show a decreasing drain current at high fields. They supposed that this can be explained in terms of the quantization of the electron states in the narrow potential well. In contrast to the (111) surface the six ellipsoids of constant energy are in (100) not equivalent in the presence of a channel field. It is expected that the electric field removes their degeneracy. The two whose ellipsoids long axes lie along the [001 ] direction lie lower in energy than the other four. Fang and Howard supposed that at low fields only these two energy ellipsoids are populated, but at higher fields also the other four ellipsoids become occupied. (It will be shown later in Fig. 94 that at room temperature this is not true.) Furthermore, they assumed that because of the higher effective mass of the upper energy bands, the mobility of electrons in this band is lower and thus the drain current decreases. The argumentation of Fang and Howard seems not very conclusive because also with increasing temperature the higher energy band becomes occupied, but then the electric field needed to reach negative transconduc¬ tance increases too. The population of the higher band can therefore not be the main reason for the effect. 132 Negative Transconductance ofMOS Transistors A possible influence on the negative transconductance effect could be the average distance zav of the inversion layer from the interface. Stern [96] has calculated zav for various temperatures and inversion charges. He showed that for lower temperatures and higher fields the average distance of the inversion layer from the interface is reduced. The lowest subband is always the closest to the interface. There the carriers experience the strongest effects of surface roughness scattering. Another interesting aspect was also shown by Stern in reference [96]: The fraction of carriers in the lowest sub- band is higher at lower temperatures and at higher fields. Unfortunately, inversion layers of samples on (111) surfaces have a similar dependence of the average distance of the inversion layer from the interface and an even higher fraction of electrons in the lowest subband. The distance of the inver¬ sion layer from the interface and the fraction of carriers in the lowest sub- band can therefore not explain why the negative transconductance effect on (111) samples could not be seen. To gain insight in the quantization of the inversion layer, some quantum mechanical calculations will be presented in this section. The calculation is based on three major approximations: It is assumed (i) that the effective- mass approximation is valid, (ii) that the envelope wave function vanishes at the surface and (iii) surface states can be neglected. The electronic wave function for the z'th subband is the product of the Bloch function at the bottom of the conduction band and an envelope func¬ tion [95]. The envelope function l^(z) satisfies the Schrödinger equation §t^^p-[v(:)~E\C^ (77) where m3 is the effective mass for motion perpendicular to the surface. For bound solutions of this equation it is required that Q(oo)=^(0)=0. This boundary condition is not exactly correct, but the deviations from the cor¬ rect values are thought to be small for silicon [96]. Each eigenvalue Ej found from the solution of (77) is the bottom of a continuum of levels called a sub- band. The potential energy V(z) was calculated from the distribution of the electrostatic potential (J)(z) Quantization of the Inversion Layer 133 With this definition the energy zero was set at the conduction band edge. (|)(z) is the solution of Pois son's equation d2(j) PdeiM-^ff(z) = (79) dz2 The charge density p(z) is the sum of the depletion and the inversion charge. The inversion charge is given by the occupation of each subband times the probability distribution of the subband. The carrier concentration Nj in the z'th subband is given by ( 47i-nvimdkT E< exp (80) h2 kT where md is the density-of-states mass per constant-energy ellipsoid in the k-space for motion parallel to the surface, and nv is the degeneracy factor which gives the number of equivalent valleys. For inversion layers on silicon surfaces of general orientation, there are three sets of values of m3i, mdi, and nvi; each set has its own ladder of subbands. On the other side, the high- symmetry surface (111) has only one ladder of subbands, since all the val¬ leys have the same orientation with respect to the surface. The (100) surface has two ladders of subbands: The lower ladder, that is the ladder whose low¬ est subband has the lowest energy, arises from the two ellipsoids whose long axes lie along the [001] direction. The valley degeneracy is 2, the effective mass m3 is mp0.916nio and the density of mass per valley md is mt=0.19m0. The values for the four valleys whose effective mass ellipsoids lie in the (100) plane are mt=0.19m0 and mcp().417m0. If we assume that each acceptor is ionized in the depletion layer and the depletion charge is constant for a distance zd from the surface and then goes abruptly to zero, Pdep(z) *s given by -q-Nv 0 The depletion-layer thickness zd was calculated with the classic expres¬ sion - I2£Ä Zd > (82) Ä For the boundary conditions of Poisson's equation it was assumed that the electric field (-d(j)/dz) vanishes for large z and that its value at the surface is Fs. The Schrödinger and Poisson equations were solved in a self-consistent way, i.e. a distribution of the potential energy V(z) was found that fulfills both equations at the same time. For the calculations a MATLAB program was written. The program worked as follows: First, the Fermi level Ef in the bulk was calculated for a constant acceptor concentration NA=2-1016cm~3. The Fermi energy Ef equals 0.16eV when the zero of energy is set at the valence band edge. Next, Poisson's equation for a classic charge distribution (compare with reference [35]) d2§ q = p„o-r*-i-«„o-p (83) was solved. For the numeric solution of this equation the 'Numerov' method was used. This technique is suited for boundary problems of the form y"=f(x,y) with y(xmin)=a and y(xmax)=b. The interval between xmax and xmin is then divided into N-l equal intervals of width h=(xmax-xmin)/(N-1) and starting at one boundary the solution of y"=f(x,y) is found with the fol¬ lowing recursion formula ' * ' - y(x + h) = 2y(x) y(x -h) + ^ [>•' (x - /z) +10 v' (x) + V (x + + 0(h6 ). (84) 12 h)} After the calculation of the electrostatic potential (j)(z), the Fermi energy was recalculated because the zero of the potential energy was defined in Eq. (78) to be at the conduction band edge: Ef=())(0)-Ecr+0.16 eV. Quantization of the Inversion Layer 135 With the potential energy V(z) and a guessed value of Ej for the eigenen- ergy of the z'th subband Schrödinger's equation was solved with the 'Numerov' method starting at some zmax in the bulk were the electrostatic potential is zero. Because Ej was guessed the resulting wave function Ç(z) normally does not fulfill the boundary condition Ç(0)=0. With a bisection method Ej was changed and Ç(z) was recalculated until the wave function vanished at the interface. Then, the wave function was normalized, i.e. each Çj was divided by the square of Ç, integrated over the whole interval. With this procedure the wave functions, eigenenergies and carrier concentrations were calculated for the eight subbands with the lowest energies of the two ladders of subbands of a (100) oriented silicon surface inversion layer. Then the inversion charge distribution was calculated with the wave func¬ tions and carrier concentrations per subband and a new electrostatic poten¬ tial was received solving Eq. (79). The new potential energy was then corrected with = vJn+l) Vn)+^-Kt(n)-vJ»A . (85) For low and medium surface potential this technique leads to a good con¬ vergence: A potential energy V(z) that fulfills Poisson's and Schrödinger' equation self-consistently was found after three loops. The errors between two runs were very small: I(|)in-(j)outkl0 V. However, for high fields, espe¬ cially when the conduction band edge is bent under the Fermi level, conver¬ gence was difficult to reach. After four loops with a factor of 0.05 instead of 0.1 in Eq. (85) the maximum difference l<|>in-(|>out'max was smaller then 0.14V for a surface potential (J)(0)=1.017V Finally, the average distance of all the inversion-layer electrons from the surface was calculated with "£Nrjz-Çf(z,)dz (86) 2NrC(z) In the following part some results will be presented for low and high sur¬ face potential. 136 Negative Transconductance ofMOS Transistors Wave function Wave function x -| g4 (2,1 ) x10 (2,2) 0 03 0 04 0 01 0 02 0 03 0 04 z[um] Wave function Wave function x104 (2,3) X10 (2,4) 2 1 /"S. ^v >-* 0 '\ ,/H\-/ -1 -2 0 01 0 02 0 03 0 04 0 02 0 03 0 04 2 [um] z [um] Fig. 92 : Wave functions of the first four eigeristates of the higher ladder at low surface potential (f(0)=0.144V. The average distance was calculated to be zav=lL9nm. «/ave function Wave function X104 (2,1) x10 (2,2) 2 1 /v 0 1 _ V(z) at 057 eV 2 Ef=0 , 0 01 0 02 0 03 0 04 0 03 0 04 z [Mm] Wave function x10 (2,3) x10 Wave function (2,4) 0 03 0 04 0 03 0 04 Fig. 93 : Wave functions of the first four eigenstates of the higher ladder at high surface potential Potential inversion Energy x10 Charge 015 ^emmm»»—«——s»«««»««»«« ^ ./ 01 "e y.3 / 0 05 I —« 816eV 1 V(z)atEf=0 01 02 03 0 01 0 02 0 03 0 04 0 05 z[um] z[um] Energylevels Occupation 012 1400 01 p-Si(lOO) 1200 T=300K 1000 ?0 08 ;oo6 g 600 0 04 o 400 0 02 I 200 0 0 ladder 1 ladder 2 ladder 1 ladder 2 94 : Distribution the Fig. of potential energy and the inversion charge, eigenenergies and carrier concentration of the various subbands of the two ladders at a low surface potential (j)(0)=0.144V Potential Energy x10 Inversion Charge 1 2 o > |3 Ä06- o > 04 02 V(z) at E =0 057 eV 0 0 01 02 03 0 01 0 02 0 03 0 04 0 05 z[um] z [Mm] Energylevels x10" Occupation 0 35 03 p-Si(1 10) rqi T=300K 0 25 > a 02 >. oi | 015 UJ o2 01 0 05 111 0 III ladder 1 ladder 2 ladder 1 ladder 2 95 : Distribution the Fig. of potential energ\ and the inversion charge, eigenenergies and carrier concentration the of various subbands of the two ladders at a high surface potential Figure 92 shows the first four wave functions of the higher ladder for a low surface potential (j)(0)=0.144V. The wave functions can be compared with the first four wave functions of the higher ladder at a high surface potential (j)(0)=1.017V, shown in Fig. 93: The higher the field the nearer to the interface are the various subbands. The wave functions are similar to the Airy functions, which are the exact solution for a triangular shape of the potential energy. In Fig. 94 and Fig. 95, the distribution of the potential energy (= shape of the conduction band edge), the inversion charge distribution, the eigenener¬ gies and the occupation of the eight subbands of each of the two ladders are compared for low and high field. It can be seen that at higher fields the aver¬ age distance zav of all the inversion-layer electrons is reduced. For a surface potential of 0.144V zav is about 11.9nm, whereas for (j)(0)= 1.017V it is only about 3.9nm. The occupation histograms show that for low and medium fields the low¬ est subband of the second ladder contributes the most to the inversion charge. At first sight this seems not reasonable, because the energy of the lowest subband of the second ladders lies higher than the energy of the low¬ est subband of the first ladder. But, when we remember how the carrier con¬ centration was calculated in Eq. (80), it can be seen that the higher occupation is due to the fourfold degeneracy and the higher density-of- states effective mass of the second ladder. At very high fields the occupation of the two lowest subbands is similar and it is supposed that at even higher fields the occupation of the lowest subband will become the highest. Unfor¬ tunately, the calculation did not converge at these fields. Because temperature plays a major role in the occupation of the sub- bands, wave functions, eigenstates and carrier concentration were calculated for T=77K as well. To account for the increased bandgap at low tempera¬ ture, E„ was assumed to be 1.17eV (see reference [35]). Additionally, tem- perature affects the effective density of states in the conduction band Nc and in the valence band Nv. For the dependence on T the following expressions given in [35] were assumed: 3/2 f A 3/2 , 0xl/3 2/3 ^\ 2iZ'\tn,m:\ kT '/'"/ kT N =12- Nv=2, (87) fr Quantization of the Inversion Layer 139 Potential 8 Inversion Energy x 10 Charge 1 zav=4.4nm y* <|>(0)=0.939V 08 ,06 i=0 6 o 04 Jo 4 0 2r 02 V(z)atE=-0 191 eV 0 0 — 0 02 04 06 0 0 01 0 02 0 03 0 04 0 05 2 [Mm] z[nm] Energylevels Occupation 015- S 01 • 0 05 level 1 level 2 ladder 1 ladder 2 Fig. 96 : Influence of temperature: Distribution of the potential energy and the inversion charge, eigenenergies and carrier concentration of the various subbands of the two lad¬ ders at a medium surface potential (M0)=0.939V and at 77K. Potential Inversion Energy x10 Charge 1 2 1 ^(0)=1.165V zav=4.1nm 1 5 08 "e Ä06 5. 1 > 04 05- 02 V(z) at E =0 035 eV 0 02 04 06 08 0 0 01 0 02 0 03 0 04 0 05 z[um] z[um] Energylevels Occupation 015 0 05 level 1 ladder 1 ladder 2 Fig. 97 : Influence of temperature: Distribution of the potential energy and the inversion charge, eigenenergies and carrier concentration of the various subbands of the two lad¬ ders at a high surface potential (j)(0)=1.165V and at 77K. 1.40 Negative Transconductance ofMOS Transistors In Fig. 96 and Fig. 97, the low temperature results are shown for a medium ((()(0)=0.939V) and for a high surface potential of 1.138V It can be observed that at low temperature the fraction of electrons in the first ladder is higher than in the second ladder. Furthermore, at 77K a much higher sur¬ face potential is required to generate an inversion layer. Even at a surface potential of 0.939V, the peak inversion charge is less than 1- LO"8 C/m^ (compared with 6T04 C/nr at room temperature). Fang and Howard [88] observed that inversion layers on a Si(l 11) surface do not show a decrease of the drain current at high normal fields. To investi¬ gate quantum effects in a Si(lll) inversion layer the first eight wave func¬ tions of the eight lowest subbands, the eigenenergies, carrier concentrations per subband were also calculated self-consistently. The Si( 111 ) surface has only one ladder of subbands, since all the valleys have the same orientation with respect to the surface. Fig. 98 and Fig. 99 show that the fraction of car¬ riers in the lowest subband increases with increasing field. Interesting is that in a Si(lll) n-channel inversion layer the average distance of all the inver¬ sion-layer electrons from the surface is higher than in a Si(100) n-channel inversion layer for the same normal field. If the values are significant, the interface roughness scattering would be slightly lower in Si(l 11). Potential Energy x10 Inversion Charge 0 15 (|>(0)=0.144V > > 0 05 V(z)atE.=-0 816eV 01 02 03 0 01 0 02 0 03 0 04 0 05 z [Mm] z[Mm] Energylevels Occupation 2000 H T=300K 1500 1 c o m m §•1000 IL o mm o II 500 lllii... 2 3 4 5 6 7 3 4 5 6 7 subband subband Fig. 98 : Distribution of the potential energy and the inversion charge, eigenenergies and carrier concentration of the various subbands in the inversion layer of a Si(lll) surface at a low surface potential (f>(0)=0.144V Quantization of the Inversion Layer 141 Potential Energy x10 Inversion Charge 12 <|>(0)=l.0l7V zav=4.5nm .06 04 02 _ V(z) at E=0 056 eV 0 o 01 02 03 0 0 01 0 02 0 03 0 04 0 05 z[um] z[pm] Energylevels x10 Occupation 0 35 T=300K a-4 4 5 6 7 4 5 6 7 subband subband Fig. 99 : Distribution of the potential energy and the inversion charge, eigenenergies and carrier concentration of the various subbands in the inversion layer of a Si(lll) sur¬ face at a low surface potential In conclusion, it is supposed that the deeper reason for the decrease of the drain current at high normal fields in Si(100) probably lies in the occupation of the two ladders of subbands. The self-consistent calculations described above showed that at room temperature the total electron concentration of the four energy valleys whose effective mass ellipsoids lie in the (100) plane is higher than in the two valleys with the lowest energy. At very high fields a tendency of a higher occupation of the two lower valleys could be observed. At 77K the lowest subband contributes the most to the carrier concentration already at medium normal fields. It seems that the higher the occupation rate of the lowest subband the higher is the scattering and the lower the mobility. Interface roughness scattering remains a possible mechanism that could explain the effect: The lowest subband of the first ladder is the nearest to the interface. Interface scattering of electrons in this subband is therefore assumed to be stronger than for electrons in higher subbands. Another possi¬ ble scattering mechanism is the transfer of electrons from the lowest sub- band of the first ladder into a subband of the second ladder by means of a surfon. Scattering within a ladder cannot take place, because the wave func¬ tions of a ladder are orthogonal, the overlap of the wave functions vanishes 142 Negative Transconductance ofMOS Transistors and the transition probability is zero [97]. In Si(lll) inversion layers only one ladder of subband exist. The mean distance of the inversion charge from the interface is higher and interaction with the interface is probably reduced. Additionally, the above mentioned scattering mechanism where electrons of one ladder are transferred into the other does not exist in Si(lll), because all wave functions of the subbands are orthonormal and the transition probability vanishes. Conclusion The negative transconductance effect was experimentally verified in NMOS transistors with different oxide thicknesses on Si(100). Different possible physical reasons were checked: First, it was supposed that elec¬ trons tunneling out of the channel cause the decrease in drain current. The Ö measured gate currents reached in thin oxides (dox<60A) in fact the order of magnitude of the decrease in drain current. In transistors with thicker oxides, however, the contribution of the tunneling current remains small. Then, the effect of the polygate depletion was estimated and was found to be too small to explain the decrease in drain current. Interface traps, on the other hand, have a contrary influence on the high field transconductance: The trapped charge gives rise to a smoothening of the interface and rough¬ ness scattering is reduced. This effect was also confirmed in the literature: Hori [90J and Ma [91J found that nitridation of the gate oxide raises the high field transconductance and explained it by the higher number of interface traps. In a further step, the influence of channel length was investigated. It was found that in transistors with a longer channel the drain current decreases earlier. This can be explained by the higher density of surface asperities in longer channel devices. (A possible type of roughness could be a monoatomic step of the Si substrate.) Surface roughness scattering leads to a E'2 dependence of the mobility on the effective field [93]. With this dependence a mobility model was constructed that qualitatively fits all mea¬ sured effects. Finally, the quantization of the interface charge was calcu¬ lated. Here, it was found that in Si(100) the higher occupation of the lowest subband at high fields and low temperatures leads to a higher contribution of surface roughness scattering. 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Sei. 57, pp. 218-228, (1976) >. « k - . &r-* \ , »1 tel et* %r * List of Symbols and Abbreviations A Ampere 1A=J C/s  Angstrom lÀ=lO"10m a particle radiation containing helium cores a thermal expansion coefficient a impact ionization coefficient ac alternating current Ai Airy function, solution of w"-zw=0 Al aluminum AFM atomic force microscope Au gold B boron Bi Airy function, solution of w"-zw=0 ß particle radiation consisting of electrons ß ß=kT/q c speed of light in vacuum c=2.998• 10 m/s cm centimeter C Coulomb=unit of electric charge C Celsius y photon Cgs gate-to-source capacitance C^c gate-to-channel capacitance CHC channel hot carrier stress CI chlorine CMOS complementary MOS technology Cp poly depletion capacitance CP charge pumping Cr chromium Cu copper CV capacitance-voltage CVD chemical vapor deposition DAHC drain avalanche hot carrier stress dc direct current D(E) density of states at energy E DIL dual-in-line package 154 List of Symbols and Abbreviations Dit density of states at the interface DLTS deep-level transient-spectroscopy oxide thickness DRAM dynamic random access memory E electric field e" electron Ea activation energy F,c energy at the conduction band Eeff effective electric field Ef Fermi energy bandgap energy in silicon at 300K Ö Ee=1.12eV e.g. for example E maximum electric field in m the channel of a MOSFET energy at the valence band £o permittivity in vacuum £0=8.85-10 F/m dielectric cox constant of an oxide £OX=3.9-£0 F electric field in the gate oxide EEPROM electrically erasable programmable read only memory EPROM erasable programmable read only memory b,s surface field es dielectric constant of silicon £s=11.9-£0 ESD electrostatic discharge ESR electron spin resonance eV electron volt leV=1.602-10"19 J F electric field F Farad 1F=1C/V f frequency FN Fowler-Nordheim F, electric field over the oxide ox gate *i critical energy for impact ionization effective barrier height at the interface FET field effect transistor FR4 epoxy based PCB material Es electric field at the surface GID grazing incidence diffraction GIDL gate induced drain leakage current §m transconductance gm=dId/dV^s GND ground potential GTO gate turn-off thyristor ggNMOS grounded-gate NMOS transistor H hydrogen h Planck constant h=6.62-10"34 Js h hour HF hydrofluoric acid HP Hewlett-Packard Hz herz=unit for frequency I current Ib substrate current IC integrated circuit I charge pumping current Id drain current rddq quiescent power supply current I gate current ö IGBT insulated gate bipolar transistor r current 1sub substrate j current density J current density J Joule 1J=1N-Im K Kelvin K potassium k kilo kg kilogram k=kB Boltzmann constant kB=l .38-10"23J/K X failure rate X thermal conductivity X mean free path of electrons L transistor length LDD lightly doped drain Li lithium m meter m3 effective electron mass in z-direction ...Mi- ,^-i m milli=l0 156 List of Symbols and Abbreviations m effective mass m0 electron rest mass m0=0.91-10 kg md density of states mass mhh heavy hole effective mass mj longitudinal effective mass, mp0.916-m0 mih light hole effective mass mt transversal effective mass, mt=0.J9-m0 microti 0"6 p=pn electron mobility M mega=10 MOS Metal oxide semiconductor MTTF mean time to failure n=ne electron concentration n nano=I0 n+ with donators highly doped silicon N nitrogen N Newton lN=lkg-m/s" Na sodium NA acceptor concentration NA" ionized acceptor concentration 10 n Nc effective density of states in conduction band Nc=2.8-10 cm"-' N(E) supply function n; intrinsic carrier concentration iij=l .45-1010 cm"3 at T=300K Ni carrier concentration in the z'th subband N; inversion inv charge Nit interface trap density Np polysilicon doping concentration nPo electron concentration in p-Si in thermal equilibrium NPN bipolar transistor with p-type base Nv effective density of states in valence band Nv= l.04-10I9cnT3 NMOS n-channel metal oxide semiconductor transistor Nsub bulk charge O oxygen P phosphorus P hole concentration p pko=10-12 p+ with acceptors highly doped silicon n 3.141 Pb lead PCB printed circuit board PMOSFET p-channel metal oxide semiconductor field effect transistor PpO hole concentration in p-Si in thermal equilibrium poly polysilicon p-Si p-type silicon, i.e. with acceptor ions doped silicon PSG phosphor silicate glass electric potential VI/ x electric at the surface s potential Qb bulk charge Qd total charge on the gate electrode QM quantum mechanics Qn mobile channel charge Qtr trapped charge q elementary charge q=1.602-10"19C Pdep depletion charge Pinv inversion charge S second G capture cross section SCR semiconductor controlled rectifier SEM secondary electron microscopy Si silicon Si(100) silicon surface with crystal orientation (100) Si(lll) silicon surface with crystal orientation (111) Si02 silicondioxide SMD surface mount device Sn tin SRAM static random access memory t time T temperature T relaxation time X lifetime T le electron temperature TEM transmission electron microscopy Ti titanium 158 List of Symbols and Abbreviations TDDB time dependent dielectric breakdown UV ultraviolet V Volt 1V=1J/C v voltage v potential energy Vbs bulk to source voltage vd drift velocity vdd power supply voltage Vds drain to source voltage Vdsat saturation voltage of a MOSFET v gate to source vgs voltage Vfb flat-band voltage V vox voltage drop over gate oxide v v ss ground voltage vth threshold voltage Vth thermal velocity, vth=107 cm/s Ç wave function W watt lW=U/s W transistor width WKB Wentzel-Kramers-Brillouin 7 average distance of the inversion charge from the interface zd depletion-layer thickness Zn zinc Curriculum Vitae I was born in Zurich on April 14, 1970. After finishing high school at Kantonsschule Kollegium Schwyz (Matura Typ A) in 1990,1 studied phys¬ ics at the Swiss Federal Institute of Technology (ETH) in Zurich. In spring 1995,1 received the M.S. degree (dipl. phys. ETH). Then I joined the Reli¬ ability Laboratory of ETH Zurich where I started my Ph.D. In 1998, I changed to the Integrated Systems Laboratory. Presently, I work for the European research project ESPRIT SUBSAFF). The goal of the project is to understand, measure and simulate the substrate potential lifting during inductive load switching of a smart power chip. 159